Commit graph

2339 commits

Author SHA1 Message Date
Stefan Roese
d1c3b27525 ppc4xx: Big cleanup of PPC4xx defines
This patch cleans up multiple issues of the 4xx register (mostly
DCR, SDR, CPR, etc) definitions:

- Change lower case defines to upper case (plb4_acr -> PLB4_ACR)
- Change the defines to better match the names from the
  user's manuals (e.g. cprpllc -> CPR0_PLLC)
- Removal of some unused defines

Please test this patch intensive on your PPC4xx platform. Even though
I tried not to break anything and tested successfully on multiple
4xx AMCC platforms, testing on custom platforms is recommended.

Signed-off-by: Stefan Roese <sr@denx.de>
2009-09-11 10:35:58 +02:00
Stefan Roese
0b34dbbd0b ppc4xx: Fix compilation warning in 4xx miiphy.c
This patch fixes the following compilation warning:

miiphy.c: In function 'emac4xx_miiphy_read':
miiphy.c:353: warning: dereferencing type-punned pointer will break
strict-aliasing rules

Signed-off-by: Stefan Roese <sr@denx.de>
2009-09-10 14:38:17 +02:00
Matthias Fuchs
99bcf14d55 ppc4xx: Allow overwriting pci target registers for all 4xx boards
This patch adds the CONFIG_PCI_4xx_PTM_OVERWRITE option and replaces
the ugly 'if defined(BOARD1) || ... || defined(BOARDn)' construct
in 4xx pci code.

When CONFIG_PCI_4xx_PTM_OVERWRITE is defined the default ptm register
setup can be overwritten through environment variables ptm1la, ptm1ms,
ptm2la and ptm2ms to do application specific pci target BAR configuration.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-09-10 14:38:17 +02:00
Kumar Gala
6c97a20d0b ppc/85xx: Introduce RESET_VECTOR_ADDRESS to handle non-standard link address
Some board ports place TEXT_BASE at a location that would cause the
RESET_VECTOR_ADDRESS not to be at 0xfffffffc when we link.  By default
we assume RESET_VECTOR_ADDRESS will be 0xfffffffc if the board doesn't
explicitly set it.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Wolfgang Denk <wd@denx.de>
2009-09-09 21:04:47 -05:00
Kumar Gala
c348322ac7 ppc/85xx: Clean up do_reset
There is no reason to do a run time check for e500 v1 based cores to
determine if we have the GUTs RSTCR facility.  Only the first generation
of PQ3 parts (MPC8540/41/55/60) do not have it.  So checking to see if
we are e500 v2 would miss future parts (like e500mc).

Just change this to be ifdef'd based on CONFIG_MPC85{40,41,55,60}.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-08 13:47:18 -05:00
Poonam Aggrwal
21170c80a8 ppc/85xx/86xx: Bug fix: call to puts in probecpu() moved to checkcpu().
While in probecpu() UART is still not initialized.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-08 09:10:08 -05:00
Poonam Aggrwal
f8027f6b47 ppc/85xx/86xx: Device tree fixup for number of cores
Fixing the number of cores in the device tree based on the actual number of
cores on the system.  With this same device tree image can be used for dual
core and single core members of otherwise exactly same SOC.

For example:
* P2020RDB and P2010RDB
* P1020RDB and P1011RDB
* MPC8641D and MPC8641

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-08 09:10:08 -05:00
Poonam Aggrwal
58442dc01e ppc/85xx,86xx: Handling Unknown SOC version
Incase the system is detected with Unknown SVR, let the system boot
with a default value and a proper message.

Now with dynamic detection of SOC properties from SVR, this is necessary
to prevent a crash.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-08 09:10:08 -05:00
Kumar Gala
3e7b6c1f2d ppc/8xxx: Refactor code to determine if PCI is enabled & agent/host
Refactor the code into a simple bitmask lookup table that determines if
a given PCI controller is enabled and if its in host/root-complex or
agent/end-point mode.

Each processor in the PQ3/MPC86xx family specified different encodings
for the cfg_host_agt[] and cfg_IO_ports[] boot strapping signals.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-08 09:10:07 -05:00
Kumar Gala
5052a771cf ppc/85xx: Cleanup makefile and related optional files
Cleaned up cpu/mpc85xx/Makefile to use CONFIG_* for those obvious cases
we have like PCI, CPM2, QE.  Also reworked it to use one line per file
for everything and sorted in alphabetical order.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-08 09:10:07 -05:00
Kumar Gala
c725908681 ppc/85xx: Fix bug in setup_mp code
Its possible that we try and copy the boot page code out of flash into a
DDR location that doesn't have a TLB cover it.  For example, if we have
3G of DDR we typically only map the first 2G.  In the cases of 4G+ this
wasn't an issue since the reset page TLB mapping covered the last page
of memory which we wanted to copy to.

We now change the physical address of the reset page TLB to map to the
true physical location of the boot page code, copy and than set the
TLB back to its 1:1 mapping of the reset page.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-08 09:10:06 -05:00
Kumar Gala
c2287af155 ppc/85xx: Add a simple function to search the TLB
Allow us to search the TLB array based on an address.  This is useful
if we want to change an entry but dont know where it happens to be
located.

For example, the boot page mapping we use on MP or the flash TLB that
we change the WIMGE settings for after we've relocated.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-08 09:10:05 -05:00
Kumar Gala
26f4cdba6b 85xx: Add support for setting IVORs to fixed offset defaults
In future Book-E implementations IVORs will most likely go away and be
replaced with fixed offsets.  The IVPR will continue to exist to allow
for relocation of the interrupt vectors.

This code adds support to setup the IVORs as their fixed offset values
per the ISA 2.06 spec when we transition from u-boot to another OS
either via 'bootm' or a cpu release.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-08 09:10:05 -05:00
Dipen Dudhat
da1cd955df ppc/85xx: Fix up eSDHC controller clock frequency in the device tree
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-08 09:10:04 -05:00
Kumar Gala
2abbd31da6 ppc/8xxx: Remove ddr_pd_cntl register since it doesn't exist
The ddr_pd_cntl isn't defined in any reference manual and thus we wil
remove especially since we set it to 0, which would most likely be its
POR value.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-08 09:10:04 -05:00
Dipen Dudhat
6b9ea08c50 ppc/85xx: Use CONFIG_FSL_ESDHC to enable sdhc clk
Enable eSDHC Clock based on generic CONFIG_FSL_ESDHC define instead of a
platform define.  This will enable all the 85xx platforms to use sdhc_clk
based on CONFIG_FSL_ESDHC.

Signed-off-by: Gao Guanhua <B22826@freescale.com>
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-08 09:10:02 -05:00
Wolfgang Denk
0052a051f6 Merge branch 'master' of git://git.denx.de/u-boot-i2c 2009-09-07 23:20:04 +02:00
Wolfgang Denk
3ea43ff773 Merge branch 'master' of git://git.denx.de/u-boot-arm 2009-09-07 23:12:46 +02:00
Eric Millbrandt
5da71efa18 Reset i2c slave devices during init on mpc5xxx cpus
Reset any i2c devices that may have been interrupted during a system reset.
Normally this would be accomplished by clocking the line until SCL and SDA
are released and then sending a start condtiion (From an Atmel datasheet).
There is no direct access to the i2c pins so instead create start commands
through the i2c interface.  Send a start command then delay for the SDA Hold
time, repeat this by disabling/enabling the bus a total of 9 times.

Signed-off-by: Eric Millbrandt <emillbrandt@dekaresearch.com>
2009-09-06 11:26:04 +02:00
Sandeep Paulraj
cf463091bc ARM: DaVinci: DaVinci DM365 SOC specific code
This patch adds support for DaVinci DM365 SOC.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
2009-09-05 13:48:07 +02:00
Anton Vorontsov
001d615681 mpc83xx/serdes: License cleanup: remove "All Rights Reserved" notice
"All Rights Reserved" conflicts with the GPL.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
2009-09-04 23:02:04 +02:00
Kumar Gala
d72871e138 arm: Remove -fno-strict-aliasing
-fno-strict-aliasing is hidding warnings.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-04 22:15:53 +02:00
Kumar Gala
d6281ff0cc ppc: Remove -fno-strict-aliasing
-fno-strict-aliasing is hidding warnings.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-09-04 22:15:48 +02:00
Graeme Russ
ed7a1b681d i386: Replace [read, write]_mmcr_[byte, word, long] with memory mapped structure
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-09-04 21:56:45 +02:00
Graeme Russ
d754902409 i386: Misc PCI fixups
Change PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY (Originally done in
commit ff4e66e93c, regressed by commit 6d7f610b09)

Cast PCI_ROM_ADDRESS_MASK to u32

Wrap probe_pci_video() call inside #ifdef CONFIG_VIDEO

Change call to pci_find_class() to pci_find_devices(). This is based on a
patch submitted on 1st March 2007 (Patch that fixes the compilation errors
for sc520_cdp board) by mushtaq_k

This patch requires that PCI_VIDEO_VENDOR_ID and PCI_VIDEO_DEVICE_ID be
specified in the board config file.  Dummy values have been added for the
SC520 CDP board to enable compilation, but since I do not have one of these,
I do know what the values should be

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-09-04 21:52:52 +02:00
Graeme Russ
04ff9ab158 Fix sc520 timer interrupt generation
The current implementation has the timer being started before the interrupt
handler is installed. It the interrupt occurs before the handler is
installed, the timer interrupt is never reset and the timer stops

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-09-04 21:51:56 +02:00
Graeme Russ
cfb3a736ff i386: Change inline asm global symbols to local
gcc 4.3.2 optimiser creates multiple copies of inline asm (who knows why)
Remove use of global names for labels to prevent 'symbol already defined'
errors

Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
2009-09-04 21:49:48 +02:00
Mike Frysinger
9c46e71af2 Blackfin: use scratch pad for exception stack
If the memory layout pushes the stack out of the default DCPLB coverage,
the exception handler may trigger a double fault by trying to push onto
the uncovered stack.  So handle the exception stack similar to the kernel
by using the top of the scratch pad SRAM.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-09-02 05:58:38 -04:00
Prafulla Wadaskar
49d2cb4d61 arm: Kirkwood: add SYSRSTn Duration Counter Support
This feature can be used to trigger special command "sysrstcmd" using
reset key long press event and environment variable "sysrstdelay" is set
(useful for reset to factory or manufacturing mode execution)

Kirkwood SoC implements a hardware-based SYSRSTn duration counter.
When SYSRSTn is asserted low, a SYSRSTn duration counter is running.
The counter value is stored in the SYSRSTn Length Counter Register
The counter is based on the 25-MHz reference clock (40ns)
It is a 29-bit counter, yielding a maximum counting duration of
2^29/25 MHz (21.4 seconds). When the counter reach its maximum value,
it remains at this value until counter reset is triggered by setting
bit 31 of KW_REG_SYSRST_CNT

Implementation:
Upon long reset assertion (> ${sysrstdelay} in secs) sysrstcmd will be
executed if pre-defined in environment variables.
This feature will be disabled if "sysrstdelay" variable is unset.

for-ex.
setenv sysrst_cmd "echo starting factory reset;
		   nand erase 0xa0000 0x20000;
		   echo finish ed sysrst command;"
will erase particular nand sector if triggered by this event

Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
2009-09-01 22:34:03 +02:00
Albin Tonnerre
9453967e28 Add support for the Calao SBC35-A9G20 board
The Calao SBC35-A9G20 board is manufactured and sold by Calao Systems
<http://www.calao-systems.com>. It is built around an AT91SAM9G20 ARM SoC
running at 400MHz. It features an Ethernet port, an SPI RTC backed by an onboard
battery , an SD/MMC slot, a CompactFlash slot, 64Mo of SDRAM, 256Mo of NAND
flash, two USB host ports, and an USB device port. More informations can be
found at <http://www.calao-systems.com/articles.php?lng=en&pg=5936>

Signed-off-by: Albin Tonnerre <albin.tonnerre@free-electrons.com>
2009-09-01 22:13:37 +02:00
Ilya Yanok
10bc241dfc imx27lite: add support for imx27lite board from LogicPD
This patch adds support for i.MX27-LITEKIT development board from
LogicPD. This board uses i.MX27 SoC and has 2MB NOR flash, 64MB NAND
flash, FEC ethernet controller integrated into i.MX27.

Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Acked-by: Wolfgang Denk <wd@denx.de>
2009-09-01 22:10:55 +02:00
Timur Tabi
05f6f66474 85xx: Improve MPIC initialization
The MPIC initialization code for Freescale e500 CPUs was not using I/O
accessors, and it was not issuing a read-back to the MPIC after setting
mixed mode.  This may be the cause of a spurious interrupt on some systems.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:43 -05:00
Poonam Aggrwal
a713ba926b 85xx: Added single core members of FSL P1xx/P2xx processors series
P1011 - Single core variant of P1020
P2010 - Single core variant of P2020

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:41 -05:00
Mingkai Hu
76b474e2f5 85xx: Add L2SRAM Register's macro definition
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:41 -05:00
Kumar Gala
ec79d33b2c 85xx: Move to a common linker script
There are really no differences between all the 85xx linker scripts so
we can just move to a single common one.  Board code is still able to
override the common one if need be.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:39 -05:00
Poonam Aggrwal
87c7661b42 85xx: Added P1020 Processor Support.
P1020 is another member of QorIQ series of processors which falls in ULE
category. It is an e500 based dual core SOC.

Being a scaled down version of P2020 it has following differences:
- 533MHz - 800MHz core frequency.
- 256Kbyte L2 cache
- Ethernet controllers with classification capabilities.
Also the SOC is pin compatible with P2020

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:39 -05:00
Poonam Aggrwal
0e870980a6 8xxx: Removed CONFIG_NUM_CPUS from 85xx/86xx
The number of CPUs are getting detected dynamically by checking the
processor SVR value.  Also removed CONFIG_NUM_CPUS references from all
the platforms with 85xx/86xx processors.

This can help to use the same u-boot image across the platforms.

Also revamped and corrected few Freescale Copyright messages.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:38 -05:00
Poonam Aggrwal
18bacc2027 8xxx: Refactored common cpu specific code for 85xx/86xx into one file.
Removed same code pieces from cpu/mpc85xx/cpu.c and cpu/mpc86xx/cpu.c
and moved to cpu/mpc8xxx/cpu.c(new file)

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:38 -05:00
Kumar Gala
73aacc5228 86xx: Remove redudant PLATFORM_CPPFLAGS
For historic reasons we had defined some additional PLATFORM_CPPFLAGS like:

PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1
PLATFORM_CPPFLAGS += -DCONFIG_MPC8641=1

However these are all captured in the config.h and thus redudant.  Also
moved common 86xx flags into cpu/mpc86xx/config.mk.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:37 -05:00
Kumar Gala
53efa1f1ac 85xx: Remove redudant PLATFORM_CPPFLAGS
For historic reasons we had defined some additional PLATFORM_CPPFLAGS
like:

PLATFORM_CPPFLAGS += -DCONFIG_E500=1
PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1

However these are all captured in the config.h and thus redudant.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-28 17:12:37 -05:00
TsiChung Liew
f6a309080b ColdFire: Fix compile warning messages
Change %08lX to %08X in board.c. Remove unused variable
'oscillator' in mcf5227x/cpu_init.c and 'scm2' in
mcf532x/cpu_init.c. Provide argument type cast in
drivers/dma/MCD_dmaApi.c.

Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
2009-08-26 03:44:31 -05:00
Eric Millbrandt
307ecb6db0 Add support for USB on PSC3 for the mpc5200
Support USB on PSC3 on the mpc5200.  Before this patch, enabling USB support
would reconfigure PSC4 and PSC5 to USB.  The mpc5200 does not support USB
enabled on both the standard USB port and PSC3.  This patch masks the
appropriate bits when enabling USB.

Signed-off-by: Eric Millbrandt <emillbrandt@dekaresearch.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Acked-by: Remy Bohmer <linux@bohmer.net>
2009-08-25 12:57:55 +02:00
Wolfgang Denk
963f2f6117 Prepare 2009.08-rc3
Update CHANGELOG, minor Coding Style cleanup.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-08-22 23:27:26 +02:00
Wolfgang Denk
f772acf8a5 ARM: compiler options cleanup - improve tool chain support
For some time there have been repeated reports about build problems
with some ARM (cross) tool chains.  Especially issues about
(in)compatibility with the tool chain provided runtime support
library libgcc.a caused to add and support a private implementation
of such runtime support code in U-Boot.  A closer look at the code
indicated that some of these issues are actually home-made.  This
patch attempts to clean up some of the most obvious problems and make
building of U-Boot with different tool chains easier:

- Even though all ARM systems basicy used the same compiler options
  to select a specific ABI from the tool chain, the code for this was
  distributed over all cpu/*/config.mk files.  We move this one level
  up into lib_arm/config.mk instead.

- So far, we only checked if "-mapcs-32" was supported by the tool
  chain; if yes, this was used, if not, "-mabi=apcs-gnu" was
  selected, no matter if the tool chain actually understood this
  option.  There was no support for EABI conformant tool chains.
  This patch implements the following logic:

  1) If the tool chain supports
	"-mabi=aapcs-linux -mno-thumb-interwork"
     we use these options (EABI conformant tool chain).
  2) Otherwise, we check first if
	"-mapcs-32"
     is supported, and then check for
	"-mabi=apcs-gnu"
     If one test succeeds, we use the first found option.
  3) In case 2), we also test if "-mno-thumb-interwork", and use
     this if the test succeeds. [For "-mabi=aapcs-linux" we set
     "-mno-thumb-interwork" mandatorily.]

  This way we use a similar logic for the compile options as the
  Linux kernel does.

- Some EABI conformant tool chains cause external references to
  utility functions like raise(); such functions are provided in the
  new file lib_arm/eabi_compat.c

  Note that lib_arm/config.mk gets parsed several times, so we must
  make sure to add eabi_compat.o only once to the linker list.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Cc: Dirk Behme <dirk.behme@googlemail.com>
Cc: Magnus Lilja <lilja.magnus@gmail.com>
Cc: Tom Rix <Tom.Rix@windriver.com>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Acked-by: Sergey Kubushyn <ksi@koi8.net>
Tested-by: Magnus Lilja <lilja.magnus@gmail.com>
Tested-by: Andrzej Wolski <awolski@poczta.fm>
Tested-by: Gaye Abdoulaye Walsimou <walsimou@walsimou.com>
Tested-by: Tom Rix <Tom.Rix@windriver.com>
Tested-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-08-21 23:11:53 +02:00
Kumar Gala
e393e2e9bc 85xx: Fix addrmap to include memory
When we init the addrmap based on the TLB we will not end up getting
the TLB that covers memory if we are using SPD.  The reason is we
haven't relocated at the point that we setup the memory TLB and thus it
will not get setup in the addrmap.

Instead we can just walk over the TLB array after we've relocated and
see all the TLBs that have been set and use that information to populate
the initial addrmap.  By doing this we insure that we get the TLB
entries that cover memory.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-08-14 17:42:05 -05:00
Wolfgang Denk
53cc18c71b Minor coding style cleanup.
Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-08-10 10:38:34 +02:00
Dirk Behme
3ed9e943fd ARM Cortex A8: Remove bogus config.mk entries
Remove bogus config.mk entry, fix newline and remove redundant
omap3/config.mk

Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
2009-08-10 00:13:22 +02:00
Ilya Yanok
ba3dbaf281 mxc-mmc: sdhc host driver for MX2 and MX3 proccessor
This is a port of Linux driver for SDHC host controller hardware
found on Freescale's MX2 and MX3 processors. Uses new generic MMC
framework (CONFIG_GENERIC_MMC) and it looks like there are some
problems with a framework (at least on LE cpus). Some of these
problems are addressed in the following patches.

Signed-off-by: Ilya Yanok <yanok@emcraft.com>
2009-08-09 23:47:38 +02:00
Josh Boyer
317734966e Dual-license IBM code contributions
It was brought to our attention that U-Boot contains code derived from the
IBM OpenBIOS source code originally provided with some of the older PowerPC
4xx development boards.  As a result, the original license of this code has
been carried in the various files for a number of years in the U-Boot project.

IBM is dual-licensing the IBM code contributions already present in U-Boot
under either the terms of the GNU General Public License version 2, or the
original code license already present.

Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
2009-08-09 23:15:33 +02:00
Penda Naveen Kumar
3b9043a7c0 omap3: bug fix for NOR boot support
This patch provides bug fix, when omap3 uses nor boot.

Signed-off-by: Penda Naveen Kumar<pnaveen@ti.com>
Acked-by: Dirk Behme <dirk.behme@googlemail.com>
2009-08-08 11:59:40 +02:00
Dirk Behme
894113529e omap3: replace all instances of gpmc config struct by one global
Signed-off-by: Matthias Ludwig <mludwig@ultratronik.de>
Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
2009-08-08 11:34:11 +02:00
Dirk Behme
97a099eaa4 omap3: remove typedefs for configuration structs
Signed-off-by: Matthias Ludwig <mludwig@ultratronik.de>
Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
2009-08-08 11:33:23 +02:00
Matthias Ludwig
187af954cf omap3: embedd gpmc_cs into gpmc config struct
Embedd chip select configuration into struct for gpmc config
instead of having it completely separated as suggested by
Wolfgang Denk on
http://lists.denx.de/pipermail/u-boot/2009-May/052247.html

Signed-off-by: Matthias Ludwig <mludwig@ultratronik.de>
2009-08-07 23:31:51 +02:00
Wolfgang Denk
cb32ed1fc2 Merge branch 'next' of git://git.denx.de/u-boot-coldfire 2009-08-04 21:54:11 +02:00
David Brownell
06bffc6ea5 rm9200 lowevel_init: don't touch reserved/readonly registers
For some reason the AT91rm9200 lowlevel init writes to a bunch of
reserved or read-only addresses.  All the boards seem to define the
value-to-be-written values as zero ... but they shouldn't actually
be writing *anything* there.

No documented erratum justifies these accesses.  It looks like maybe
some pre-release BDI-2000 setup code has been carried along by cargo
cult programming since at least late 2004 (per GIT history).

Here's a patch disabling what seems to be bogosity.  Tested on a
csb337; there were no behavioral changes.

Signed-off-by: David Brownell <david-b@pacbell.net>

on RM9200ek
Tested-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-08-03 09:26:26 +02:00
Eric Benard
3c448e6482 Add AT91SAM9260 to at91's lowlevel_init.S
Needed for AT91SAM9260 NOR Boot on Eukrea's CPU9260.

Signed-off-by: Eric Benard <eric@eukrea.com>
2009-08-01 11:45:05 +02:00
Stefan Roese
89bcc48750 ppc4xx: Add basic support for AMCC PPC460EX/460GT rev B chips
This patch is based on a diff created by Phong Vo from AMCC.

Signed-off-by: Phong Vo <pvo@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-07-30 07:22:18 +02:00
Wolfgang Denk
108f56b056 Merge branch 'master' of git://git.denx.de/u-boot-i2c 2009-07-30 00:36:25 +02:00
Kumar Gala
4c2e3da82d Update Freescale copyrights to remove "All Rights Reserved"
"All Rights Reserved" conflicts with the GPL.

Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
2009-07-29 09:59:22 +02:00
Alessandro Rubini
60cbfbfd0f arm nomadik: add gpio support
Signed-off-by: Alessandro Rubini <rubini@unipv.it>
Acked-by: Andrea Gallo <andrea.gallo@stericsson.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2009-07-29 09:57:46 +02:00
Kim Phillips
be9b56df02 mpc83xx: CONFIG_83XX_GENERIC_PCI is now synonymous with CONFIG_PCI; remove the former
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-07-27 10:17:54 -05:00
Wolfgang Denk
9689ddcca6 cpu/arm920t/start.S: include <common.h> to have ROUND() defined
Commit fcd3c87e made include/common.h usable by assembler code but
failed to update cpu/arm920t/start.S

Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-07-27 10:06:39 +02:00
Wolfgang Denk
fcd3c87e49 Make include/common.h usable by assembler code
Commit 70ebf316 factored out the ROUND() macro into include/common.h,
not realizing that the primary use of this macro on AT91 systems was
in start.S where common.h was not included, and could not be included
because it contains a lot of C code which the assembler doesn't
understand.

This patch wraps such code in common.h in a "#ifndef __ASSEMBLY__"
construct, and then adds an include to cpu/arm926ejs/start.S thus
solving the problem.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-07-27 00:12:32 +02:00
Wolfgang Denk
8bf7437c01 Merge branch 'master' of git://git.denx.de/u-boot-video 2009-07-26 23:15:57 +02:00
Mark Jackson
716ece1de9 Add AVR32 LCD support
This patch adds support for the AVR32 LCD controller.  This patch is
based off the latest u-boot-video.

A quick summary of what's going on:-

Enable LCDC pixel clock
Enable LCDC port pins
Add framebuffer pointer to global_data struct
Allocate framebuffer

To use the new code, update your board config to include something like
this:-

#define CONFIG_LCD			1

#if defined(CONFIG_LCD)
#define CONFIG_CMD_BMP
#define CONFIG_ATMEL_LCD		1
#define LCD_BPP				LCD_COLOR16
#define CONFIG_BMP_16BPP		1
#define CONFIG_FB_ADDR			0x10600000
#define CONFIG_WHITE_ON_BLACK		1
#define CONFIG_VIDEO_BMP_GZIP 		1
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE		262144
#define CONFIG_ATMEL_LCD_BGR555		1
#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
#define CONFIG_SPLASH_SCREEN		1
#endif

The standard U-Boot BMP and Splash-screen features should just work.

Signed-off-by: Mark Jackson <mpfj@mimc.co.uk>
[agust@denx.de: fixed some style issues]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
2009-07-26 13:12:02 +02:00
Matthias Fuchs
58ea142fb2 ppc4xx: Replace 4xx lowercase SPR references
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-07-24 06:47:17 +02:00
Stefan Roese
87c0b72908 Add "chip_config" command for PPC4xx bootstrap configuration
This patch adds a generic command for programming I2C bootstrap
eeproms on PPC4xx. An implementation for Canyonlands board is
included.

The command name is intentionally chosen not to be PPC4xx specific.
This way other CPU's/SoC's can implement a similar command under
the same name, perhaps with a different syntax.

Usage on Canyonlands:

=> chip_config
Available configurations (I2C address 0x52):
600-nor          - NOR  CPU: 600 PLB: 200 OPB: 100 EBC: 100
600-nand         - NAND CPU: 600 PLB: 200 OPB: 100 EBC: 100
800-nor          - NOR  CPU: 800 PLB: 200 OPB: 100 EBC: 100
800-nand         - NAND CPU: 800 PLB: 200 OPB: 100 EBC: 100
1000-nor         - NOR  CPU:1000 PLB: 200 OPB: 100 EBC: 100
1000-nand        - NAND CPU:1000 PLB: 200 OPB: 100 EBC: 100
1066-nor         - NOR  CPU:1066 PLB: 266 OPB:  88 EBC:  88 ***
1066-nand        - NAND CPU:1066 PLB: 266 OPB:  88 EBC:  88
=> chip_config 600-nor
Using configuration:
600-nor          - NOR  CPU: 600 PLB: 200 OPB: 100 EBC: 100
done (dump via 'i2c md 52 0.1 10')
Reset the board for the changes to take effect

Other 4xx boards will be migrated to use this command soon
as well.

Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Acked-by: Matthias Fuchs <matthias.fuchs@esd.eu>
2009-07-24 06:42:32 +02:00
Dirk Eibach
9b1b8c8a1b ppc4xx: Fix missing freqOPB for 405EP
In cpu/ppc4xx/speed.c initialization of sysInfo->freqOPB for 405EP was
left out for no obvious reason.

Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-07-24 06:42:31 +02:00
Stefan Roese
0a371ca089 ppc4xx: Fix TLB reset problem with recent 44x images
Patch d873133f [ppc4xx: Add Sequoia RAM-booting target] broke "normal"
booting on some 44x platforms. This breakage is only noticed in some
cases while powercycling. As it seems, the code in question in start.S
didn't invalidate TLB #0. This makes sense since this TLB is used for
the bootrom mapping. With the patch mentioned above even TLB #0 got
invalidated resulting in an error later on.

This patch now fixes this issue by only invalidating TLB #0 in the RAM-
booting case.

Tested succesfully on Sequoia and Canyonlands.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Dirk Eibach <Eibach@gdsys.de>
2009-07-24 06:42:31 +02:00
Mike Frysinger
9aef738885 unify HOST_CFLAGS and HOSTCFLAGS
The top build system sets up HOSTCFLAGS a bit and exports it, but other
places use HOST_CFLAGS instead.  Unify the two as HOSTCFLAGS so that the
values stay in sync.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-07-23 21:26:14 +02:00
Ilya Yanok
0b23fb368d fec_mxc: driver for FEC ethernet controller on i.MX27
Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-07-22 22:59:07 -07:00
David Brownell
7168eba729 rm9200 ethernet driver: board-specific quirk (csb337)
CSB337 boards originally shipped with MicroMonitor, not U-Boot;
and with a version using a different convention for recording
Ethernet addresses than anyone else.  To avoid breaking Linux
when it uses U-Boot, have it use the same convention on that
hardware.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
2009-07-22 22:39:23 -07:00
Wolfgang Denk
84efbf4d14 Merge branch 'master' of git://git.denx.de/u-boot-arm 2009-07-23 00:59:37 +02:00
Minkyu Kang
6b96a20d51 ARM Cortex A8: Move OMAP3 specific reset handler
Because of the reset_cpu is soc specific, should be move to soc

Cc: Dirk Behme <dirk.behme@googlemail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2009-07-22 23:39:42 +02:00
Peter Tyser
d9c147f371 85xx, 86xx: Add common board_add_ram_info()
Previously, 85xx and 86xx boards would display DRAM information on
bootup such as:

...
I2C:   ready
DRAM:
Memory controller interleaving enabled: Bank interleaving!
 2 GB
FLASH: 256 MB
...

This patch moves the printing of the DRAM controller configuration to a
common board_add_ram_info() function which prints out DDR type, width,
CAS latency, and ECC mode.  It also makes the DDR interleaving
information print out in a more sane manner:

...
I2C:   ready
DRAM:   2 GB (DDR2, 64-bit, CL=4, ECC on)
       DDR Controller Interleaving Mode: bank
FLASH: 256 MB
...

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-07-22 09:43:48 -05:00
Peter Tyser
e7ee23ec17 86xx: Rename ccsr_ddr's sdram_mode_1, sdram_cfg_1 fields
Rename sdram_mode_1 to sdram_mode and sdram_cfg_1 to sdram_cfg to match
the 86xx user's manual and other Freescale architectures

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2009-07-22 09:43:47 -05:00
Mike Frysinger
490fe73491 Blackfin: split cpu COBJS into multilines
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-07-18 21:15:54 -04:00
Mike Frysinger
909878fd3f Blackfin: add os log functions
Part of the mini Blackfin ABI with operating systems is that they can use
0x4f0-0x4f8 to pass log buffers to/from bootloaders.  So add support to
U-Boot for reading the log buffer.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2009-07-18 21:15:50 -04:00
Wolfgang Denk
a694610d33 Merge branch 'master' of git://git.denx.de/u-boot-nand-flash 2009-07-19 00:38:23 +02:00
Tom Rix
6bb6e6c75e OMAP3 Fix compiler warning for v7_flush_dcache_all
On build of omap3 targets in MAKEALL, the *.ERR files have

cpu.c: In function 'cleanup_before_linux':
cpu.c:64: warning: implicit declaration of function 'v7_flush_dcache_all'
cpu.c:64: warning: implicit declaration of function 'get_device_type

The functions v7_flush_dcache_all and get_device_type are declared
in include/asm-arm/arch-omap3/sys_proto.h, so use this file to
declare the functions.

Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
2009-07-18 22:36:32 +02:00
Jean-Christophe PLAGNIOL-VILLARD
52cb4d4fb3 stdio/device: rework function naming convention
So far the console API uses the following naming convention:

	======Extract======
	typedef struct device_t;

	int	device_register (device_t * dev);
	int	devices_init (void);
	int	device_deregister(char *devname);
	struct list_head* device_get_list(void);
	device_t* device_get_by_name(char* name);
	device_t* device_clone(device_t *dev);
	=======

which is too generic and confusing.

Instead of using device_XX and device_t we change this
into stdio_XX and stdio_dev

This will also allow to add later a generic device mechanism in order
to have support for multiple devices and driver instances.

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

Edited commit message.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2009-07-18 00:27:46 +02:00
Stefan Roese
12582ac771 nand/ppc4xx: Move PPC4xx NAND driver to common NAND driver directory
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
2009-07-16 17:52:02 -05:00
Valeriy Glushkov
d89e1c3689 usb: mpc834x: added support of the MPH USB controller in addition to the DR one
Signed-off-by: Valeriy Glushkov <gvv@lstec.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2009-07-14 14:53:52 -05:00
TsiChung Liew
ee0a846246 ColdFire: Add DSPI support for MCF5227x and MCF5445x
Remove individual CPU specific DSPI driver.
Add required feature for the common DSPI driver in cpu_init and
in platform configuration file.

Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
2009-07-14 09:46:34 -05:00
TsiChung Liew
bf9a521529 ColdFire: Add M5208EVB and MCF520x CPU support
Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
2009-07-14 09:27:17 -05:00
TsiChung Liew
709b384b64 ColdFire: Update for M54451EVB
Update serial boot DRAM's Internal RAM, vector table and DRAM in
start.S, serial flash's read status command over SPI and NOR
flash.

Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
2009-07-14 09:27:14 -05:00
Wolfgang Denk
7629f1c06b MPC512x: factor out common code
Now that we have 3 boards for the MPC512x it turns out that they all
use the very same fixed_sdram() code.

This patch factors out this common code into cpu/mpc512x/fixed_sdram.c
and adds a new header file, include/asm-ppc/mpc512x.h, with some
macros, inline functions and prototype definitions specific to MPC512x
systems.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
2009-07-14 00:02:41 +02:00
Wolfgang Denk
87abce6e91 Merge branch 'master' of /home/wd/git/u-boot/master 2009-07-14 00:00:04 +02:00
Wolfgang Denk
c3ae126c2c Merge branch 'master' of git://git.denx.de/u-boot-arm 2009-07-13 23:45:02 +02:00
Wolfgang Denk
ed01c4f59d Merge branch 'master' of git://git.denx.de/u-boot-sh 2009-07-13 23:37:55 +02:00
Wolfgang Denk
5db1dcce91 Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx 2009-07-13 23:34:30 +02:00
Sedji Gaouaou
5ccc2d99d6 at91: Introduction of at91sam9g10 SOC.
AT91sam9g10 is an ARM 926ej-s SOC. It is an evolution of the at91sam9261 with a
faster clock speed: 266/133MHz.

Signed-off-by: Sedji Gaouaou <sedji.gaouaou@atmel.com>
2009-07-12 17:56:11 +02:00
Sedji Gaouaou
22ee647380 at91: Introduction of at91sam9g45 SOC.
AT91sam9g45 series is an ARM 926ej-s SOC family clocked at 400/133MHz.
It embeds USB high speed host and device, LCD, DDR2 RAM, and a full set of
peripherals.

The first board that embeds at91sam9g45 chip is the AT91SAM9G45-EKES.
On the board you can find 2 USART, USB high speed,
a 480*272 LG lcd, ethernet, gpio/joystick/buttons.

Signed-off-by: Sedji Gaouaou <sedji.gaouaou@atmel.com>
2009-07-12 17:43:34 +02:00
Jon Smirl
c9969947a4 board support patch for phyCORE-MPC5200B-tiny
Add support for the Phytec phyCORE-MPC5200B-tiny.
Code originally from Pengutronix.de.
Created CONFIG_SYS_ATA_CS_ON_TIMER01 define for when IDE CS is on
Timer 0/1

Signed-off-by: Jon Smirl <jonsmirl@gmail.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
2009-07-10 23:21:32 +02:00
Matthias Fuchs
632e9b671e ppc4xx: Set default PCI device ID for 405EP boards
Current code only sets the PCI vendor id to 0x1014 and
leaved device id to 0x0000.

Ths patch ....
a) uses the correct PCI_VENDOR_ID_IBM macro for this
b) sets the default device ID as stated in the UM to 0x0156
   by using PCI_DEVICE_ID_IBM_405GP for this.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-07-10 08:26:11 +02:00
Matthias Fuchs
123f102ec0 ppc4xx: Move 405EP pci code from cpu_init_f() to __pci_pre_init()
This patch moves some basic PCI initialisation from the 4xx cpu_init_f()
to cpu/ppc4xx/4xx_pci.c.

The original cpu_init_f() function enabled the 405EP's internal arbiter
in all situations. Also the HCE bit in cpc0_pci is always set.
The first is not really wanted for PCI adapter designs and the latter
is a general bug for PCI adapter U-Boots. Because it enables
PCI configuration by the system CPU even when the PCI configuration has
not been setup by the 405EP. The one and only correct place is
in pci_405gp_init() (see "Set HCE bit" comment).

So for compatibility reasons the arbiter is still enabled in any case,
but from weak pci_pre_init() so that it can be replaced by board specific
code.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-07-10 08:26:03 +02:00
Vivek Mahajan
db7b43e468 mpc83xx: USB: fix: access of ehci struct elements
It fixes the access to the 'ehci' struct elements for mpc83xx which
should have been taken care of in 4ef01010aa
Sorry about that.

Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
Signed-off-by: Remy Bohmer <linux@bohmer.net>
2009-07-09 21:33:15 +02:00
Matthias Fuchs
0580e48f53 ppc4xx: Make pll_write global
This patch makes pll_write on PPC405EP boards
global and callable from C code.

pll_write can be used to dynamically modify the PLB:PCI divider
as it is required for 33/66 MHz pci adapters based on the 405EP.

board_early_init_f() is a good place to do that (check M66EN signal
and call pll_write() when it is required).

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-07-08 10:59:07 +02:00
Stefan Roese
20b3c4b528 ppc4xx: Remove compilation warning "pci_async_enabled defined but not used"
Signed-off-by: Stefan Roese <sr@denx.de>
2009-07-08 10:59:07 +02:00
Matthias Fuchs
d0a1364f91 ppc4xx: Implement is_pci_host() for 405 CPUs
This patch implements the is_pci_host() function in a similiar way
as it is used on 440 targets.

The former path with CONFIG_PCI_HOST == PCI_HOST_AUTO does not
build on 405EP targets because checking the PCI arbiter is different.
So putting the fixed code into a separate function makes the code
more readable.

Also using is_pci_host() on 405 brings 405 and 440 PCI code
a little bit closer.

In preparation for an upcoming 405EP based PMC module I made this
function weak so that it can be overwritten from board specific code.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
2009-07-08 10:59:07 +02:00