Commit graph

35 commits

Author SHA1 Message Date
Simon Glass
05af050e9f x86: ivybridge: Declare global data where it is used
Some files are missing this declaration. Add it to avoid build errors when
we actually need the declaration.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-02-06 11:38:46 +08:00
Simon Glass
b6409ec302 dm: x86: Move link to use driver model for video
Update the configuration to use the new driver. Drop the existing plumbing
code and unused header files.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-10-11 11:55:33 +08:00
Simon Glass
a219639d42 dm: Rename disk uclass to ahci
This started as 'ahci' and was renamed to 'disk' during code review. But it
seems that this is too generic. Now that we have a 'blk' uclass, we can use
that as the generic piece, and revert to ahci for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-05-17 09:54:43 -06:00
Simon Glass
8c30b57130 x86: Move common LPC code to its own place
Some of the LPC code is common to several Intel LPC devices. Move it into a
common location.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:24 +08:00
Simon Glass
bb096b9fad x86: Add the root-complex block to common intel registers
This is similar to MCH in that it is used in various drivers. Add it to
the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:24 +08:00
Bin Meng
87077e97d1 x86: ivybridge: bd82x6x: Support FSP enabled configuration
Wrap initialization codes with #ifndef CONFIG_HAVE_FSP #endif,
and enable the build for both FSP and non-FSP configurations.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-02-21 13:42:52 +08:00
Bin Meng
ec2af6f82d x86: pch: Implement get_gpio_base op
Implement get_gpio_base op for bd82x6x, pch7 and pch9 drivers.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:21 +08:00
Bin Meng
3e389d8ba6 dm: pch: Rename get_sbase op to get_spi_base
Spell out 'sbase' to 'spi_base' so that it looks clearer.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:21 +08:00
Bin Meng
d02be99e67 dm: pch: Remove pch_get_version op
pch_get_version op was only used by the ich spi controller driver,
and does not really provide a good identification of pch controller
so far, since we see plenty of Intel PCH chipsets and one differs
from another a lot, which is not simply either a PCHV_7 or PCHV_9.
Now that ich spi controller driver was updated to not get such info
from pch, the pch_get_version op is useless now.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2016-02-05 12:47:21 +08:00
Simon Glass
25d5352c71 x86: ivybridge: Use syscon for the GMA device
Until we have a proper video uclass we can use syscon to handle the GMA
device, and avoid the special device tree and PCI searching. Update the code
to work this way.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:42 +08:00
Simon Glass
278d3a4444 x86: ivybridge: Drop special EHCI init
This is not needed. On reset wake-on-disconnect is already set. It may a
problem during a soft reset or resume, but for now it does not seem
important. Also drop the command register update since PCI auto-config
does it for us.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:42 +08:00
Simon Glass
a5ea3a7d4a x86: ivybridge: Move code from pch.c to bd82x6x.c
This code relates to the PCH, so we should move it into the same file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:41 +08:00
Simon Glass
4e19072907 x86: ivybridge: Move LPC init into the LPC probe() method
Drop the lpc_init_extra() function and just use the post-relocation LPC
probe() instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:40 +08:00
Simon Glass
865c24eea1 x86: ivybridge: Move lpc_enable() into gma.c
This graphics init code is best placed in the gma init code. Move the code
and drop the function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:40 +08:00
Simon Glass
01a679084b x86: ivybridge: Use the SATA driver to do the init
Instead of manually initing the device, probe the SATA device and move the
init there.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:40 +08:00
Simon Glass
82935b751b x86: ivybridge: Drop the unused bd82x6x_init_extra()
This function does nothing now so can be dropped.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:40 +08:00
Simon Glass
d46f2a68e6 x86: ivybridge: Do the SATA init before relocation
The SATA device needs to set itself up so that it appears correctly on the
PCI bus. The easiest way to do this is to set it up to probe before
relocation. This can do the early setup.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:09:39 +08:00
Simon Glass
9ed781a6ff x86: ivybridge: Move northbridge and PCH init into drivers
Instead of calling the northbridge and PCH init from bd82x6x_init_extra()
when the PCI bus is probed, call it from the respective drivers. Also drop
the Northbridge init as it has no effect. The registers it touches appear to
be read-only.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:08:17 +08:00
Simon Glass
9d156b5725 x86: ivybridge: Move CPU init code into the driver
Use the CPU driver's probe() method to perform the CPU init. This will happen
automatically when the first CPU is probed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:08:17 +08:00
Simon Glass
2b27d20529 x86: ivybridge: Rename lpc_init() to lpc_init_extra()
In preparation for adding an init() method to the LPC uclass, rename this
existing function so that it will not conflict.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:08:16 +08:00
Simon Glass
858361b174 x86: ivybridge: Rename bd82x6x_init()
Rename the existing bd82x6x_init() to bd82x6x_init_extra(). We will remove
this in a later patch.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:07:19 +08:00
Simon Glass
4acc83d437 x86: ivybridge: Set up the LPC device using driver model
Find the LPC device in arch_cpu_init_dm() as a first step to converting
this code to use driver model. Probing the LPC will probe its parent (the
PCH) automatically, so make sure that probing the PCH does nothing before
relocation.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:07:19 +08:00
Simon Glass
f2b85ab5e6 dm: x86: spi: Convert ICH SPI driver to driver model PCI API
At present this SPI driver works by searching the PCI buses for its
peripheral. It also uses the legacy PCI API.

In addition the driver has code to determine the type of Intel PCH that is
used (version 7 or version 9). Now that we have proper PCH drivers we can
use those to obtain the information we need.

While the device tree has a node for the SPI peripheral it is not in the
right place. It should be on the PCI bus as a sub-peripheral of the LPC
device.

Update the device tree files to show the SPI controller within the PCH, so
that PCI access works as expected.

This patch includes Bin's fix-up patch from here:

   https://patchwork.ozlabs.org/patch/569478/

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-24 12:07:17 +08:00
Simon Glass
9bf727fcc4 dm: x86: ivybridge: Convert graphics init to use DM PCI API
Use the driver-model PCI functions here where possible. For now we have to
search for the device with pci_bus_find_bdf() but at some point we can put
this in a proper driver and avoid this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-12 10:19:09 -07:00
Bin Meng
5bf935925b x86: ivybridge: Remove the dead codes that programs pci bridge
Remove bd82x6x_pci_bus_enable_resources() that is not called anywhere.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-10-21 07:46:25 -06:00
Simon Glass
452f548753 dm: x86: Add a uclass for a Platform Controller Hub
Add a simple uclass for this chip which is often found in x86 systems
where the CPU is a separate device.

The device can have children, so make it scan the device tree for these.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:14 -06:00
Simon Glass
aad78d2732 dm: x86: pci: Convert chromebook_link to use driver model for pci
Move chromebook_link over to driver model for PCI.

This involves:
- adding a uclass for platform controller hub
- removing most of the existing PCI driver
- adjusting how CPU init works to use driver model instead
- rename the lpc compatible string (it will be removed later)

This does not really take advantage of driver model fully, but it does work.
Furture work will improve the code structure to remove many of the explicit
calls to init the board.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:09 -06:00
Simon Glass
31f57c2873 x86: Add a x86_ prefix to the x86-specific PCI functions
These functions currently use a generic name, but they are for x86 only.
This may introduce confusion and prevents U-Boot from using these names
more widely.

In fact it should be possible to remove these at some point and use
generic functions, but for now, rename them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-04-16 19:27:41 -06:00
Simon Glass
effcf067df x86: Add initial video device init for Intel GMA
Intel's Graphics Media Accelerator (GMA) is a generic name for a wide range
of video devices. Add code to set up the hardware on ivybridge. Part of the
init happens in native code, part of it happens in a 16-bit option ROM for
those nostalgic for the 1970s.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 07:11:16 -07:00
Simon Glass
24774278c9 x86: ivybridge: Add northbridge init functions
Add init for the northbridge, another part of the platform controller hub.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:14 -07:00
Simon Glass
bb80be3916 x86: Add init for model 206AX CPU
Add the setup code for the CPU so that it can be used at full speed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:14 -07:00
Simon Glass
9baeca4b89 x86: ivybridge: Set up EHCI USB
Add init for EHCI so that USB can be used.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:01 -07:00
Simon Glass
3ac839352d x86: ivybridge: Add SATA init
Add code to set up the SATA interfaces on boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:01 -07:00
Simon Glass
72cd085aae x86: ivybridge: Add additional LPC init
Set up all the remaining pieces of the LPC (low-pin-count) peripheral in
PCH (Peripheral Controller Hub).

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:01 -07:00
Simon Glass
4e7a6acac7 x86: ivybridge: Add support for BD82x6x PCH
Add basic setup for the PCH.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-25 06:34:00 -07:00