Commit graph

32274 commits

Author SHA1 Message Date
Marcel Ziswiler
8648b2358a serial: pxa: clean-up include file order
Cleaning up order of include files by sorting them alphabetically
keeping in mind to leave common.h on top.

Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
2015-08-24 20:30:38 +02:00
Marcel Ziswiler
54a5cf81c4 arm: pxa: mmc: clean-up include file order
Cleaning up order of include files by sorting them alphabetically
keeping in mind to leave common.h on top.

Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
2015-08-24 20:30:37 +02:00
Marcel Ziswiler
67b855fe54 arm: pxa: clean-up include file order
Cleaning up order of include files by sorting them alphabetically
keeping in mind to leave common.h on top.

Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
2015-08-24 20:30:37 +02:00
Andrew Ruder
7d211fec96 arm: pxa: use common timer functions
This patch moves pxa to the common timer functions added in commit

  8dfafdd - Introduce common timer functions <Rob Herring>

The (removed) pxa timer code (specifically __udelay()) could deadlock at
the 32-bit boundary of get_ticks().  get_ticks() returned a 32-bit value
cast up to a 64-bit value.  If get_ticks() + tmo in __udelay() crossed
the 32-bit boundary, the while condition became unconditionally true and
locked the processor.  Rather than patch the specific pxa issues, simply
move everything over to the common code.

Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsuiko.com>
2015-08-24 20:30:37 +02:00
Andrew Ruder
07a8e6d6ee pxa: Fix boot hang by avoiding vector relocation
Since commit 3ff46cc42b ("arm: relocate the exception vectors")
pxa does not boot anymore.

Add a specific relocate_vectors macro that skips the vector relocation,
as the pxa SoC does not provide RAM at the high vectors address
(0xFFFF0000), and (0x00000000) maps to ROM.

This allows pxa to boot again.

Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com>
2015-08-24 20:30:37 +02:00
Tom Rini
c851a2458f Merge git://git.denx.de/u-boot-socfpga
Conflicts:
	configs/socfpga_arria5_defconfig
	configs/socfpga_cyclone5_defconfig
	configs/socfpga_socrates_defconfig

Merged these by hand and re-ran savedefconfig on them.

Signed-off-by: Tom Rini <trini@konsulko.com>
2015-08-23 20:44:25 -04:00
Tom Rini
14e7a30f2e Merge branch 'master' of git://git.denx.de/u-boot-net 2015-08-23 20:41:04 -04:00
Marek Vasut
29aa439759 arm: socfpga: Fix ArriaV SoCDK PLL config
Pull out the ArriaV SoCDK clock config from ancient Altera U-Boot
"rel_socfpga_v2013.01.01_15.05.01_pr" and implant those values into
mainline to get a booting ArriaV SoCDK.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-23 11:56:21 +02:00
Marek Vasut
9238b52abd arm: socfpga: Enable ethernet on ArriaV SoCDK
Synchronise the config options with Cyclone V SoCDK and other boards.
This enables ethernet on the ArriaV SoCDK.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-23 11:56:21 +02:00
Marek Vasut
476a36032d arm: socfpga: Fix SD/MMC boot on ArriaV SoCDK
Add the missing DT nodes, so that ArriaV SoCDK can boot from SD
card. The SD card must be in slot J5 and BSEL must be 0x5.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-23 11:56:20 +02:00
Marek Vasut
d418301167 arm: socfpga: Fix MAINTAINERS entry for CV/AV SoCDK
Repair the maintainer entries so they match the current state of code.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-23 11:56:20 +02:00
Marek Vasut
1bd57ff540 arm: socfpga: Enable DWAPB GPIO driver
Enable the DWAPB GPIO driver for SoCFPGA Cyclone V and Arria V.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-08-23 11:56:20 +02:00
Marek Vasut
660f53bc1a arm: socfpga: dts: Add bank-name property to each GPIO bank
Add "bank-name" property to each GPIO bank to give it unique name.
The approach here is exactly the same as with the "regulator-name"
property for regulators.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-23 11:56:20 +02:00
Marek Vasut
e30a70c2d3 gpio: Add DW APB GPIO driver
Add driver for the DesignWare APB GPIO IP block.
This driver is DM capable and probes from DT.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
2015-08-23 11:56:20 +02:00
Marek Vasut
cc9429a556 arm: socfpga: Make the pinmux table const u8
Now that we're actually converting the QTS-generated header files,
we can even adjust their data types. A good candidate for this is
the pinmux table, where each entry can have value in the range of
0..3, but each element is declared as unsigned long. By changing
the type to u8, we can save over 600 Bytes from the SPL, so do it.
This patch also constifies the array.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-23 11:56:20 +02:00
Marek Vasut
f6badb0d89 arm: socfpga: Switch to filtered QTS files
Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-23 11:56:20 +02:00
Marek Vasut
e996b9362b arm: socfpga: Add qts-filter.sh script
Add script which loads the QTS-generated sources and headers and converts
them into sensible format which can be used with much more easy in mainline
U-Boot. The script also filters out macros which makes no sense anymore, so
they don't pollute namespace and waste space.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-23 11:56:20 +02:00
Marek Vasut
37b3a30ae6 arm: socfpga: Remove AV-specific parts from CV-SoCDK
Just remove the ArriaV specific parts from the CycloneV SoCDK board
and they are no longer needed now.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-23 11:56:20 +02:00
Marek Vasut
c68eea0492 arm: socfpga: Remove CV-specific parts from AV-SoCDK
Just remove the CycloneV specific parts from the ArriaV SoCDK board
and they are no longer needed now.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-23 11:56:20 +02:00
Marek Vasut
f089240128 arm: socfpga: Split Altera socfpga into AV and CV SoCDK
The board/altera/socfpga directory is not a generic SoCFPGA machine
anymore, but instead it represents the Altera SoCDK board. To make
matters more complicated, it represents both CycloneV and ArriaV
variant.

On the other hand, nowadays, the content of this board directory is
mostly comprised of QTS-generated header files, while all the generic
code is in arch/arm/mach-socfpga already.

Thus, this patch splits the board/altera/socfpga into a separate
board directory for ArriaV SoCDK and CycloneV SoCDK, so that each
can be populated with the correct QTS-generated header files for
that particular board.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-23 11:56:19 +02:00
Marek Vasut
cd9b731771 arm: socfpga: Unbind CPU type from board type
The CONFIG_TARGET_SOCFPGA_CYCLONE5 and CONFIG_TARGET_SOCFPGA_ARRIA5
selected both a board and a CPU. This is not correct as these macros
are supposed to select only board.

All would be good, if QTS-generated header files didn't check for
these macros exactly to determine if the platform is Cyclone V or
Arria V. Thus, for the sake of compatibility with not well fleshed
out header file generator, this patch makes these two macros into
a stub config option and introduces new CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK
and CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK targets, which select the
previous stub config option.

The result is that compatibility with QTS is preserved and the new
CONFIG_TARGET_* select actual target boards.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-23 11:56:19 +02:00
Marek Vasut
ca62d2e1fc arm: socfpga: Move wrappers into platform directory
Move the wrappers for QTS-generated files into platform directory
out of the board directory. The trick here is to add -I to CFLAGS
such that it points to the board directory in source tree and thus
the qts/ directory there is still reachable.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-23 11:56:19 +02:00
Marek Vasut
c2624240dd arm: socfpga: Do not enable gmac1 in Cyclone V dtsi
The GMAC which is enabled is purely board property, so do not enable
arbitrary GMAC in DT include files. Same goes for PHY mode, which is
again a board property. The CycloneV SoCDK does this correctly, but
SoCrates doesn't. This bug never manifested itself though, since all
the boards ever used the GMAC1 . This bug manifests itself only on
boards that utilise GMAC0.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-23 11:56:19 +02:00
Marek Vasut
afe139938a arm: socfpga: Make the DT mmc node consistent
The socfpga_cyclone5.dtsi has an mmc0 node, socrates has mmc node.
This makes aliases not very usable, so make everything into mmc0.
Moreover, zap the useless mmc alias while at this.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-23 11:56:19 +02:00
Marek Vasut
7e4d2fa2ed arm: socfpga: Fix delay in clock manager
This code claims it needs to wait 7us, yet it uses get_timer() function
which operates with millisecond granularity. Use timer_get_us() instead,
which operates with microsecond granularity.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-23 11:56:19 +02:00
Marek Vasut
a8535c306c arm: socfpga: Fix delay in freeze controller
Based on observation, this udelay(20) was apparently too high and caused
subsequent failure to calibrate DDR when U-Boot was compiled with certain
toolchains. Lowering this delay fixed the problem.

Instead of permanently lowering the delay, calculate the correct delay
based on the original comment, that is, obtain EOSC1 frequency and use
it to calculate the precise delay.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-23 11:56:19 +02:00
Marek Vasut
35e47b7132 ddr: altera: Repair uninited variable
Fix the following problem:
drivers/ddr/altera/sequencer.c: In function 'sdram_calibration_full':
drivers/ddr/altera/sequencer.c:1943:25: warning: 'found_failing_read' may be used uninitialized in this function [-Wmaybe-uninitialized]
  if (found_passing_read && found_failing_read)
                         ^
drivers/ddr/altera/sequencer.c:1803:26: note: 'found_failing_read' was declared here
  u32 found_passing_read, found_failing_read, initial_failing_dtap;
                          ^

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-23 11:56:19 +02:00
Marek Vasut
6d7a33301a ddr: altera: Replace float multiplication with integer one
This gem is really really rare, there was an actual float used in
the Altera DDR init code, which pulled in floating point ops from
the libgcc, just wow.

Since we don't support floating point operations the same way Linux
does not support them, replace this with an integer multiplication
and division combo. This removes some 2kiB of size from the SPL as
the floating point ops are no longer pulled in from libgcc.

This was detected by enabling CONFIG_USE_PRIVATE_LIBGCC=y , which
does not contain the floating point bits.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-23 11:56:19 +02:00
Simon Glass
a77fda1f7d net: Move CONFIG_E1000 options to Kconfig
Move config for the E1000 Ethernet driver to Kconfig and tidy up affected
boards.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-08-21 16:40:23 -05:00
Simon Glass
b880fcf021 Tidy up some defconfig files
Several files are out of order. This means that when the moveconfig tool
moves CONFIG options to Kconfig it generates a large diff. To avoid this,
reorder the files first.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-21 16:39:39 -05:00
Simon Glass
c294ac5c16 net: e1000: Add Kconfig options
Add Kconfig options in preparation for moving boards to use Kconfig.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-08-21 16:33:39 -05:00
Simon Glass
c6d80a1522 net: e1000: Convert to driver model
Update this driver to support driver model.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Apalis T30 2GB on Apalis Evaluation Board
2015-08-21 16:33:21 -05:00
Simon Glass
5c5e707a55 net: e1000: Prepare for driver model conversion
Since struct eth_device does not exist with CONFIG_DM_ETH defined, avoid
using it in the driver unless necessary. Most of the time it is better to
pass the private driver pointer anyway.

Also refactor the code so that code that the driver model implementation
will share are available in functions that can be called. Add stubs where
necessary.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Apalis T30 2GB on Apalis Evaluation Board
2015-08-21 16:32:55 -05:00
Simon Glass
c752cd2a30 net: e1000: Move #include of common.h to the C files
We cannot currently include any header files in the C files since common.h
needs to be included first, and it is in the header file. Move it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Apalis T30 2GB on Apalis Evaluation Board
2015-08-21 16:32:32 -05:00
Michal Simek
19a4fbaadd net: Return -EINTR when ctrl+c is pressed
Current behavior is that if CTRL+C is pressed command returns 0 that was
successful which is not correct behavior.
The easiest test case is "tftpboot 80000 uImage && echo yes"
and press CTRL+C. Then the second command is called which is incorrect.

Error log:
zynq-uboot> tftpb 80000 uImage && echo yes
Gem.e000b000:7 is connected to Gem.e000b000.  Reconnecting to
Gem.e000b000
Gem.e000b000 Waiting for PHY auto negotiation to complete....... done
Using Gem.e000b000 device
TFTP from server 192.168.0.102; our IP address is 192.168.0.101
Filename 'uImage'.
Load address: 0x80000
Loading: ################
Abort
yes
zynq-uboot>

This patch adds -EINTR return value when CTRL+C is pressed.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-08-21 16:32:05 -05:00
Mingkai Hu
6497e37a75 net: e1000: Support 64-bit physical address
High 32-bit address is needed when u-boot runs in 64-bit space.
Tested on armv8-based LS2085ARDB.

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-08-21 16:31:34 -05:00
Pavel Machek
620776d734 tftp: adjust settings to be suitable for 100Mbit ethernet
Adjust timouts and retry counts to be suitable for loaded ethernet
network. With 5 seconds timeout, 10 retries maximum, tftp is
impossible even on local network with single full-speed TCP
connection.

100msec timeout should be suitable for most networks tftp is used on,
that is local ethernets. Timeout count really needs to be way higher,
as lost packets are normal when TCP is running over the same network.

Enforce 10msec minimum.

Signed-off-by: Pavel Machek <pavel@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2015-08-21 16:31:00 -05:00
Wu, Josh
7a53b9544e ARM: at91: sama5: update the spi flash mapping
Also move the spi flash configurations to the at91-sama5_common.h.

Current at91 zImage size is about 3.3M, the old mapping is not
suitable. So update the spi flash map as following:
	0x0      ~ 0x004000: at91bootstrap(16k)
	0x04000  ~ 0x008000: u-boot env(16k)
	0x08000  ~ 0x060000: u-boot(352k)
	0x60000  ~ 0x06c000: dtb (48k)
	0x6c000  ~ 0x400000: kernel (3M+592k)

In AT91Bootstrap, the U-Boot in spi flash also update to 0x8000, refer
to following commit in AT91Bootstrap:
	3e91e54 Kconfig: fix spi flash address

So also update SPL's u-boot load address to 0x8000 in spi flash.

Signed-off-by: Josh Wu <josh.wu@atmel.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2015-08-21 15:47:05 +02:00
Wu, Josh
dc018fef2f ARM: at91: sama5: move the nandflash env config to at91-sama5_common.h
As all sama5 nandflash env configurations are same, so move them to
at91-sama5_common.h.

Signed-off-by: Josh Wu <josh.wu@atmel.com>
2015-08-21 15:47:05 +02:00
Wu, Josh
89a3658ac0 ARM: at91: sama5d3xek: use a $dtb_name to load dtb
Since sama5d3xek boards has different type of dtb blobs, so we need to detect
the cpu type in runtime.

So we add a new variable $dtb_name. if $dtb_name is not defined, we just use
	at91-${board_name}.dtb

as the $dtb_name. Otherwise, we will just load the dtb with
	$dtb_name.

For sama5d3xek, we will detect cpu type and make up $dtb_name in
runtime.

Signed-off-by: Josh Wu <josh.wu@atmel.com>
2015-08-21 15:47:04 +02:00
Wu, Josh
372ca03fcd ARM: at91: sama5: move the sd/mmc env config to at91-sama5_common.h
As almost all sama5 sd/mmc env configurations are same, so move them to
at91-sama5_common.h.

Also define CONFIG_ENV_VARS_UBOOT_CONFIG to have the varaible: $board_name.
Then we can use 'at91-${board_name}.dtb' as the dtb name.

TODO: since sama5d3xek has different dtb name, we need to some extra
stuff to make it work on sama5d3xek boards.

Signed-off-by: Josh Wu <josh.wu@atmel.com>
2015-08-21 15:47:04 +02:00
Erik van Luijk
bfc37f3cb8 arm: at91: add support for mini-box picosam9g45 board
Bootlog:
U-Boot SPL 2015.10-rc1-00452-g96a7ed1 (Aug 17 2015 - 10:32:21)
mci: setting clock 258000 Hz, block size 512
mci: setting clock 258000 Hz, block size 512
mci: setting clock 258000 Hz, block size 512
mci: setting clock 33024000 Hz, block size 512
reading u-boot.img
reading u-boot.img

U-Boot 2015.10-rc1-00452-g96a7ed1 (Aug 17 2015 - 10:32:21 +0000)

CPU: AT91SAM9G45
Crystal frequency:       12 MHz
CPU clock        :      400 MHz
Master clock     :  133.333 MHz
       Watchdog enabled
DRAM:  256 MiB
WARNING: Caches not enabled
MMC:   mci: 0
mci: setting clock 260416 Hz, block size 512
mci: setting clock 260416 Hz, block size 512
mci: setting clock 260416 Hz, block size 512
mci: setting clock 33333333 Hz, block size 512
reading uboot.env
In:    serial
Out:   serial
Err:   serial
Net:   macb0
Error: macb0 address not set.

Hit any key to stop autoboot:  0
U-Boot>

Signed-off-by: Erik van Luijk <evanluijk@interact.nl>
[add 'picosam9g45_defconfig' to MAINTAINERS]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-08-21 15:47:04 +02:00
Erik van Luijk
c982f6b9bf arm: at91: pmc: replace the constant with a define in at91_pmc.h
To enable the clocks on the at91 boards a constant (0x4) is used.
This is replaced with a define in at91_pmc.h (1 <<  2).

Signed-off-by: Erik van Luijk <evanluijk@interact.nl>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-08-21 15:47:03 +02:00
Erik van Luijk
6560491fe5 arm: at91: at91sam9m10g45ek/corvus remove useless chip select 1 init
On these boards the DDR is connected to a dedicated controller and not
to chip select 1 of the EBI.

Signed-off-by: Erik van Luijk <evanluijk@interact.nl>
Tested-by: Erik van Luijk <evanluijk@interact.nl>
2015-08-21 15:47:03 +02:00
Erik van Luijk
0c01c3e876 arm: at91: mpddr: allow multiple DDR controllers
The mpddr.c depends on ATMEL_BASE_MPDDRC for the base address to configure the controller.
This cannot be used when there is more than one controller (i.e. AT91SAM9G45, AT91SAM9M10).

Signed-off-by: Erik van Luijk <evanluijk@interact.nl>
[remove 'new blank line at EOF']
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-08-21 15:47:02 +02:00
Masahiro Yamada
8d77576371 ARM: davinci: remove support for cam_enc_4xx
This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Heiko Schocher <hs@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
2015-08-20 12:55:50 -04:00
Tom Rini
a5d338b2f2 Merge git://git.denx.de/u-boot-usb 2015-08-19 18:04:48 -04:00
Marek Vasut
7a1386f96b usb: dwc2: Rename to dwc2_usb
This driver is not used only on exynos, but also on Altera SoCFPGA,
HiSilicon SoCs, RPi etc, so rename it accordingly to prevent confusion.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-19 22:31:39 +02:00
Marek Vasut
f522f9475f usb: dwc2: Add original Synopsys compat string
Add the Synopsys compatible string. This is used in SoCFPGA DT files.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-19 22:31:39 +02:00
Kishon Vijay Abraham I
5df1315211 usb: gadget: ether: populate _reset_ callback
populate _reset_ callback to the USB ethernet gadget since UDC core
expects every gadget driver to have the reset callback. This shouldn't
be needed once the ethernet gadget driver is adapted to use the
composite driver.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
2015-08-19 22:30:31 +02:00