Commit graph

20 commits

Author SHA1 Message Date
Tom Rini
83d290c56f SPDX: Convert all of our single license tags to Linux Kernel style
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-07 09:34:12 -04:00
Lukasz Majewski
d695d66278 spl: eMMC/SD: Provide one __weak spl_boot_mode() function
The goal of this patch is to clean up the code related to choosing SPL
MMC boot mode.

The spl_boot_mode() now is called only in spl_mmc_load_image() function,
which is only compiled in if CONFIG_SPL_MMC_SUPPORT is enabled.

To achieve the goal, all per mach/arch implementations eligible for
unification has been replaced with one __weak implementation.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Acked-by: Michal Simek <michal.simek@xilinx.com> (For ZynqMP)
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-02-07 22:06:18 -05:00
Ley Foon Tan
8f4c80c4fd arm: socfpga: Add SPL support for Arria 10
Add SPL support for Arria 10.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2017-05-18 11:33:18 +02:00
Ley Foon Tan
de77811589 arm: socfpga: Restructure clock manager driver
Restructure clock manager driver in the preparation to support A10.
Move the Gen5 specific code to _gen5 files.

- Change all uint32_t to u32 and change to use macro BIT(n) for bit shift.
- Check return value from wait_for_bit(). So change return type to int for
  cm_write_with_phase() and cm_basic_init().

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2017-05-18 11:33:16 +02:00
Marek Vasut
2b1cdafa9f common: Pass the boot device into spl_boot_mode()
The SPL code already knows which boot device it calls the spl_boot_mode()
on, so pass that information into the function. This allows the code of
spl_boot_mode() avoid invoking spl_boot_device() again, but it also lets
board_boot_order() correctly alter the behavior of the boot process.

The later one is important, since in certain cases, it is desired that
spl_boot_device() return value be overriden using board_boot_order().

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
[add newly introduced zynq variant]
Signed-aff-by: Andreas Bießmann <andreas@biessmann.org>
2016-06-26 20:17:22 +02:00
Marek Vasut
ac242e1625 arm: socfpga: Unreset NAND in SPL
If the system boots from NAND, make sure to de-assert the NAND IP
reset, otherwise the system will get stuck.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-12-22 21:30:02 +01:00
Marek Vasut
a665b051b5 arm: socfpga: Do not call board_init_r() from board_init_f()
Instead of calling board_init_r() directly from board_init_f(), just
return from board_init_f(). This will make the code continue executing
in crt0.S _main(), from which the board_init_r() is called. This patch
aligns the SoCFPGA SPL with the correct SPL design as well as reduces
the stack utilisation slightly.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-09-04 11:54:20 +02:00
Marek Vasut
7599b53dc1 arm: socfpga: config: Move SPL GD and malloc to RAM
Now that the SPL structure is organised such that it matches the
U-Boot's SPL design, it is possible to use the option of relocating
GD to RAM. And since we have GD in RAM, move malloc area to RAM as
well. We point the malloc base pointer 1 MiB past U-Boot's load
address. We use simple malloc for SPL because it is 3kiB smaller
in terms of code size than regular malloc which was used thus far.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:09 +02:00
Marek Vasut
066ad14a22 arm: socfpga: spl: Add support for selecting boot device from BSEL
Rework spl_boot_device() such that it reads the BSEL settings from
system manager and decides from where to load U-Boot based on this
information.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:08 +02:00
Marek Vasut
346d6f5667 arm: socfpga: spl: Add support for booting from QSPI
Add code and configuration options to support booting from QSPI NOR.
Enable support for booting from QSPI NOR.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:08 +02:00
Marek Vasut
d3f34e752d arm: socfpga: spl: Add support for booting from SD/MMC
Add code and configuration options to support booting from RAW
SD/MMC card as well as for ext4/vfat filesystems. Enable support
for booting from SD/MMC card, but don't enable the filesystem
support just yet to retain compatibility with old SoCFPGA card
format.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:08 +02:00
Marek Vasut
6473054a12 arm: socfpga: spl: Merge spl_board_init() into board_init_f()
The code in spl_board_init() should have been in board_init_f()
from the beginning, since it is code which configures system and
then starts DRAM. Thus, it cannot be in spl_board_init(), which
is called from board_init_r() , which already expects a working
DRAM.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:07 +02:00
Marek Vasut
bd65fe35ff arm: socfpga: spl: Add missing reset logic
Make sure that all the peripherals are correctly reset and then
brought out of reset in the SPL. Not going through proper reset
cycle might leave the IP blocks in inconsistent state.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:07 +02:00
Marek Vasut
232fcc6e9d arm: socfpga: spl: Configure SCU and NIC-301 early
Configure the ARM SCU and NIC301 very early. The ARM SCU SNSAC register
must be configured, so we can access all peripherals. The NIC-301 must
be configured so that the BootROM is not mapped into the SDRAM address
space.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:07 +02:00
Marek Vasut
4a0080d985 arm: socfpga: spl: Toggle warm reset config I/O bit
Synchronise the SPL behavior with the original Altera code and
toggle the Warm Reset Config I/O bit accordingly.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:07 +02:00
Marek Vasut
40687b4f46 arm: socfpga: system: Rework sysmgr_enable_warmrstcfgio()
Rework sysmgr_enable_warmrstcfgio() into sysmgr_config_warmrstcfgio(),
which allows both enabling and disabling the warm reset config I/O
functionality.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:07 +02:00
Marek Vasut
93b4abd3a2 arm: socfpga: clock: Clean up pll_config.h
Extract the clock configuration horribleness caused by pll_config.h in
the following manner.

First of all, introduce a few new accessors which return values of
various clocks used in clock_manager.c and use them in clock_manager.c .
These accessors replace those few macros which came from pll_config.h
originally. Also introduce an accessor which returns the struct cm_config
default configuration for the clock manager used in SPL.

The accessors are implemented in a board-specific wrap_pll_config.c
file, whose sole purpose is to include the qts-generated pll_config.h
and provide only the necessary values to the clock manager.

The purpose of this design is to limit the scope of inclusion for the
pll_config.h , which thus far was included build-wide and poluted the
namespace. With this change, the inclusion is limited to just the new
wrap_pll_config.c file, which in turn provides three simple functions
for the clock_manager.c to use.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:06 +02:00
Marek Vasut
163ee7d9d2 arm: socfpga: clock: Get rid of cm_config_t typedef
Get rid of this cryptic typedef and replace it with explicit struct cm_config.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:06 +02:00
Marek Vasut
a71df7aa4f arm: socfpga: reset: Replace ad-hoc reset functions
Replace all those ad-hoc reset functions, which were all copies
of the same invocation of clrbits_le32() anyway, with one single
unified function, socfpga_per_reset(), with necessary parameters.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:06 +02:00
Masahiro Yamada
05a217212b ARM: socfpga: move SoC sources to mach-socfpga
Our recent trend is to collect SoC files into arch/arm/mach-(SOC).

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2015-05-07 05:21:12 +02:00
Renamed from arch/arm/cpu/armv7/socfpga/spl.c (Browse further)