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https://github.com/AsahiLinux/u-boot
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bd65fe35ff
Make sure that all the peripherals are correctly reset and then brought out of reset in the SPL. Not going through proper reset cycle might leave the IP blocks in inconsistent state. Signed-off-by: Marek Vasut <marex@denx.de>
156 lines
3.9 KiB
C
156 lines
3.9 KiB
C
/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/pl310.h>
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#include <asm/u-boot.h>
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#include <asm/utils.h>
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#include <image.h>
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#include <asm/arch/reset_manager.h>
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#include <spl.h>
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#include <asm/arch/system_manager.h>
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#include <asm/arch/freeze_controller.h>
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#include <asm/arch/clock_manager.h>
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#include <asm/arch/scan_manager.h>
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#include <asm/arch/sdram.h>
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#include <asm/arch/scu.h>
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#include <asm/arch/nic301.h>
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DECLARE_GLOBAL_DATA_PTR;
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static struct pl310_regs *const pl310 =
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(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
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static struct scu_registers *scu_regs =
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(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
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static struct nic301_registers *nic301_regs =
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(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
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static void socfpga_nic301_slave_ns(void)
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{
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writel(0x1, &nic301_regs->lwhps2fpgaregs);
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writel(0x1, &nic301_regs->hps2fpgaregs);
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writel(0x1, &nic301_regs->acp);
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writel(0x1, &nic301_regs->rom);
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writel(0x1, &nic301_regs->ocram);
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writel(0x1, &nic301_regs->sdrdata);
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}
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void board_init_f(ulong dummy)
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{
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struct socfpga_system_manager *sysmgr_regs =
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(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
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unsigned long reg;
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/*
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* First C code to run. Clear fake OCRAM ECC first as SBE
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* and DBE might triggered during power on
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*/
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reg = readl(&sysmgr_regs->eccgrp_ocram);
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if (reg & SYSMGR_ECC_OCRAM_SERR)
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writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN,
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&sysmgr_regs->eccgrp_ocram);
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if (reg & SYSMGR_ECC_OCRAM_DERR)
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writel(SYSMGR_ECC_OCRAM_DERR | SYSMGR_ECC_OCRAM_EN,
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&sysmgr_regs->eccgrp_ocram);
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memset(__bss_start, 0, __bss_end - __bss_start);
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socfpga_nic301_slave_ns();
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/* Configure ARM MPU SNSAC register. */
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setbits_le32(&scu_regs->sacr, 0xfff);
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/* Remap SDRAM to 0x0 */
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writel(0x1, &nic301_regs->remap); /* remap.mpuzero */
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writel(0x1, &pl310->pl310_addr_filter_start);
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board_init_r(NULL, 0);
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}
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u32 spl_boot_device(void)
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{
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return BOOT_DEVICE_RAM;
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}
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/*
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* Board initialization after bss clearance
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*/
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void spl_board_init(void)
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{
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unsigned long sdram_size;
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#ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
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const struct cm_config *cm_default_cfg = cm_get_default_config();
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#endif
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debug("Freezing all I/O banks\n");
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/* freeze all IO banks */
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sys_mgr_frzctrl_freeze_req();
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/* Put everything into reset but L4WD0. */
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socfpga_per_reset_all();
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/* Put FPGA bridges into reset too. */
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socfpga_bridges_reset(1);
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socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
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socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
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socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
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timer_init();
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debug("Reconfigure Clock Manager\n");
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/* reconfigure the PLLs */
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cm_basic_init(cm_default_cfg);
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/* Enable bootrom to configure IOs. */
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sysmgr_config_warmrstcfgio(1);
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/* configure the IOCSR / IO buffer settings */
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if (scan_mgr_configure_iocsr())
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hang();
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sysmgr_config_warmrstcfgio(0);
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/* configure the pin muxing through system manager */
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sysmgr_config_warmrstcfgio(1);
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sysmgr_pinmux_init();
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sysmgr_config_warmrstcfgio(0);
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#endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */
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/* De-assert reset for peripherals and bridges based on handoff */
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reset_deassert_peripherals_handoff();
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socfpga_bridges_reset(0);
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debug("Unfreezing/Thaw all I/O banks\n");
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/* unfreeze / thaw all IO banks */
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sys_mgr_frzctrl_thaw_req();
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/* enable console uart printing */
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preloader_console_init();
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if (sdram_mmr_init_full(0xffffffff) != 0) {
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puts("SDRAM init failed.\n");
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hang();
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}
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debug("SDRAM: Calibrating PHY\n");
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/* SDRAM calibration */
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if (sdram_calibration_full() == 0) {
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puts("SDRAM calibration failed.\n");
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hang();
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}
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sdram_size = sdram_calculate_size();
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debug("SDRAM: %ld MiB\n", sdram_size >> 20);
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/* Sanity check ensure correct SDRAM size specified */
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if (get_ram_size(0, sdram_size) != sdram_size) {
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puts("SDRAM size check failed!\n");
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hang();
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}
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socfpga_bridges_reset(1);
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}
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