mx3fb.c was based on CONFIG_LCD and is moved by this patch to
CONFIG_VIDEO, which has greater freedom in selecting videomodes
even at runtime.
This renders the accumulating list of display defines
(CONFIG_DISPLAY_VBEST..., CONFIG_DISPLAY_C057...) obsolete as
these may be setup through env variables:
uboot> setenv mydisplay 'video=ctfb❌240,y:320,depth:16,mode:0,pclk:185925,
le:9,ri:17,up:7,lo:10,hs:1,vs:1,sync:100663296,vmode:0'
uboot> setenv videomode ${mydisplay}
This commit also fixes the board config files for qong and
imx31_phycore boards as needed. The videomode settings of
previously supported displays are added to CONFIG_EXTRA_ENV_SETTINGS
now. CONFIG_SYS_MALLOC_LEN for imx31_phycore board is increased
to make the frame buffer allocation working with the changed
driver.
Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
The framebuffer driver for MX5 is based on CONFIG_LCD.
In the current implementation, there is a serious bug
because the required memory is allocated before
relocation, but the driver knows only later which is
the resolution of the display. The patch switches the driver
to CONFIG_VIDEO and the memory is allocated by the driver itself.
We also need to switch the vision2 board code and config file
in the same commit so that this commit will be bisectable.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Anatolij Gustschin <agust@denx.de>
Tested-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
In the recent dropping of !NET_MULTI code (commit e2a53458a7),
I misread the logic in include/net.h. Some of it was used by NET_MULTI
code as glue between the multi/non-multi worlds for cpm2 boards.
Rather than restore the block of code, push the logic to the board config
headers where it all belongs.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
A delay of approximately 250 ms after PCI bus reset in
pci_mpc5xxx_init() is needed to recognize the Coral-PA
controller on the graphic extention board.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Detlev Zundel <dzu@denx.de>
With older compilers (gcc-4.2.x) we run into issues that resulting image
is too large. We can save a bunch of space by removing the video support.
In general video support on these boards is a nice to have since it
requires a PCIe add-on card.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
- Rework tlb and law tables.
- PCI2 is not available on MPC8548CDS, so remove it.
- Move the memory map to the board config file.
- Rewrite the board info according to the manual.
- Remove unnecessary macros and redefine some macros to align with other boards.
- Fix some typos.
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 'master' of git://git.denx.de/u-boot-ppc4xx:
ppc4xx: Change DDR2 CL from 4 to 5 for intip
ppc4xx: Improve lm63 pwm on dlvision-10g
ppc4xx: Do not stop booting on any keypress on intip
Add support for the qi_lb60 (a.k.a QI Ben NanoNote) clamshell device
from Qi hardware:
http://en.qi-hardware.com/wiki/Ben_NanoNotehttp://en.qi-hardware.com/wiki/Main_Pagehttp://en.wikipedia.org/wiki/Qi_hardware
This Jz4740-based clamshell device does not use NOR flash to boot.
The initial bring-up assumes that U-Boot is directly loaded into SDRAM
using USB boot tool, and starts from 0x80100000.
About USB boot tool
-------------------
Jz4740 is one of the XBurst processors with USB boot functionality
supported. The CPU can boot from a small ROM in the LSI, initialize
CPU and USB module, then wait for USB commands from the USB host.
We can send 8 KB binary data to the CPU cache using USB boot tool.
USB boot tool is available to the public at Ingenic website. Also
there is an alternative Debian package named xburst-tools.
Signed-off-by: Xiangfu Liu <xiangfu@openmobilefree.net>
Acked-by: Daniel <zpxu@ingenic.cn>
Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
Some intip boards don't seem to run stable with CL4, datasheets suggest that
CL5 is the safe value.
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Fan PWM lookuptable was modified to start at 46 degrees
celsius instead of 40 degrees celsius.
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
Use CONFIG_AUTOBOOT_KEYED on intip so that booting can only be
stopped with well defined keypresses.
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
MPC8536DS offer booting from SDcard or SPI flash. This patch defined that
u-boot can save the environment variables on SDcard or SPI flash when
booting from the related device. The Env parameter region and linux
kernel region have overlap in SPI-Flash, So change the Env param saving
address.
Signed-off-by: Xie Xiaobo <r63061@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
1. The SD_DATA[4:7] signals are shared with the SPI chip selects on 8536DS,
so don't set MPC85xx_PMUXCR_SD_DATA that config eSDHC data bus-width
to 4-bit and enable SPI signals.
2. Add eSPI controller and SPI-FLASH definition.
Signed-off-by: Xie Xiaobo <r63061@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
- Increase the size of malloc space.
- Enable e1000 network card.
- Show pci devices on startup.
- Change the location of env address.
- Use hwconfig to turn off ECC by default.
[Kumar Gala] Fixed white space formating for CONFIG_EXTRA_ENV_SETTINGS
Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We really shouldn't be overwriting bat registers with translation enabled,
especially when we're executing code using one of them for translating
the current instruction stream. Instead, disable address translation
while doing the final BAT setup.
In order to do this, setup_bats has to move back to asm code, because we
require translation to be enabled to have a stack for C code. The yucky
thing about that is that the assembler doesn't like ULL so we have to
switch to using HIGH/LOW pairs for physical addresses that are > 32 bits
in length.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Acked-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
There were duplicate (and conflicting) defines for the BATs used
to cover SRIO. Drop the bogus set.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The macro CONFIG_ENABLE_36BIT_PHYS is used to indicate that the given SOC is
capable of 36-bit physical addresses, even if such large addresses are not
used. On two boards, this macro was enabled only when building a 36-bit
image.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Interactive DDR debugging provides a user interface to view and modify SPD,
DIMM parameters, board options and DDR controller registers before DDR is
initialized. With this feature, developers can fine-tune DDR for board
bringup and other debugging without frequently having to reprogram the flash.
To enable this feature, define CONFIG_FSL_DDR_INTERACTIVE in board header
file and set an environment variable to activate it. Syntax:
setenv ddr_interactive on
After reset, U-boot prompts before initializing DDR controllers
FSL DDR>
The available commands are
print print SPD and intermediate computed data
reset reboot machine
recompute reload SPD and options to default and recompute regs
edit modify spd, parameter, or option
compute recompute registers from current next_step to end
next_step shows current next_step
help this message
go program the memory controller and continue with u-boot
The first command should be "compute", which reads data from DIMM SPDs and
board options, performs the calculation then stops before setting DDR
controller. A user can use "print" and "edit" commands to view and modify
anything. "Go" picks up from current step with any modification and
compltes the calculation then enables the DDR controller to continue u-boot.
"Recompute" does it over from fresh reading.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Now that none of the core checks CONFIG_NET_MULTI, there's not much point
in boards defining it. So scrub all references to it.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
These drivers have never been converted to NET_MULTI, and they are only
used by one board (BMW). So drop the drivers until someone feels like
rewriting them for NET_MULTI support.
Rather than punting the BMW board completely, just disable net support
in its board config. Seems to build fine without it.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The current km_arm boards have a Power-On test jumper. When this
jumper is set, this triggers some Power-On tests on the board.
This patch enables the support of this jumper for starting the
memory_regions test when the jumper is set.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
This allows to test a larger part of the RAM in the memory tests.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
* 'master' of git://git.denx.de/u-boot-mpc85xx:
powerpc/p3060: Add SoC related support for P3060 platform
powerpc/85xx: Add support for setting up RAID engine liodns on P5020
powerpc/85xx: Refactor some defines out of corenet_ds.h
fm-eth: Add ability for board code to disable a port
powerpc/mpc8548: Add workaround for erratum NMG_LBC103
powerpc/mpc8548: Add workaround for erratum NMG_DDR120
powerpc/mpc85xxcds: Fix PCI speed
powerpc/mpc8548cds: Fix booting message
powerpc/p4080: Add support for secure boot flow
powerpc/85xx: Add Secure Boot support on P1010RDB for NOR, NAND & SPIFLASH
powerpc/85xx: Add PBL & SECUREBOOT support on P3041/P5020DS boards
powerpc/p2041rdb: remove watch dog related codes
powerpc/p2041rdb: updated description of cpld command
powerpc/p2041rdb: add more ddr frequencies support
powerpc/p2041rdb: set sysclk according to status of physical switch SW1
powerpc/p2041rdb: update cpld reset command according to CPLD 2.0
powerpc/mpc8349emds: Migrate from spd_sdram to unified DDR driver
powerpc/mpc83xx: Migrate from spd_sdram to unified DDR driver
powerpc/mpc8xxx: Add DDR2 to unified DDR driver
powerpc/mpc8xxx: Fix picos_to_mclk() and get_memory_clk_period_ps()
powerpc/mpc8xxx: Add SPD EEPROM address for single controller 2 slots
powerpc/mpc8xxx: Fix DDR code for empty first DIMM slot and enable DQS_en
powerpc/85xx: Refactor P2041RDB to use common p_corenet files
powerpc/85xx: refactor common P-Series CoreNet files for FSL boards
powerpc/85xx: Enable CMD_REGINFO on corenet boards
powerpc/85xx: p2041rdb - Remove unused 'execute' perm in TLB entries
powerpc/85xx: Fix USB protocol definitions for P1020RDB
powerpc/corenet_ds: Use separated speed tables for UDIMM and RDIMM
powerpc/mpc8xxx: Move DDR RCW overriding to common code
powerpc/mpc8xxx: Extend CWL table
powerpc/85xx: Cleanup how SVR_MAJ() is defined on MPC8536
powerpc/85xx: Cleanup extern in corenet_ds board code
powerpc/p2041rdb: Add ethernet support on P2041RDB board
powerpc/85xx: Add networking support to P1023RDS
powerpc/hydra: Add ethernet support on P5020/P3041 DS boards
powerpc/85xx: Add FMan ethernet support to P4080DS
powerpc/85xx: Add support for FMan ethernet in Independent mode
powerpc/mpc8548cds: Cleanup mpc8548cds.c
powerpc/mp: add support for discontiguous cores
powerpc/85xx: corenet_ds - Remove unused 'execute' perm in TLB entries
fdt: Add new fdt_create_phandle helper
fdt: Rename fdt_create_phandle to fdt_set_phandle
powerpc/85xx: Fix compile warnings/errors if CONFIG_SYS_DPAA_FMAN isn't set
fsl_ifc: Add the workaround for erratum IFC A-003399(enabled on P1010)
powerpc/P1010: Add workaround for erratum P1010-A003549 (related to IFC)
fsl_ifc: Add the workaround for erratum IFC-A002769 (enable on P1010)
powerpc/85xx: Expanding the window of CCSRBAR in AS=1 from 4k to 1M
powerpc/85xx: Add NAND/NAND_SPL support to P1010RDB
nand: Freescale Integrated Flash Controller NAND support
powerpc/85xx: Add basic support for P1010RDB
powerpc/85xx: Add support for new P102x/P2020 RDB style boards
powerpc/85xx: relocate CCSR before creating the initial RAM area
powerpc/85xx: introduce and document CONFIG_SYS_CCSRBAR macros
powerpc/85xx: Enable internal USB UTMI PHY on p204x/p3041/p50x0
powerpc/85xx: Add ULPI and UTMI USB Phy support for P1010/P1014
Add support for Job Queue/Ring LIODN for the RAID Engine on P5020. Each
Job Queue/Ring combo needs one id assigned for a total of 4 (2 JQs/2
Rings per JQ). This just handles RAID Engine in non-DPAA mode.
Signed-off-by: Santosh Shukla <santosh.shukla@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Move some SoC/board specific defines out of corenet_ds.h and into the
corresponding P3041DS/P4080DS/P5020.h.
We moved CONFIG_MMC, CONFIG_PCIE3, & CONFIG_FSL_NGPIXIS because the P3060
SoC/reference board does not have these devices and it will share the same
board code.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Pre u-boot Flow:
1. User loads the u-boot image in flash
2. PBL/Configuration word is used to create LAW for Flash at 0xc0000000
(Please note that ISBC expects all these addresses, images to be
validated, entry point etc within 0 - 3.5G range)
3. ISBC validates the u-boot image, and passes control to u-boot
at 0xcffffffc.
Changes in u-boot:
1. Temporarily map CONFIG_SYS_MONITOR_BASE to the 1M
CONFIG_SYS_PBI_FLASH_WINDOW in AS=1.
(The CONFIG_SYS_PBI_FLASH_WINDOW is the address map for the flash
created by PBL/configuration word within 0 - 3.5G memory range. The
u-boot image at this address has been validated by ISBC code)
2. Remove TLB entries for 0 - 3.5G created by ISBC code
3. Remove the LAW entry for the CONFIG_SYS_PBI_FLASH_WINDOW created by
PBL/configuration word after switch to AS = 1
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Kuldip Giroh <kuldip.giroh@freescale.com>
Acked-by: Wood Scott-B07421 <B07421@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
P2041RDB supports 3 sysclk frequencies, it's selected by SW1[6~8],
software need to read the SW1 status to decide what the sysclk needs.
SW1[8~6] : frequency
0 0 1 : 83.3MHz
0 1 0 : 100MHz
others: 66.667MHz
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
U-Boot BSP handle 0x3 offset for big endian systems.
Little endian Microblaze systems don't use any offset.
Signed-off-by: Michal Simek <monstr@monstr.eu>
The EST SBC8260 is over 10 years old, and the SBC8240 older than
that. With the tiny amount of RAM (by today's standards), there
really isn't anyone interested in running the latest U-boot on
these EOL products anymore.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
CC: jon.diekema@smiths-aerospace.com
* 'post' of git://git.denx.de/u-boot-blackfin:
Blackfin: uart: implement loop callback for post
Blackfin: bf537-stamp/bf548-ezkit: update POST flash block range
Blackfin: post: generalize led/button tests with GPIOs
Blackfin: bf537-stamp: drop uart/flash post tests
Blackfin: post: drop custom test list
Blackfin: bf537-stamp: convert to gpio post hotkey
Let common code set the machine ID.
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Let common code set the machine ID.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Jason Liu <jason.hui@linaro.org>
