Commit graph

217 commits

Author SHA1 Message Date
Tom Rini
d5dbc661c3 i.MX
----
 
 - mx7ulp : fix  WDOG
 - imx8 : Phytec
 - USB3 support for i.MX8
 
 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/8277
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Merge tag 'u-boot-imx-20210717' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

i.MX
----

- mx7ulp : fix  WDOG
- imx8 : Phytec
- USB3 support for i.MX8

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/8277
2021-07-17 10:52:21 -04:00
Ye Li
4266dc1dff phy: phy-imx8mq-usb: Add USB PHY driver for i.MX8MQ
Add the USB PHY driver for i.MX8MQ to work with DWC3 USB controller.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Patrick Wildt <patrick@blueri.se>
Tested-by: Patrick Wildt <patrick@blueri.se>
2021-07-17 13:12:23 +02:00
Stephan Gerhold
4559df9e81 phy: Add driver for ST-Ericsson AB8500 USB PHY
The AB8500 PMIC contains an USB PHY that needs to be set up in
device or host mode to make USB work properly. Add a simple driver
for the generic PHY uclass that allows enabling it.

The if (CONFIG_IS_ENABLED(USB_MUSB_HOST)) might be a bit strange.
The USB PHY must be configured in either host or device mode and
somehow the USB PHY driver must be made aware of the mode.

Actually, the MUSB driver used together with this PHY does not
support dynamic selection of host/device mode in U-Boot at the moment.
Therefore, one very simple approach that works fine is to select
the mode to configure at compile time. When the MUSB driver is
configured in host mode the PHY is configured in host mode, and
similarly when the MUSB driver is configured in device/gadget mode.

Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-07-14 16:48:15 -04:00
Kunihiko Hayashi
b0415d826f phy: socionext: Add UniPhier PCIe PHY driver
Add PCIe PHY driver support for Pro5, LD20 and PXs3 SoCs.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
2021-07-14 16:48:07 -04:00
Paul Kocialkowski
0d5824cbc9 phy: sun4i-usb: Fix PHY0 routing and passby configuration for MUSB
Recent Allwinner platforms (starting with the H3) only use the MUSB
controller for peripheral mode and use HCI for host mode. As a result,
extra steps need to be taken to properly route USB signals to one or
the other. More precisely, the following is required:
* Routing the pins to either HCI/MUSB (controlled by PHY);
* Enabling USB PHY passby in HCI mode (controlled by PMU).

The current code will enable passby for each PHY and reroute PHY0 to
MUSB, which is inconsistent and results in broken USB peripheral support.

Passby on PHY0 must only be enabled when we want to use HCI. Since
host/device mode detection is not available from the PHY code and
because U-Boot does not support changing the mode dynamically anyway,
we can just mux the controller to MUSB if it is enabled and mux it to
HCI otherwise.

This fixes USB peripheral support for platforms with PHY0 dual-route,
especially H3/H5 and V3s.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-07-10 01:22:09 +01:00
Patrick Delaunay
b953ec2bca dm: define LOG_CATEGORY for all uclass
Define LOG_CATEGORY for all uclass to allow filtering with
log command.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-07-06 10:38:03 -06:00
Grzegorz Jaszczyk
82c30736ae phy: marvell: utmi: update utmi config which fixes usb2.0 instability
- Add additional step which enables the Impedance and PLL calibration.
- Enable old squelch detector instead of the new analog squelch detector
circuit and update host disconnect threshold value.
- Update LS TX driver strength coarse and fine adjustment values.

Change-Id: Ifa0a585bfb5ecab0bfa033eed6874ff98b16a7df
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
2021-04-29 07:45:24 +02:00
Igal Liberman
341e548eb8 phy: marvell: add support for SFI1
In CP115, comphy4 can be configured into SFI port1
(in addition to SFI0). This patch adds the option
described above.

In addition, rename all existing SFI/XFI references:
COMPHY_TYPE_SFI --> COMPHY_TYPE_SFI0

No functional change for exsiting configuration.

Change-Id: If9176222e0080424ba67347fe4d320215b1ba0c0
Signed-off-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2021-04-29 07:45:24 +02:00
Grzegorz Jaszczyk
a007f23626 phy: marvell: fix pll initialization for second utmi port
According to Design Reference Specification the PHY PLL and Calibration
register from PHY0 are shared for multi-port PHY. PLL control registers
inside other PHY channels are not used.

This commit reworks utmi device tree nodes in a way that common PHY PLL
registers are moved to main utmi node. Accordingly both child nodes
utmi-unit range is reduced and register offsets in utmi_phy.h are updated
to this change.

This fixes issues in scenarios when only utmi port1 was in use, which
resulted with lack of correct pll initialization.

Change-Id: Icc520dfa719f43a09493ab31f671efbe88872097
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
2021-04-29 07:45:24 +02:00
Grzegorz Jaszczyk
76342ac5c8 phy: marvell: allow to initialize up to 6 USB ports
New products can contain up to 6 usb ports, therefore allow to initialize
all relevant UTMI PHYs.

Change-Id: I28c36e59fa0e3e338bb3ee0cee2240b923f39785
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Kostya Porotchkin <Kostya.Porotchkin@cavium.com>
2021-04-29 07:45:24 +02:00
Igal Liberman
80ebc63cc9 phy: marvell: cp110: mark u-boot power-off calls
It helps ATF to determine who called power off
function (U-boot/Linux) and act accordingly

Change-Id: Icfc5cbfdba64754496812154272b28c0ff639f0f
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com>
2021-04-29 07:45:24 +02:00
Christine Gharzuzi
f596b01b9a phy: marvell: fix handling of unconnected comphy
- the default value of comphy pipe selector is set to PCIe (x4)
  in case of unconnected comphy the default value remains 0x4
  which may lead to several issues with comphy initialization.

- this patch adds SMC call that powers off the comphy lane in case of
  unconnected comphy.

Change-Id: I196b2916518dd8df3b159ffa85e2989b8e483087
Signed-off-by: Christine Gharzuzi <chrisg@marvell.com>
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com>
2021-04-29 07:45:24 +02:00
Igal Liberman
5f41aaf4c3 phy: marvell: pass sgmii id to firmware
Currently, we don't pass id for SGMII 0/1.
A bug in comphy selector configuration was found (in comphy
firmware), after fixing it, SGMII0/1 have different configuration,
so we need to pass the ID the firmware.

Change-Id: Idcff4029cc9cf018278e493221b64b33574e0d38
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com>
2021-04-29 07:45:24 +02:00
Grzegorz Jaszczyk
cd2caff77f phy: marvell: cp110: clean up driver after it was moved to atf
Change-Id: I358792a96c13b54e700c05227cc7a8f6bd584694
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
2021-04-29 07:45:24 +02:00
Grzegorz Jaszczyk
affd61f51c phy: marvell: cp110: remove both phy and pipe selector configuration
Now the comphy configuration is handled in atf, therefore there is no
need to configure phy or pipe selector in u-boot, it is configured by
atf for each particular pair: lane and mode.

Change-Id: I0bebf8d5ff66dbeb6bf9ef90876195938a8eb705
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
2021-04-29 07:45:24 +02:00
Grzegorz Jaszczyk
2e28b597fa phy: marvell: cp110: let the firmware perform training for XFI
Replace the XFI training with appropriate SMC call, so the firmware will
perform exact initialization.

Update Stefan 2021-03-23:
Move comphy_smc() function to an earlier place - necessary for the
mainline merge.

Change-Id: I789b130b05529dc80dadcf66aef407d93595b762
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Igal Liberman <igall@marvell.com>
2021-04-29 07:45:24 +02:00
Grzegorz Jaszczyk
f635c3b3a2 phy: marvell: cp110: let the firmware configure comphy for USB
Replace the comphy initialization for USB with appropriate SMC call,
so the firmware will execute required serdes configuration.

Change-Id: I7f773c0dfac70db9dd2653de2cdcfac577e78c4e
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
2021-04-29 07:45:24 +02:00
Grzegorz Jaszczyk
26d9763f3b phy: marvell: cp110: let the firmware configure comphy for RXAUI
Replace the comphy initialization for RXAUI with appropriate SMC call,
so the firmware will execute required serdes configuration.

Change-Id: Iedae0285fb283e05bb263a8b4ce46e8e7451a309
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
2021-04-29 07:45:24 +02:00
Marcin Wojtas
5ed3dc27bb phy: marvell: cp110: remove unused definitions
Even if comphy types of SATA2/SATA3/SGMII3 and comphy speeds of
1.5G/3G/6.25G were referenced in the driver non configuration (dts)
was using it.

This patch removes unused definitions.

Change-Id: I53ed6f9d3a82b9d18cb4e488bc14d3cf687f9488
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2021-04-29 07:45:24 +02:00
Igal Liberman
b21e1f36d4 phy: marvell: enable comphy info prints for all devices
Change-Id: I3b97253e7102a0868440a9e0200acc1c7919c743
Signed-off-by: Igal Liberman <igall@marvell.com>
2021-04-29 07:45:24 +02:00
Igal Liberman
e49cdbe10b phy: marvell: add RX training command
This patch adds support for running RX training using new command called
"rx_training"
Usage:
rx_training - rx_training <cp id> <comphy id>

RX training allows to improve link quality (for SFI mode)
by running training sequence between us and the link partner,
this allows to reach better link quality then using static configuration.

Change-Id: I818fe67ccaf19a87af50d4c34a9db7d6802049a5
Signed-off-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
2021-04-29 07:45:24 +02:00
Igal Liberman
7b27e608f8 phy: marvell: save comphy_map_data priv structure
This allows the lower level driver access to comphy map data
(required for RX training support, which is introduced
in the following patches).

Change-Id: Ib7ffdc4b32076c01c3a5d33f59552c9dfc6b12fa
Signed-off-by: Igal Liberman <igall@marvell.com>
2021-04-29 07:45:24 +02:00
Igal Liberman
c2bf42f5fd phy: marvell: fix several minor bugs in comphy_probe
If fdtdec_get_int can't find speed, set COMPHY_SPEED_INVALID
If fdtdec_get_int can't find type, set COMPHY_TYPE_INVALID
Move the error print if phy-type is invalid
Add continue to the probe loop (in a case of invalid phy)
Cosmetic changes

Change-Id: I0c61b40bfe685437426fe907942ed338b7845378
Signed-off-by: Igal Liberman <igall@marvell.com>
2021-04-29 07:45:24 +02:00
Igal Liberman
3e69b4abff phy: marvell: cp110: utmi: update analog parameters according to latest ETP
Add UTMI analog parameters initialization values according to
latest ETP.

Change-Id: I5bcca205a3995202a18ff126f371a81f69e205c8
Signed-off-by: Igal Liberman <igall@marvell.com>
2021-04-29 07:45:24 +02:00
Omri Itach
22bc868e49 phy: marvell: cp110: initialize only enabled UTMI units
UTMI should be initialized only for enabled device tree nodes.

This fix overrides current internal configuration array
entry with the next DT entry data if error is detected
during the current DT entry parsing or the current port
is disabled.

This way the internal configuration structure will only
contain valid ports information obtained from the DT.

Change-Id: I9c43c6a5d234e15ae9005d1c9bc983fc1f3544b8
Signed-off-by: Omri Itach <omrii@marvell.com>
Signed-off-by: Ken Ma <make@marvell.com>
2021-04-29 07:45:24 +02:00
Igal Liberman
89351ba4c8 phy: marvell: add missing speed during info prints
In get_speed_string() we have an array (speed_strings[])
which includes all possible speed strings.
This array size and content must be aligned to the speed
defines in comphy_data.h.

This patch adds missing 5.125G speed, aligns speed_strings[]
and fixes incorrect printing when speed > 5.0G.

Change-Id: I9900d23595094be321be0c62fcaa88036324568e
Signed-off-by: Igal Liberman <igall@marvell.com>
2021-04-29 07:45:24 +02:00
Igal Liberman
2dbba24088 phy: marvell: rename comphy related definitions to COMPHY_XX
Currently, all comphy definitions are PHY_TYPE_XX and PHY_SPEEED_XX.
Those definition might be confused with MDIO PHY definitions.

This patch does the following changes:
 - PHY_TYPE_XX --> COMPHY_TYPE_XX
 - PHY_SPEED_XX --> COMPHY_SPEED_XX

This improves readability, no functional change.

Change-Id: I2bd1d9289ebbc5c16fa80f9870f797ea1bcaf5fa
Signed-off-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2021-04-29 07:45:24 +02:00
jinghua
4568e2041c phy: marvell: add comphy type PHY_TYPE_USB3
- For some Marvell SoCs, like armada-3700, there are both
  USB host and device controller, but on PHY level the
  configuration is the same.
- The new type supports both USB device and USB host
- This patch is cherry-picked from u-boot-2015 as-is.

Change-Id: I01262027edd8ec23391cff6fb409b3009aedfbb9
Signed-off-by: jinghua <jinghua@marvell.com>
Signed-off-by: Ken Ma <make@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
2021-04-29 07:45:23 +02:00
Neil Armstrong
320160cd97 phy: meson-g12a-usb3-pcie: add support for PCIe ops
Add the PCIe part of the G12A USB3 PCIe Combo PHY driver.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-04-19 16:59:33 +02:00
Marek Vasut
1220aa9a65 phy: nop-phy: Add standard usb-nop-xceiv compat string
The USB no-op PHY uses "usb-nop-xceiv" compatible string. This driver is
compatible with USB no-op PHY, so add the compatible string.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Alexey Brodkin <alexey.brodkin@synopsys.com>
Cc: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Jean-Jacques Hiblot <jjhiblot@ti.com>
Cc: Murali Karicheri <m-karicheri2@ti.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>
2021-04-18 04:29:35 +02:00
Tom Rini
2ae80437fb Merge branch '2021-02-02-drop-asm_global_data-when-unused'
- Merge the patch to take <asm/global_data.h> out of <common.h>
2021-02-15 10:16:45 -05:00
Neil Armstrong
4547551aa0 phy: Add Amlogic AXG MIPI PCIe Analog PHY driver
The Amlogic AXG MIPI + PCIe Analog PHY provides function for both PCIe and
MIPI DSI at the same time, and provides the Analog part of MIPI DSI transmission
and Analog part of the PCIe lines.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-02-10 10:00:51 +01:00
Neil Armstrong
7ef19503ba phy: Add Amlogic AXG MIPI D-PHY driver
The Amlogic AXG SoCs embeds a MIPI D-PHY used to communicate with DSI
panels.

This D-PHY depends on a separate analog PHY.

Signed-off-by:Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-02-10 10:00:51 +01:00
Neil Armstrong
f8da8a82c5 generic-phy: add configure op
Add the PHY configure op callback to the generic PHY uclass to permit
configuring the PHY.

It's useful for MIPI DSI PHYs to setup the link timings.

Signed-off-by:Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-02-10 10:00:51 +01:00
Neil Armstrong
afef20585a phy: dphy: Add configuration helpers
The MIPI D-PHY spec defines default values and boundaries for most of the
parameters it defines. Introduce helpers to help drivers get meaningful
values based on their current parameters, and validate the boundaries of
these parameters if needed.

These helpers and header are taken from Linux commit 9123e3a74ec7 ("Linux 5.9-rc1").

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-02-10 10:00:51 +01:00
Simon Glass
401d1c4f5d common: Drop asm/global_data.h from common header
Move this out of the common header and include it only where needed.  In
a number of cases this requires adding "struct udevice;" to avoid adding
another large header or in other cases replacing / adding missing header
files that had been pulled in, very indirectly.   Finally, we have a few
cases where we did not need to include <asm/global_data.h> at all, so
remove that include.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-02-02 15:33:42 -05:00
Weijie Gao
b4f214f044 phy: add USB PHY driver for MediaTek MT7620 SoC
This patch adds USB PHY driver for MediaTek MT7620 SoC

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2021-01-24 21:39:26 +01:00
Shawn Lin
9ddc0787bd pci: Add Rockchip dwc based PCIe controller driver
Add Rockchip dwc based PCIe controller driver for rk356x platform.
Driver support Gen3 by operating as a Root complex.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2021-01-21 12:00:45 +08:00
Shawn Lin
6ec62b6ca6 phy: rockchip: Add Rockchip Synopsys PCIe 3.0 PHY
Add the Rockchip Synopsys based PCIe 3.0 PHY driver as
part of Generic PHY framework.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2021-01-21 12:00:45 +08:00
Patrick Delaunay
0d5fbadeff phy: stm32-usbphyc: migrate trace to dev and log macro
Change pr_debug to log_debug or dev_dbg macro and define LOG_CATEGORY.

Remove the "%s:" __func__  header as it is managed by dev macro
(dev->name is displayed) or log macro (CONFIG_LOGF_FUNC).

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2021-01-13 09:52:58 +01:00
Tom Rini
b11f634b1c Driver model: make some udevice fields private
Driver model: Rename U_BOOT_DEVICE et al.
 dtoc: Tidy up and add more tests
 ns16550 code clean-up
 x86 and sandbox minor fixes for of-platdata
 dtoc prepration for adding build-time instantiation
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Merge tag 'dm-pull-5jan21' of git://git.denx.de/u-boot-dm into next

Driver model: make some udevice fields private
Driver model: Rename U_BOOT_DEVICE et al.
dtoc: Tidy up and add more tests
ns16550 code clean-up
x86 and sandbox minor fixes for of-platdata
dtoc prepration for adding build-time instantiation
2021-01-05 22:34:43 -05:00
Tom Rini
720620e691 Prepare v2021.01-rc5
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Merge tag 'v2021.01-rc5' into next

Prepare v2021.01-rc5

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-01-05 16:20:26 -05:00
Simon Glass
f10643cf8a dm: core: Access device ofnode through functions
At present ofnode is present in the device even if it is never used. With
of-platdata this field is not used, so can be removed. In preparation for
this, change the access to go through inline functions.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-01-05 12:24:41 -07:00
Simon Glass
c69cda25c9 dm: treewide: Rename dev_get_platdata() to dev_get_plat()
Rename this to be consistent with the change from 'platdata'.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13 16:51:09 -07:00
Simon Glass
caa4daa2ae dm: treewide: Rename 'platdata' variables to just 'plat'
We use 'priv' for private data but often use 'platdata' for platform data.
We can't really use 'pdata' since that is ambiguous (it could mean private
or platform data).

Rename some of the latter variables to end with 'plat' for consistency.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13 16:51:08 -07:00
Simon Glass
41575d8e4c dm: treewide: Rename auto_alloc_size members to be shorter
This construct is quite long-winded. In earlier days it made some sense
since auto-allocation was a strange concept. But with driver model now
used pretty universally, we can shorten this to 'auto'. This reduces
verbosity and makes it easier to read.

Coincidentally it also ensures that every declaration is on one line,
thus making dtoc's job easier.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13 08:00:25 -07:00
Patrice Chotard
0f8106f8e0 treewide: Update email address Patrick Delaunay and Patrice Chotard
Update Patrick and my email address with the one dedicated to
upstream activities.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-12-09 10:57:50 +01:00
Patrick Delaunay
c480138958 phy: stm32: usbphyc: manage optional vbus regulator on phy_power_on/off
This patch adds support for optional vbus regulator.
It is managed on phy_power_on/off calls and may be needed for host mode.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-11-25 12:02:58 +01:00
Jaehoon Chung
85c9a7ba8c phy: meson-g12a-usb2: fix the potential build warning
Fix the potential build warning.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-11-12 14:27:38 +01:00
Igal Liberman
3261f6d390 phy: marvell: cp110: update mode parameter for pcie power on calls
It helps ATF to determine who called power on function (U-boot/Linux).

The corresponding ATF code was added in this commit:

  mvebu: cp110: avoid pcie power on/off sequence when called from Linux
  55df84f974

Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
2020-10-29 08:00:12 +01:00