A recent change to disable cache setup when booting from coreboot
assumed that this has been done by SPL. The result is that for the
coreboot board, the cache is disabled (in start.S) and never
re-enabled.
If the cache was turned off, as it is on boards without SPL, we should
turn it back on. Add this new condition.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
These constants conflict with error codes returned by the MP
implementation when something is wrong. In particular, mp_first_cpu()
returns MP_SELECT_BSP when running without multiprocessing enabled.
Since this is -2, it is interpreted as an error by callers, which
expect a positive CPU number for the first CPU.
Correct this by using a different range for the pre-defined CPU
numbers, above zero and out of the range of possible CPU values. For
now it is safe to assume there are no more than 64K CPUs.
This fixes the 'mtrr' command when CONFIG_SMP is not enabled.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
When starting U-Boot from a previous-stage bootloader we presumably don't
need to set up the variable MTRRs. In fact this could be harmful if the
existing settings are not what U-Boot uses.
Skip that step in this case.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
If fixup offset is zero then there is nothing to fix. All calculation in
this case just increase addresses by value zero which results in identity.
So in this case skip whole fixup re-calculation as it is not needed.
This is just an optimization for special case when fix_offset is zero which
skips code path which does only identity operations (meaning nothing). No
functional changes.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Stefan Roese <sr@denx.de>
The U-Boot "stemmy" board is mainly intended to simplify booting
mainline Linux on various smartphones from Samsung based on ST-Ericsson
Ux500. While the mainline kernel is working great, there are still some
features missing there. In particular, it is currently not possible to
charge the battery when using the mainline kernel.
This means that it is still necessary to boot the downstream/vendor
kernel from Samsung sometimes to charge the device. That kernel is
ancient, still uses board files + ATAGS instead of device trees and
relies on a strange very long kernel command line hardcoded in the
Samsung bootloader.
Actually, since mainline is booted with device trees there is a very
simple way to make the old downstream kernel work as well: We can
simply take most of the ATAGS passed to U-Boot from the Samsung
bootloader and copy them as-is when booting a kernel without device
tree. That way the long command line and other needed ATAGS are copied
as-is without having to bother with them.
The only exception is the ATAG_INITRD - since the initrd is loaded
by U-Boot, the atag for that should be generated in U-Boot so it points
to the correct address. All other ATAGS are copied as-is and not
generated in U-Boot.
Also use the chance and provide a serial# for U-Boot by parsing the
ATAG_SERIAL that is also passed by the Samsung bootloader.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
At the moment the "stemmy" board attempts to detect the RAM size with
a simple memory test (get_ram_size()). Unfortunately, this does not work
correctly for devices with 768 MiB RAM (e.g. Samsung Galaxy Ace 2
(GT-I8160), "codina"). Reading/writing memory after the 768 MiB RAM
succeeds but actually overwrites some earlier parts of the memory.
For U-Boot this does not result in any major problems, but on Linux
this will eventually lead to strange crashes because of the memory
corruption.
Since the "stemmy" U-Boot port is designed to be chainloaded from
the original Samsung bootloader, the most reliable way to get the
available amount of RAM is to look at the ATAGS passed by the Samsung
bootloader. Fortunately, the header used to generate ATAGS in U-Boot
(asm/setup.h) can also be easily used to parse them.
Also clarify and simplify stemmy.h a bit to make it more clear where
some of the magic values in there are actually coming from.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Add the device tree for Akebi96. Akebi96 is a 96boards certified
development board based on UniPhier LD20.
( https://www.96boards.org/product/akebi96/ )
Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
According to arch/arm/lib/crt0_64.S, the BSS section is "UNAVAILABLE"
and uninitialized before relocation. Also, it overlaps with the
appended DTB before relocation, so writing data into a variable
in the BSS section might corrupt the appended DTB.
Unfortunately, pinctrl-apq8016.c and pinctrl-apq8096.c do place the
"pin_name" variable in the BSS section (since it's uninitialized).
It's also used before relocation, when setting up the pinctrl for
the serial driver.
On DB410c this causes "GPIO_5" to be written into some part of an
appended DTB, e.g.:
80111820: edfe0dd0 9f100000 38000000 c00e0000 ...........8....
80111830: 28000000 11000000 10000000 00000000 ...(............
80111840: 4f495047 8800355f 00000000 00000000 GPIO_5..........
80111850: 00000000 00000000 01000000 00000000 ................
80111860: 03000000 04000000 00000000 02000000 ................
80111870: 03000000 04000000 0f000000 02000000 ................
80111880: 03000000 2d000000 1b000000 6c617551 .......-....Qual
80111890: 6d6d6f63 63655420 6c6f6e68 6569676f comm Technologie
Depending on the part of the DTB that is corrupted this might not
cause any problems, but it can also result in strange reboots
without any serial output.
Fortunately, in practice this does not cause issues on DB410c yet
because board_fdt_blob_setup() in dragonboard410c.c currently
overrides the appended DTB with the one passed by the previous
bootloader (LK) (which does not get corrupted).
DB820c does not have board_fdt_blob_setup() so I would expect it to
be affected by this problem. Perhaps everyone was just fortunate to
not compile an U-Boot configuration where the pin_name corrupts an
important part of the DTB.
Make sure "pin_name" is explicitly placed in the .data section
instead of .bss to fix this.
Cc: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
In case the iMX8M boot from eMMC boot partition and the primary image
is corrupted, the BootROM is capable of starting a secondary image in
the other eMMC boot partition as a fallback.
However, the BootROM leaves the eMMC BOOT_PARTITION_ENABLE setting as
it was, i.e. pointing to the boot partition containing the corrupted
image, and the BootROM does not provide any indication that this sort
of fallback occured.
According to AN12853 i.MX ROMs Log Events, Rev. 0, May 2020, it is
possible to determine whether fallback event occurred by parsing the
ROM event log. In case ROM event ID 0x51 is present, fallback event
did occur.
This patch implements ROM event log parsing and search for event ID
0x51 for all iMX8M SoCs, and based on that corrects the eMMC boot
partition selection. This way, the SPL loads the remaining boot
components from the same eMMC boot partition from which it was
started, even in case of the fallback.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Faiz Abbas <faiz_abbas@ti.com>
Cc: Harald Seiler <hws@denx.de>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Fix the dsa switch config:
- remove the unnecessary phy-mode from the switch itself
- added the necessary fixed-link node to the non-cpu ports required
for U-Boot DSA
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
The Gateworks GW7901 is an ARM based single board computer (SBC)
featuring:
- i.MX8M Mini SoC
- LPDDR4 DRAM
- eMMC FLASH
- SPI FRAM
- Gateworks System Controller (GSC)
- Atmel ATECC Crypto Authentication
- USB 2.0
- Microchip GbE Switch
- Multiple multi-protocol RS232/RS485/RS422 Serial ports
- onboard 802.11ac WiFi / BT
- microSD socket
- miniPCIe socket with PCIe, USB 2.0 and dual SIM sockets
- Wide range DC power input
- 802.3at PoE
To add support for this board:
- add dts from Linux (accepted for v5.14)
- add SPL PMIC config
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Make macros actually use passed parameter instead of local variables
that happen
to be named the same as symbols in macro expansion.
Signed-off-by: Kacper Kubkowski <kkubkowski@fluence.pl>
With the first redesign the debug UART had changed from
UART2 to UART1.
As the first hardware revision is considered as alpha and
will not be supported in future. The old setup will not
be preserved.
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
This update includes eqos support and some minor changes.
Synced with kernel commit
412627f6ffe3 ("arm64: dts: imx8mp-phyboard-pollux-rdk: Add missing pinctrl entry")
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Factor out the common node settings for dm-spl and dm-pre-reloc
and move them to imx8mp-u-boot.dtsi
Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
If reset-gpio is defined by device-tree use that if
CONFIG_PCIE_IMX_PERST_GPIO is not defined.
Note that after this the following boards which define
CONFIG_PCIE_IMX_PERST_GPIO in their board header file as well as their
device-tree should be able to remove CONFIG_PCIE_IMX_PERST_GPIO without
consequence:
- mx6sabresd
- mx6sxsabresd
- novena
- tbs2910
- vining_2000
Note that the ge_bx50v3 board uses CONFIG_PCIE_IMX_PERST_GPIO and does
not have reset-gpios defined it it's pcie node in the dt thus removing
CONFIG_PCIE_IMX_PERST_GPIO globally can't be done until that board adds
reset-gpios.
Cc: Ian Ray <ian.ray@ge.com> (maintainer:GE BX50V3 BOARD)
Cc: Sebastian Reichel <sebastian.reichel@collabora.com> (maintainer:GE BX50V3 BOARD)
Cc: Fabio Estevam <festevam@gmail.com> (maintainer:MX6SABRESD BOARD)
Cc: Marek Vasut <marex@denx.de> (maintainer:NOVENA BOARD)
Cc: Soeren Moch <smoch@web.de> (maintainer:TBS2910 BOARD)
Cc: Silvio Fricke <open-source@softing.de> (maintainer:VINING_2000 BOARD)
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Some IPs have their accessible address space restricted by the
interconnect. Let's make sure U-Boot only ever uses the space below
the 4G address boundary (which is 3GiB big), even when the effective
available memory is bigger.
We implement board_get_usable_ram_top() for all i.MX8M SoCs, as the
whole family is affected by this.
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Aside from the usual fixes and updates one visible change is the
MMC update, which fixes some lingering bugs and gives a decent speed
increase on some boards (9->19 MB/s on H6, 21->43 MB/s on A64 eMMC).
I am keeping an watchful eye on bug reports here, to spot any correctness
regressions.
Another change is finally the enablement of the first USB host port on
many boards without micro-USB (data) sockets, like the Pine64 family.
That doubles the number of usable USB ports from 1 to 2 on those boards.
Some smaller fixes, 4GB DRAM support (on the H616) and a new board (ZeroPi)
conclude this first round of changes.
Compile-tested for all 157 sunxi boards, boot-tested on Pine H64,
Pine64-LTS, OrangePi Zero 2 and BananaPi M2 Berry.
Summary:
- DT update for H3/H5/H6
- Enable first USB port on boards without micro-USB
- ZeroPi board support
- 4GB DRAM support for H616 boards
- MMC fixes and speed improvement
- some fixes
To avoid the complexity of DMA operations (with chained descriptors), we
use repeated MMIO reads and writes to the SD_FIFO_REG, which allows us
to drain or fill the MMC data buffer FIFO very easily.
However those MMIO accesses are somewhat costly, so this limits our MMC
performance, to between 17 and 22 MB/s, but down to 9.5 MB/s on the H6
(partly due to the lower AHB1 frequency).
As it turns out we read the FIFO status register after *every* word we
read or write, which effectively doubles the number of MMIO accesses,
thus effectively more than halving our performance.
To avoid this overhead, we can make use of the FIFO level bits, which are
in the very same FIFO status registers.
So for a read request, we now can collect as many words as the FIFO
level originally indicated, and only then need to update the status
register.
We don't know for sure the size of the FIFO (and it seems to differ
across SoCs anyway), so writing is more fragile, which is why we still
use the old method for that. If we find a minimum FIFO size available on
all SoCs, we could use that, in a later optimisation.
This patch increases the eMMC read speed on a Pine64-LTS from about
22MB/s to 44 MB/s. SD card reads don't gain that much, but with 23 MB/s
we now reach the practical limit for 3.3V SD cards.
On the H6 we double our transfer speed, from 9.5 MB/s to 19.7 MB/s.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
All SoCs since the Allwinner A64 (H5, H6, R40, H616) feature the so
called "new timing mode", so enable this in Kconfig for those SoCs.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Most Allwinner SoCs which use the so called "new timing mode" in their
MMC controllers actually use the double-rate PLL6/PERIPH0 clock as their
parent input clock. This is interestingly enough compensated by a hidden
"by 2" post-divider in the mod clock, so the divider and actual output
rate stay the same.
Even though for the H6 and H616 (but only for them!) we use the doubled
input clock for the divider computation, we never accounted for the
implicit post-divider, so the clock was only half the speed on those SoCs.
This didn't really matter so far, as our slow MMIO routine limits the
transfer speed anyway, but we will fix this soon.
Clean up the code around that selection, to always use the normal PLL6
(PERIPH0(1x)) clock as an input. As the rate and divider are the same,
that makes no difference.
Explain the hardware differences in a comment.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
The H616 is our first supported Allwinner SoC which goes beyond the 4GB
address space "barrier", by having more than 32 address bits.
Lift the preliminary 3GB DRAM limit for the H616, and update the page
table setup on the way, to actually map that last GB as well.
As not all devices are actually capable of dealing with more than 32
bits (the DMA in the EMAC for instance), we also limit U-Boot's own
DRAM usage to 4GB on the way.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
ZeroPi is a new board of high performance with low cost
designed by FriendlyElec., using the Allwinner H3 SOC.
ZeroPi features
- Allwinner H3, Quad-core Cortex-A7@1.2GHz
- 256MB/512MB DDR3 RAM
- microsd slot
- 10/100/1000Mbps Ethernet
- Debug Serial Port
- DC 5V/2A power-supply
Signed-off-by: Yu-Tung Chang <mtwget@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Most clock factors and dividers in the H6 PLLs use a "+1 encoding",
which we were missing on two occasions.
This fixes the MMC clock setup on the H6, which could be slightly off due
to the wrong parent frequency:
mmc 2 set mod-clk req 52000000 parent 1176000000 n 2 m 12 rate 49000000
Also the CPU frequency (PLL1) was a tad too high before.
For PLL5 (DRAM) we already accounted for this +1, but in the DRAM code
itself, not in the bit field macro. Move this there to be aligned with
what the other SoCs and other PLLs do.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Update the H3 DT files from the Linux 5.12 release.
The changes update some boards, and don't affect U-Boot, but fix Gigabit
Ethernet when this DT is passed on to the Linux kernel.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Update the H5 DT files from the Linux 5.12 release.
The changes don't affect U-Boot at all, but fix Gigabit Ethernet when
this DT is passed on to the Linux kernel. It also introduces DVFS.
This also updates the shared sunxi-h3-h5.dtsi, but that only adds nodes
that are of no concern to U-Boot.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Update the H6 DT files from the Linux 5.12 release.
The changes are minimal (many LED node renames), but also help to enable
USB port 0 in U-Boot (later), enable the RSB device (not yet used in
U-Boot), and also introduce an MMC frequency limit.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
As seen with clang-12:
warning: __asm_invalidate_l3_dcache changed binding to STB_WEAK
As we indeed use ENTRY and then declare the function weak manually. Use
the WEAK declarative from <linux/linkage.h> instead.
Signed-off-by: Tom Rini <trini@konsulko.com>
On arm64, board info is not applicable and kernel command line patched into
the DT, so the LMB reservation here makes no sense anymore. On legacy arm32,
this might still be necessary on systems which do not use DT or use legacy
ATAGS. Disable this LMB reservation on arm64.
This also permits Linux DT to specify reserved memory node at address close
to the end of DRAM bank, i.e. overlaping with U-Boot location. Since after
boot, U-Boot will be no more, this is OK.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Hai Pham <hai.pham.ud@renesas.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Tom Rini <trini@konsulko.com>
Fix following compilation issue when SYS_DCACHE_OFF is enable:
drivers/misc/scmi_agent.c:128: undefined reference to `mmu_set_region_dcache_behaviour'
when SYS_DCACHE_OFF is enable, mmu_set_region_dcache_behaviour() must be
defined.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
On implementations that support VHE, the layout of the CPTR_EL2
register depends on whether HCR_EL2.E2H is set. If the bit is
set, CPTR_EL2 uses the same layout as CPACR_EL1 and can in fact
be accessed through that register. In that case, jump to the
EL1 code to enable access to the FP/SIMD registers. This allows
U-Boot to run on systems that pass control to U-Boot in EL2 with
EL2 Host mode enabled such as machines using Apple's M1 SoC.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Acked-by: Marc Zyngier <maz@kernel.org>
While this platform has not yet been converted, there is active efforts
to do so. Keep the platform for now.
This reverts commit aa697e6904.
Signed-off-by: Tom Rini <trini@konsulko.com>
These boards have not been converted to CONFIG_DM_USB by the deadline
and is also missing conversion to CONFIG_DM. Remove them. As this is
the last of the SPEAr platforms, so remove the rest of the remaining
support as well.
Cc: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
These boards have not been converted to CONFIG_DM_USB by the deadline
and is also missing conversion to CONFIG_DM. Remove them. As this is
also the last SPEAR3XX platform, remove that symbol as well.
Cc: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
These boards have not been converted to CONFIG_DM_USB by the deadline
and is also missing conversion to CONFIG_DM. Remove them.
Cc: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
These boards have not been converted to CONFIG_DM_USB by the deadline
and is also missing conversion to CONFIG_DM. Remove them.
Cc: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
These boards have not been converted to CONFIG_DM_USB by the deadline
and is also missing conversion to CONFIG_DM. Remove it
Cc: Gerald Kerma <dreagle@doukki.net>
Cc: Tony Dinh <mibodhi@gmail.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Signed-off-by: Tom Rini <trini@konsulko.com>
These boards have not been converted to CONFIG_DM_USB by the deadline
and is also missing conversion to CONFIG_DM. Remove it
Cc: Ajay Bhargav <contact@8051projects.net>
Signed-off-by: Tom Rini <trini@konsulko.com>
These boards have not been converted to CONFIG_DM_USB by the deadline
and is also missing conversion to CONFIG_DM. Remove it.
This is also the last PL010_SERIAL using board, so remove those
references.
Cc: Sergey Kostanbaev <sergey.kostanbaev@fairwaves.ru>
Signed-off-by: Tom Rini <trini@konsulko.com>
These boards have not been converted to CONFIG_DM_USB by the deadline
and is also missing conversion to CONFIG_DM. Remove them.
Cc: Andreas Bießmann <andreas@biessmann.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
This board has not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM. Remove it. As this is the last
ARCH_T4160 platform, remove that support as well.
Signed-off-by: Tom Rini <trini@konsulko.com>
These boards have not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM. Remove them.
Signed-off-by: Tom Rini <trini@konsulko.com>
This board has not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM. Remove it.
Signed-off-by: Tom Rini <trini@konsulko.com>
This board has not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM. Remove it. As this is the last
ARCH_MPC8315 platform, remove that support as well.
Signed-off-by: Tom Rini <trini@konsulko.com>
This board has not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM. Remove it. This is also the last
of the ARCH_MPC8641/MPC8610 platforms, so remove that support as well.
Cc: Paul Gortmaker <paul.gortmaker@windriver.com>
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
These boards have not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM. Remove them. As this includes
the last ARCH_MPC8572 platform, remove that as well.
Cc: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Peter Tyser <ptyser@xes-inc.com>
This board has not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM. Remove it. As this is the last
ARCH_MPC8568 platform, remove that support as well.
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
These boards have not been converted to CONFIG_DM_PCI by the deadline
and is also missing conversion to CONFIG_DM. Remove them. As this is
the only ARCH_T1023 platform left, remove that support as well.
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
These boards have not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM. Remove them. As this is the only
ARCH_MPC8555 platform left, remove that support as well.
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
This board has not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM. Remove it. As this is the only
MPC8541 target left, remove that architecture support as well.
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
This board has not been converted to CONFIG_DM_PCI by the deadline and is
also missing conversion to CONFIG_DM. Remove it.
Signed-off-by: Tom Rini <trini@konsulko.com>
These boards have not been converted to CONFIG_DM_PCI by the deadline and are
also missing conversion to CONFIG_DM. Remove them.
Cc: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
These boards have not been converted to CONFIG_DM_PCI by the deadline
and is also missing conversion to CONFIG_DM. Remove them.
Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
This board has not been converted to CONFIG_DM_PCI by the deadline.
Remove it.
Cc: Heiko Schocher <hs@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Heiko Schocher <hs@denx.de>
This board has not been converted to CONFIG_DM_PCI by the deadline.
Remove it.
Cc: Ilya Yanok <yanok@emcraft.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
These boards have not been converted to CONFIG_DM_PCI, CONFIG_DM_USB or
in some cases CONFIG_DM itself by the deadline. Remove them.
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Cc: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
This board has not been converted to CONFIG_DM_MMC by the deadline.
Remove it.
Cc: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
These board has not been converted to CONFIG_DM_PCI by the deadline.
Remove them. As this is the last of the mcf547x_8x family of boards,
remove that support as well.
Cc: TsiChung Liew <Tsi-Chung.Liew@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
These board has not been converted to CONFIG_DM_PCI by the deadline.
Remove them. As this is all of the CONFIG_M548x platforms as well,
remove that code.
Cc: TsiChung Liew <Tsi-Chung.Liew@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
With x86 we can execute an option ROM either natively or using the
x86 emulator (if enabled with CONFIG_BIOSEMU). Both of these share
the _X86EMU_env variable, with the native code using it to hold
register state during interrupt processing.
At present, in 32-bit U-Boot, the variable is declared twice, once
in common code and once in code only compiled with CONFIG_BIOSEMU.
With GCC 11 this causes a 'multiple definitions' error on boards
with CONFIG_BIOSEMU.
Drop the emulator definition when CONFIG_BIOSEMU is used.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
When we do not have bootstage enabled, rather than include an empty
dummy function, we just don't reference it. This saves us space in some
tight builds. This also shows a few cases where show_boot_progress was
incorrectly guarded before.
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
-----BEGIN PGP SIGNATURE-----
iQFQBAABCgA6FiEEqxhEmNJ6d7ZdeFLIHrMeAg6sL8gFAmDkSkAcHGV1Z2VuLmhy
aXN0ZXZAbWljcm9jaGlwLmNvbQAKCRAesx4CDqwvyD24B/9t87hFqWovJvVAcoUT
JoTqFblplE4Sckssy0cQyR7sRpzuZEaakUeAxaLFecBN6Tn30YJEG3hNpEDCLEbA
hn/oiZ4hQ3JA9Yu2SHepQi0fLqdAjkQtMXy57o3Mk20GBLtPtpdItUHxg3iyeMSj
Ny1mm/KjL6ltmNeGfYfeqRf435Rm718DB94wCZTgS9woYe3Z5YRDNBPyL7u27hpY
2WiyvvU9EA12mjGYdEt5sCqnTQZFtHHlEWNHz4a3db6HkcPV7pfr+SpTNJjcFhIg
O7VN7yUTwnV0UGu5IXTWcZqFIqJkLPbPX5cvkSBnnaGge4e0K3Cw36Nv/EqCY8LX
gWfu
=Ru8k
-----END PGP SIGNATURE-----
Merge tag 'u-boot-atmel-fixes-2021.10-a' of https://source.denx.de/u-boot/custodians/u-boot-atmel
First set of u-boot-atmel fixes for 2021.10 cycle:
This small fixes set is dedicated to fixing the onewire subsystem for
the at91 boards which was broken since 2020.04.
Previous device tree for OpenPiton emits a warning during compilation.
This commit fixes the previous warning adds dts to the OpenPiton RISC-V
board and added the device tree to MAINTAINER file.
Signed-off-by: Tianrui Wei <tianrui-wei@outlook.com>
Reported-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
- mpc8379erdb DM_USB, DM_PCI and DM_ETH support.
- Drop PCI support from the integrator family of boards
- Add synquacer support
- Assorted lpc32xx updates and improvements
- snapdragon (and related) fixes, Broadcom iproc update
It looks like SD card detection is broken at the moment for DB410c.
The eMMC is detected correctly, but the SD card is not.
This is probably similar to the issue fixed in commit 8505147403
("mmc: msm_sdhci: Use mmc_of_parse for setting host_caps") for eMMC,
except that the SD card does not have a property like "non-removable"
that skips the card detection.
The SDHCI on DB410c cannot detect itself if a SD card is inserted,
so add the necessary cd-gpios to make SD card detection work again.
While at it, fix the #gpio-cells for the soc_gpios to avoid DTC
warnings - the soc_gpios are actually already used with two cells
for the gpio-leds so this was just wrong all the time.
Cc: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
The GICC register used by u-boot is 0x0a20c000, which is actually a GICC
for WCNSS, the WLAN processor. U-boot runs on the Application Processor,
therefore it should use APCS GICC instead. Hence, correct it with APCS GICC
register address.
Signed-off-by: Sheep Sun <sunxiaoyang2003@gmail.com>
Add basic support for running U-Boot on the Embedded Artists LPC3250
Developer's Kit v2 board by launching U-Boot from the board's s1l loader
(which comes pre-installed on the board).
Signed-off-by: Trevor Woerner <twoerner@gmail.com>
Import the dtsi, dts, and clock binding files for the lpc32xx ea3250 board
directly and unmodified from the latest Linux kernel.
Signed-off-by: Trevor Woerner <twoerner@gmail.com>
There's nothing special or unique to the lpc32xx that requires its own config
parameter for specifying the console uart index. Therefore instead of using
the lpc32xx-specific CONFIG_SYS_LPC32XX_UART include parameter, use the
already-available CONFIG_CONS_INDEX from Kconfig.
Signed-off-by: Trevor Woerner <twoerner@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add the DeveloperBox 96boards EE support. This board is also
known as Socionext SynQuacer E-Series. It contians one "SC2A11"
SoC, which has 24-cores of arm Cortex-A53, and 4 DDR3 slots,
3 PCIe slots (1 4x port and 2 1x ports which are expanded via
PCIe bridge chip), 2 USB 3.0 ports and 2 USB 2.0 ports, 2 SATA
ports and 1 GbE, 64MB NOR flash and 8GB eMMC on standard
MicroATX Form Factor.
For more information, see this page;
https://www.96boards.org/product/developerbox/
Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
Add device trees for 96boards EE DeveloperBox and basement SynQuacer
SoC dtsi. These files are imported from EDK2
commit 83d38b0b4c0f240d4488c600bbe87cea391f3922
as-is (except for the changes #include path and some macros).
And add U-Boot specific changes in synquacer-sc2a11-developerbox-u-boot.dtsi
Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
Since some SoCs and boards do not hae extra asm/arch/gpio.h,
introduce CONFIG_GPIO_EXTRA_HEADER instead of adding
!define(CONFIG_ARCH_XXXX) in asm/gpio.h.
Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
Add support for 1.3GHz, 1.35GHz and 1.4GHz parts. This is based on
equivalent code in Broadcom's LDK 5.0.6.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
This patch adds a limited pulse-width modulator to sandbox's Chromium OS
Embedded Controller emulation. The emulated PWM device supports multiple
channels but can only set a duty cycle for each, as the actual EC
doesn't expose any functionality or information other than that. Though
the EC supports specifying the PWM channel by its type (e.g. display
backlight, keyboard backlight), this is not implemented in the emulation
as nothing in U-Boot uses this type specification.
This emulated PWM device is then used to test the Chromium OS PWM driver
in sandbox. Adding the required device node to the sandbox test
device-tree unfortunately makes it the first PWM device, so this also
touches some other tests to make sure they still use the sandbox PWM.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
state_uninit() and dm_uninit() are mutually exclusive:
state_uninit() prints via drivers. So it cannot be executed after
dm_uninit().
dm_uninit() requires memory. So it cannot be executed after state_uninit()
which releases all memory.
Just skip dm_uninit() when resetting the sandbox. We will wake up in a new
process and allocate new memory. So this cleanup is not required. We don't
do it in sandbox_exit() either.
This avoids a segmentation error when efi_reset_system_boottime() is
invoked by a UEFI application.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Addresses in state->ram_buf must be in the low 4 GiB of the address space.
Otherwise we cannot correctly fill SMBIOS tables. This shows up in warnings
like:
WARNING: SMBIOS table_address overflow 7f752735e020
Ensure that state->ram_buf is initialized by the first invocation of
os_malloc().
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
At present if sandbox crashes it prints a message and tries to exit. But
with the recently introduced signal handler, it often seems to get stuck
in a loop until the stack overflows:
Segmentation violation
Segmentation violation
Segmentation violation
Segmentation violation
Segmentation violation
Segmentation violation
Segmentation violation
...
The signal handler is only useful for a few tests, as I understand it.
Make it optional.
Signed-off-by: Simon Glass <sjg@chromium.org>
The difference between unmatched rev3 and rev1 is DDR timing, the rev3
uses 1866 MT/s for 16GiB, and rev1 uses 2133 MT/s for 8GiB.
Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
There are different DDR parameter settings for different board
revisions. Add a new interface to get the PCB revision to determine
which DT should be selected at runtime.
Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Enable SPL_I2C_SUPPORT for fu740, and add 'u-boot,dm-spl' property in
i2c node.
Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
The GPIO polarity for onewire must be GPIO_ACTIVE_HIGH.
On previous versions this used to work as it looks like the right flag values
are being passed since :
https://lists.denx.de/pipermail/u-boot/2020-April/407195.html
And that series broke the old functionality for onewire nodes.
Some boards had the correct value for the polarity, but it wasn't clear
so I replaced it with the right macro for the flag, instead of an empty value.
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
This patch adds openpiton-riscv64 SOC support. In particular, this
board supports a standard bootflow through zsbl->u-boot SPL->
opensbi->u-boot proper->Linux. There are separate defconfigs for
building u-boot SPL and u-boot proper
Signed-off-by: Tianrui Wei <tianrui-wei@outlook.com>
Signed-off-by: Jonathan Balkind <jbalkind@ucsb.edu>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Now that u-boot gained DSA support, and it is already enabled for the
kontron_sl28 board, add the last missing piece and enable the
corresponding devices it in the device tree.
Signed-off-by: Michael Walle <michael@walle.cc>
The enetc-2 port is used as DSA master (connected back-to-back to
mscc_felix_port4). Since the convention is to not enable ports in the
common SoC dtsi unless they are used on the board, then enable enetc-2
only when mscc_felix_port4 itself is enabled.
All existing device trees appear to adhere to this rule, so disable
enetc-2 in the SoC dtsi.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
To comply with the device tree bindings expectations for an Ethernet
controller, as well as to simplify the driver code, declare fixed-link
nodes for the internal ENETC ports (attached to the mscc_felix switch).
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
There are no PCB trace delays on this board, so the PHY needs to enable
its internal ones in order to have a proper electrical connection to the
enetc MAC.
Fixes: b32e9a7578 ("arm: dts: ls1028a updates for network interfaces")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Due to an upstream change, the ls1028a.dtsi bindings for the mscc_felix
switch got accepted with all ports disabled by default and with no link
to the DSA master - this needs to be done on a per board basis.
Note that enetc-2 is not currently disabled in the ls1028a.dtsi, but
presumably at some point it might become. Explicitly enable it in the
QDS device trees anyway, to proactively avoid issues when that happens.
Fixes: a7fdac7e2a ("arm: dts: ls1028a: define QDS networking protocol combinations")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
clk:
- Add driver for Xilinx Clocking Wizard IP
fdt:
- Also record architecture in /fit-images
net:
- Fix plat/priv data handling in axi emac
- Add support for 10G/25G speeds
pca953x:
- Add missing dependency on i2c
serial:
- Fix dependencies for DEBUG uart for pl010/pl011
- Add setconfig option for cadence serial driver
watchdog:
- Add cadence wdt expire now function
zynq:
- Update DT bindings to reflect the latest state and descriptions
zynqmp:
- Update DT bindings to reflect the latest state and descriptions
- SPL: Add support for ECC DRAM initialization
- Fix R5 core 1 handling logic
- Enable firmware driver for mini configurations
- Enable secure boot, regulators, wdt
- Add support xck devices and 67dr
- Add psu init for sm/smk-k26 SOMs
- Add handling for MMC seq number via mmc_get_env_dev()
- Handle reserved memory locations
- Add support for u-boot.itb generation for secure OS
- Handle BL32 handoffs for secure OS
- Add support for 64bit addresses for u-boot.its generation
- Change eeprom handling via nvmem aliases
-----BEGIN PGP SIGNATURE-----
iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCYN105QAKCRDKSWXLKUoM
IZiFAJ9CIiEpHiBbnAhA0VOMGoaXHGULywCdED/5dNgVtc1C7y4avzETbEyWzD4=
=CdMa
-----END PGP SIGNATURE-----
Merge tag 'xilinx-for-v2021.10' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next
Xilinx changes for v2021.10
clk:
- Add driver for Xilinx Clocking Wizard IP
fdt:
- Also record architecture in /fit-images
net:
- Fix plat/priv data handling in axi emac
- Add support for 10G/25G speeds
pca953x:
- Add missing dependency on i2c
serial:
- Fix dependencies for DEBUG uart for pl010/pl011
- Add setconfig option for cadence serial driver
watchdog:
- Add cadence wdt expire now function
zynq:
- Update DT bindings to reflect the latest state and descriptions
zynqmp:
- Update DT bindings to reflect the latest state and descriptions
- SPL: Add support for ECC DRAM initialization
- Fix R5 core 1 handling logic
- Enable firmware driver for mini configurations
- Enable secure boot, regulators, wdt
- Add support xck devices and 67dr
- Add psu init for sm/smk-k26 SOMs
- Add handling for MMC seq number via mmc_get_env_dev()
- Handle reserved memory locations
- Add support for u-boot.itb generation for secure OS
- Handle BL32 handoffs for secure OS
- Add support for 64bit addresses for u-boot.its generation
- Change eeprom handling via nvmem aliases
