Commit graph

29 commits

Author SHA1 Message Date
Manikanta Guntupalli
28dc356e66 xilinx: dts: Fix open drain warning on Zynq, ZynqMP and Versal
Fix for below open drain warning on Zynq, ZynqMP and Versal reported by
Linux.
"enforced open drain please flag it properly in DT/ACPI DSDT/board
file."

Signed-off-by: Manikanta Guntupalli <manikanta.guntupalli@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/056b6f60f89fa2addb762669b80640cd5b31b001.1688992653.git.michal.simek@amd.com
2023-07-21 09:00:38 +02:00
Michal Simek
174d728471 arm64: zynqmp: Switch to amd.com emails
Update my and DPs email address to match current setup.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/aba5b19b9c5a95608829e86ad5cc4671c940f1bb.1688992543.git.michal.simek@amd.com
2023-07-21 09:00:38 +02:00
Michal Simek
2b1db7b18c arm64: zynqmp: Wire GEM reset gpio
With ethernet-phy-id driver ETH phy reset can be properly handle that's why
describe it in DT.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/5bfd92827033d19617113f4117f37dcf79699a0f.1662721547.git.michal.simek@amd.com
2022-09-21 09:55:19 +02:00
Michal Simek
13622c7a9d arm64: zynqmp: Describe TI phy as ethernet-phy-id
TI DP83867 is using strapping based on MIO pins. Tristate setup can influce
PHY address. That's why switch description with ethernet-phy-id compatible
string which enable calling reset. PHY itself setups phy address after
power up or reset. Reset description will be added in separate commit.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/52bf9ac0453d4e4896d8edd2618e684bb1ff6012.1662721547.git.michal.simek@amd.com
2022-09-21 09:55:19 +02:00
Ashok Reddy Soma
b8745e7eb4 arm64: zynqmp: Fix usb node drive strength and slew rate
As per design, all input/rx pins should have fast slew rate and 12mA
drive strength. Rest all pins should be slow slew rate and 4mA drive
strength. Fix usb nodes as per this and remove setting of slow slew rate
for all the usb gorup pins.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/b245c165f05845c1f3ab41a92c82b7ec1538cee4.1655288171.git.michal.simek@amd.com
2022-06-24 14:17:18 +02:00
Amit Kumar Mahapatra
6e38e2ea79 arm64: zynqmp: Set qspi tx-buswidth to 4
In all the ZynqMP boards dts files tx-buswidth is by default set to 1. Due
to this the framework only issues 1-1-1 write commands to the GQSPI driver.
But the GQSPI controller is capable of handling 1-4-4 write commands, so
updated the tx-buswidth to 4 in ZynqMP boards dts files. This would enable
the spi-nor framework to issue 1-4-4 write commands instead of 1-1-1. This
will increase the tx data transfer rate, as now the tx data will be
transferred on four lines instead on single line.

Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/ad61199f55e5e00f29de6206d9d1872a52a7657e.1652193179.git.michal.simek@amd.com
2022-05-18 13:17:18 +02:00
Manish Narani
15ca9ebb07 arm64: zynqmp: Move USB3 PHY properties from DWC3 node to USB node
Move the PHY properties from DWC3 node to USB node in ZynqMP DTs as here
the USB3 PHY used is PSGTR, which is connected to Xilinx USB core. This
PHY initialization should be handled from Xilinx USB core as the
prerequisite register configurations are done here only.

Signed-off-by: Manish Narani <manish.narani@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-07-26 09:26:41 +02:00
Michal Simek
52caf2c12b arm64: zynqmp: Remove gpio from aliases list
It is not recommended to have aliases for gpio. In past it was used in
Linux for assigning numbers via sysfs which is deprecated and libgpiod
should be used instead.
In U-Boot this number is used for seq number but gpio offset are not
counted from this number. That's why having these aliases only for seq
number is not needed. As is done in Linux it is the best to use full gpio
name instead of sequence number which depends on sequence in binding.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:36 +02:00
Michal Simek
6a2ce6ec24 arm64: zynqmp: Sync psgtr location on zcu104/zcu111/zc1751-dc1
psgtr node should be below pinctrl for easier comparion among dts files.
That's why move that nodes to different location.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
43086886ad arm64: zynqmp: Remove si5328 and si5382 nodes
There are no drivers for these devices that's why remove that nodes
completely. This change is done based on Linux kernel.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/20210308115437.2232847-1-quanyang.wang@windriver.com
2021-06-23 09:48:35 +02:00
Michal Simek
531abcb71e xilinx: Convert xlnx,eeprom property to nvmem alias
Convert all boards to use nvmem alias instead of xlnx,eeprom. The change is
done based on discussion in the link below.

Link: https://lore.kernel.org/r/CAL_JsqLMDqpkyg-Q7mUfw-XH67-v068Q6e9wTq2UOoN=0-_coQ@mail.gmail.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
447fb8db02 arm64: zynqmp: Update Copyright years to 2021
Trivial change for all files I have touched recently.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-06-23 09:48:35 +02:00
Michal Simek
3195840c94 arm64: zynqmp: Add psgtr DT descriptions
Mainline kernel has psgtr driver that's why it is good to add description
to DT files. Some boards are just missing description for USB3 and sata.
zc1751-dc1 and p-a2197 are also missing clock descriptions for input
clocks.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-05-19 09:44:50 +02:00
Michal Simek
bd00849ae9 arm64: zynqmp: Add pinctrl description
ZynqMP pinctrl Linux driver has been merged to 5.13-rc1 kernel. Based on it
DT files can be extended by pinctrl configurations.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-05-19 09:44:50 +02:00
Michal Simek
ce90654d1c xilinx: Sync DTs with Linux kernel
There are several changes which happen in mainline kernel which should get
also to U-Boot. Here is the list of patches from the kernel:

- ARM: zynq: Fix leds subnode name for zc702/zybo-z7
- arm64: dts: zynqmp: Fix leds subnode name for zcu100/ultra96 v1
- arm64: dts: zynqmp: Fix u48 si5382 chip on zcu111
- arm64: dts: zynqmp: Wire up the DisplayPort subsystem
- arm64: dts: zynqmp: Add DisplayPort subsystem
- arm64: dts: zynqmp: Add DPDMA node
- arm64: dts: zynqmp: Enable phy driver for Sata on zcu102/zcu104/zcu106
- arm64: dts: zynqmp: Enable si5341 driver for zcu102/106/111
- arm64: dts: zynqmp: Add DT description for si5328 for zcu102/zcu106
- arm64: dts: zynqmp-zcu100-revC: correct interrupt flags
- arm64: dts: xilinx: align GPIO hog names with dtschema
- arm64: zynqmp: Add Xilinx AES node
- dt: bindings: dma: xilinx: dpdma: DT bindings for Xilinx DPDMA

but also some other changes have been done.
- Using only one compatible string for adxl345 on zturn
- Remove Xilinx internal DP bindings
- Remove USB3.0 serdes configurations
- Remove SATA serdes configuration for zc1232
- Resort nvmem_firmware
- Update nand compatible string
- Aling power-domains property for sd0/1

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-03-30 12:03:24 +02:00
Michal Simek
01a6da1661 xilinx: Fix xlnx,mio_bank property
s/xlnx,mio_bank/xlnx,mio-bank/g

DT binding is describing mio-bank not mio_bank that's why fix all DTSes and
also driver itself.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
2020-08-20 09:49:20 +02:00
Michal Simek
14c0fbbc94 arm64: zynqmp: Fix irps5401 device nodes
- Do not use irps54012 as device node which is not correct.
- Fix addresses of irps5401/u180 on zcu104 revisions.
- Remove clock-cells property. It is PMIC without any clock output.
- Define irps5401 nodes in zynqmp-e-a2197

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-27 14:21:18 +02:00
Michal Simek
5df63a60aa arm64: zynqmp: Fix addresses in partition definitions
Node name should be <name>@<address> which is not how partitions are
described.

Issue was found by running dtbs_check as:
flash@0: 'partition@qspi-device-tree', 'partition@qspi-fsbl-uboot',
'partition@qspi-linux', 'partition@qspi-rootfs'
do not match any of the regexes: ...

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-06 12:51:31 +02:00
Michal Simek
d31f1c9236 arm64: zynqmp: Update Copyright years to 2020
Trivial change.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-06 12:51:31 +02:00
Harini Katakam
631d9a9981 arm64: zynqmp: dt: Add missing DP83867 quirk
The DP83867 strap control workaround is already present in Linux kernel
mainline binding. All these Xilinx boards require this quirk.

Signed-off-by: Harini Katakam <harini.katakam@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-24 13:37:02 +02:00
Michal Simek
0ae57b34f0 arm64: zynqmp: Enable fpd_dma for zcu104 platforms
Enable fpd_dma for these boards.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-24 13:37:02 +02:00
Michal Simek
3d82d7167f arm64: zynqmp: Enable iio-hwmon for ina226 on zcu104
ina226 hwmon driver is deprecated and it is recommended to use new iio
based driver. The patch is enabling iio-hwmon driver to export
functionality from IIO to hwmon interface to be able to use lm-sensors
package.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-24 13:37:02 +02:00
Michal Simek
2975a42b42 arm64: zynqmp: Use ethernet-phy as node name for ethernet phys
Ethernet phys based on devicetree specification should be using
ethernet-phy@ node name instead of pure phy@.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-10-24 13:37:01 +02:00
Neil Armstrong
ffd4c7c2ec dts: switch spi-flash to jedec, spi-nor compatible
There is no reason not to use the Linux "jedec,spi-nor" binding in U-Boot
dts files. This compatible has been added in sf_probe, let use it.

This patch switches to jedec,spi-nor when spi-flash is used in the DTS
and DTSI files, and removed spi-flash when jedec,spi-nor is already
present.

The x86 dts are switched in a separate commit since it depends on a change
in fdtdec.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Evgeniy Paltsev <paltsev@synopsys.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Patrick Delaunay <Patrick.delaunay@st.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-04-12 10:54:27 +05:30
Michal Simek
8bdad43333 arm64: zynqmp: Switch all platforms to DM_I2C
CONFIG_PCA953X is not needed because of PCA953X is integrated in gpio
subsystem already. That's why also remove CMD_PCA953X which is only for
this driver.

zcu102/zcu104-revC/zcu106/zcu111 contain links to eeprom which stores MAC address.

DM_I2C is not enabled for the whole SoC because it increase size for
mini configurations and there is no I2C symbol present to setup
dependencies.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-02-14 14:31:10 +01:00
Michal Simek
0ed45f0025 arm64: zynqmp: Wire spi-flash compatible string with flashes
Enable reading tx and rx buswidth from DT via spi-uclass.
To get these from uclass spi-flash compatible string has to be added
to flash node.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-11-29 10:30:02 +01:00
Michal Simek
ce236dce56 arm64: zynqmp: Fix address for tca6416_u97 chip on zcu104
I2c address is not 0x21 but 0x20. This patch is fixing both revA and
revC boards.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-31 13:50:39 +02:00
Michal Simek
3705dae164 arm64: zynqmp: Add ina226 to zcu104 revC
Add new ina226 chip present on i2c bus which wasn't on revA.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-31 13:50:39 +02:00
Michal Simek
f7c8e491e9 arm64: zynqmp: Add support for zcu104 customer board
Xilinx zcu104 is another customer board. It is sort of zcu102 clone with
some differences.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-04-09 12:14:52 +02:00