There are a lot of unrelated files in common, including all of the commands.
Moving them into their own directory makes them easier to find and is more
logical.
Some commands include non-command code, such as cmd_scsi.c. This should be
sorted out at some point so that the function can be enabled with or without
the associated command.
Unfortunately, with m68k I get this error:
m68k: + M5329AFEE
+arch/m68k/cpu/mcf532x/start.o: In function `_start':
+arch/m68k/cpu/mcf532x/start.S:159:(.text+0x452): relocation truncated to fit: R_68K_PC16 against symbol `board_init_f' defined in .text.board_init_f section in common/built-in.o
I hope someone can shed some light on what this means. I hope it isn't
depending on the position of code in the image.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
This commit 4bdcbe60a1 removes reset_cpu
which breaks SPL build when DEBUG macro defined.
"
arch/arm/lib/built-in.o: In function `do_reset':
~/uboot/arch/arm/lib/reset.c:45: undefined reference to `reset_cpu'
scripts/Makefile.spl:244: recipe for target 'spl/u-boot-spl' failed
"
Enable CONFIG_SPL_WATCHDOG_SUPPORT to fix this issue.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Acked-by: Eric Nelson <eric@nelint.com>
The management data input/output (MDIO) requires open-drain,
i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports
this feature. So to TO1.1, need to enable open drain by setting
bits GPR0[8:7] for TO1.1.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Check "Figure 19-5. BUS clock generation" of i.MX 6SoloX Applications
Processor Reference Manual and "Figure 18-5. BUS clock generation" of
i.MX 6UltraLite Applications Processor Reference Manual. If mmdc clk
sources from pll4_main_clk(pll_audio), the calculation is wrong.
Fix mmdc_ch0 clk calculation. Also add PLL_AUDIO/VIDEO support
for decode_pll.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Add more entries for structure mxc_ccm_reg.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Eric Nelson <eric@nelint.com>
Cc: Stefano Babic <sbabic@denx.de>
Add pinmux settings.
Add related macro definitions.
Nand pin conflicts with emmc, so if want to enable nand, need to do
hardware rework. After hardware rework, define CONFIG_NAND_MXS in
board header file.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
As the lowlevel_init function is empty we should better
remove this assembly file entirely and use a dummy C
function instead.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Support uncompressing zImage which is larger than 8M.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Peter Robinson <pbrobinson@gmail.com>
Cc: Volodymyr Riazantsev <volodymyr.riazantsev@globallogic.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Adrian Alonso <aalonso@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
To i.MX6UL 14x14 EVK, system memory is 512M; to i.MX6UL 9x9 EVK,
system memory is 256M. If setting mtest size to 256M, mtest will
crash uboot for i.MX6UL 9x9 evk. So change mtest size to 128M.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Until we have a proper video uclass we can use syscon to handle the GMA
device, and avoid the special device tree and PCI searching. Update the code
to work this way.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Each system controller can have a number to identify it. It can then be
accessed using syscon_get_by_driver_data(). Put this in a shared header
file and update the only current user.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
U-Boot does not support SMM yet, so we can drop this code. It is easy to
bring back when needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This is not used on link which is the only ivybridge board. Drop this code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This is not needed. On reset wake-on-disconnect is already set. It may a
problem during a soft reset or resume, but for now it does not seem
important. Also drop the command register update since PCI auto-config
does it for us.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This function is called all over the place. Convert it use the driver model
PCI API, and rationalise the calls.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This code relates to the PCH, so we should move it into the same file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
SDRAM init needs access to the Northbridge controller and the Intel
Management Engine device. Add the latter to the device tree and convert all
of this code to driver model.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
We will use a system controller to model the Intel Management Engine. Enable
this for link.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Convert this function to use the the driver model PCI API. We just need
to pass in the northbridge device.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Convert the top part of the DRAM init to use the driver model PCI API.
Further work will complete the transformation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Convert this function over to use the driver model PCI API. In this case
we want to avoid using the real PCI devices since they have not yet been
probed. Instead, write directly to their PCI configuration address.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Move the init code into the I2C driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This is used on most Intel platforms. We don't have a driver for it yet, but
add a stub to handle the init. For now this targets ivybridge so we may want
to add a device tree binding and generalise it when other platforms are
supported.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Adjust this code to use the driver model PCI API. This is all called through
lpc_init_extra().
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
There is nothing special about the ivybridge pci driver now, so just use
the generic one.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Drop the lpc_init_extra() function and just use the post-relocation LPC
probe() instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This graphics init code is best placed in the gma init code. Move the code
and drop the function.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Adjust the functions in this file to use the driver model PCI API.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Instead of manually initing the device, probe the SATA device and move the
init there.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The SATA device needs to set itself up so that it appears correctly on the
PCI bus. The easiest way to do this is to set it up to probe before
relocation. This can do the early setup.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a uclass ID for a disk controller. This can be used by AHCI/SATA or
other controller types. There are no operations and no interface so far,
but it is possible to probe a SATA device.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Adjust most of the remaining functions in this file to use the driver model
PCI API. The one remaining function is bridge_silicon_revision() which will
need a little more work.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Instead of calling the northbridge and PCH init from bd82x6x_init_extra()
when the PCI bus is probed, call it from the respective drivers. Also drop
the Northbridge init as it has no effect. The registers it touches appear to
be read-only.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
These devices currently need to be inited early in boot. Once we have the
init in the right places (with each device doing its own init and no
problems with ordering) we should be able to remove this. For now it is
needed to keep things working.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
When the final MRC cache record is the same as the one we want to write, we
skip writing since there is no point. This is normal behaviour.
Avoiding printing an error when this happens.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
There are no other implementations of this function, and boards that need it
can implement a CPU driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This code is now part of the northbridge driver, so move it into the same
place.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This uses a non-existent node at present. It should use the first CPU node.
The referenced property does not exist (the correct value is the default of
0), but this allows the follow-on init to complete.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Use the CPU driver's probe() method to perform the CPU init. This will happen
automatically when the first CPU is probed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The existing ivybridge code predates the normal multi-core CPU init, and
it is not used. Remove it and add CPU nodes to the device tree so that all
four CPUs are set up. Also enable the 'cpu' command.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
