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imx: nand: update GPMI NAND driver to support MX7
Update GPMI NAND driver and BCH head file to support i.MX7 Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
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parent
1fc4f80495
commit
bedaa842ae
2 changed files with 4 additions and 4 deletions
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@ -123,7 +123,7 @@ struct mxs_bch_regs {
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#define BCH_FLASHLAYOUT0_NBLOCKS_OFFSET 24
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#define BCH_FLASHLAYOUT0_META_SIZE_MASK (0xff << 16)
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#define BCH_FLASHLAYOUT0_META_SIZE_OFFSET 16
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#if defined(CONFIG_MX6)
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#if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
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#define BCH_FLASHLAYOUT0_ECC0_MASK (0x1f << 11)
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#define BCH_FLASHLAYOUT0_ECC0_OFFSET 11
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#else
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@ -154,7 +154,7 @@ struct mxs_bch_regs {
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#define BCH_FLASHLAYOUT1_PAGE_SIZE_MASK (0xffff << 16)
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#define BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET 16
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#if defined(CONFIG_MX6)
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#if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
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#define BCH_FLASHLAYOUT1_ECCN_MASK (0x1f << 11)
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#define BCH_FLASHLAYOUT1_ECCN_OFFSET 11
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#else
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@ -30,7 +30,7 @@
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#define MXS_NAND_DMA_DESCRIPTOR_COUNT 4
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#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512
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#if defined(CONFIG_MX6)
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#if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
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#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 2
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#else
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#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 0
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@ -152,7 +152,7 @@ static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size,
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int max_ecc_strength_supported;
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/* Refer to Chapter 17 for i.MX6DQ, Chapter 18 for i.MX6SX */
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if (is_cpu_type(MXC_CPU_MX6SX))
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if (is_cpu_type(MXC_CPU_MX6SX) || is_soc_type(MXC_SOC_MX7))
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max_ecc_strength_supported = 62;
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else
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max_ecc_strength_supported = 40;
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