Commit graph

372 commits

Author SHA1 Message Date
Marek Vasut
c76976d98f ddr: altera: Implement universal scc manager config function
Implement unified scc_mgr_set() function and convert all those
9 scc_mgr_set_*() ad-hoc functions to call this one function.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:12 +02:00
Marek Vasut
5ff825b853 ddr: altera: Reorder scc manager functions
This patch just puts functions which look similar next to each
other, so they can be sorted out. No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:12 +02:00
Marek Vasut
07aee5bd98 ddr: altera: Clean up scc manager function args
Clean up the unused args of the functions used to configure the
SCC manager.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:11 +02:00
Marek Vasut
2c0d2d9c40 ddr: altera: Clean up reg_file_set*()
Turn the insides of these functions into trivial clrsetbits_le32()
and fix the data type of their argument to reflect it's actual size.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:11 +02:00
Marek Vasut
2ca151f86c ddr: altera: Clean up initialize_hps_phy()
Add brief kerneldoc.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:11 +02:00
Marek Vasut
9c1ab2ca19 ddr: altera: Clean up initialize_reg_file()
Add brief kerneldoc.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:11 +02:00
Marek Vasut
bb06434bb2 ddr: altera: Clean up hc_initialize_rom_data()
Clean the function up, fix data types, add kerneldoc.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:11 +02:00
Marek Vasut
1273dd9ea3 ddr: altera: Massage addr into I/O accessors
Get rid of invocations of this sort:
  addr = (u32)&base->reg;
  writel(val, addr);

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:11 +02:00
Marek Vasut
6cb9f16781 ddr: altera: Stop using SDR_CTRLGRP_ADDRESS directly
Use the proper structure which describes these registers,
especially since this is already in place.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:11 +02:00
Marek Vasut
17fdc9167f ddr: altera: Wrap SOCFPGA_SDR_ADDRESS into SDR_PHYGRP.*ADDRESS
Just trim down the constant SOCFPGA_SDR_ADDRESS + SDR_PHYGRP.*ADDRESS
in the code.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:11 +02:00
Marek Vasut
c4815f7671 ddr: altera: Pluck out remaining sdr_get_addr() calls
Remove the remaining invocations of sdr_get_addr() and the function
itself. This makes the code a bit less cryptic.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:11 +02:00
Marek Vasut
1bc6f14a61 ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_mgr_.*->.*)
Instead of this indirection, just adjust the register pointer and
directly use the register base address.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:10 +02:00
Marek Vasut
6afb4fe2a0 ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_rw_load.*->.*)
Instead of this indirection, just adjust the register pointer and
directly use the register base address.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:10 +02:00
Marek Vasut
e79025a774 ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_scc_mgr->.*)
Instead of this indirection, just adjust the register pointer and
directly use the register base address.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:10 +02:00
Marek Vasut
a1c654a893 ddr: altera: Dissolve invocation of sdr_get_addr(&sdr_reg_file->.*)
Instead of this indirection, just adjust the register pointer and
directly use the register base address.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:10 +02:00
Marek Vasut
a4bfa463e0 ddr: altera: Zap invocation of sdr_get_addr((u32 *)BASE_RW_MGR)"
Instead of this indirection, just adjust the register pointer and
directly use the register base address.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:10 +02:00
Marek Vasut
23f62b36da ddr: altera: Clean up ugly casts in sdram_calibration_full()
Use the correct formating string in those debug_cond() invocations
and zap those unnecessary ugly casts.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:10 +02:00
Marek Vasut
963bca63b6 ddr: altera: Minor indent fix in set_rank_and_odt_mask()
Fix the position of the } else { statement to make it correctly
indented.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:10 +02:00
Marek Vasut
7ac40d25cf ddr: altera: Fix debug message format in sequencer
The debug messages missed proper newlines and/or spaces in them.
Fix the formatting.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Tom Rini <trini@konsulko.com>
2015-08-08 14:14:06 +02:00
Marek Vasut
452a81e078 ddr: altera: Fix typo in mp_threshold1 programming
It is the configuration data that should go into the register,
not the register mask, just like the surrounding code does it.
Fix this typo.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Tom Rini <trini@konsulko.com>
2015-08-08 14:14:05 +02:00
Marek Vasut
42f7ebb82b ddr: altera: Move struct sdram_prot_rule prototype
Move the structure prototype from sdram.h header file into sdram.c
source file, since it is used only there and for local purpose only.
There is no point in having it global.

While at this move, fix the data types in the structure from uintNN_t
to uNN and fix the coding style a bit.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:05 +02:00
Marek Vasut
d04941cf33 arm: socfpga: Move sdram_config.h to board dir
This file is absolutelly positively board specific, so move it
into the correct place.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:05 +02:00
Dinh Nguyen
3da428595e driver/ddr/altera: Add the sdram calibration portion
This patch adds the DDR calibration portion of the Altera SDRAM driver.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-08-08 14:14:05 +02:00
Dinh Nguyen
9bbd2132e3 driver/ddr/altera: Add DDR driver for Altera's SDRAM controller
This patch enables the SDRAM controller that is used on Altera's SoCFPGA
family. This patch configures the SDRAM controller based on a configuration
file that is generated from the Quartus tool, sdram_config.h.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-08-08 14:14:05 +02:00
York Sun
56848428a8 drivers/ddr/fsl: Adjust bstopre value
By default the bstopre value has been set to 0x100, used to be 1/4
value of refint. Modern DDR has increased the refresh time. Adjust
to 1/4 of refresh interval dynamically. Individual board can still
override this value in board ddr file, or to use auto-precharge.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-08-03 12:06:38 -07:00
Stefan Roese
ad6ac7aa00 arm: mvebu: a38x: Use correct PEX register access macros
Remove the incorrect PEX macros from the DDR header. And insert the
correct ones in ctrl_pex.h instead.

Signed-off-by: Stefan Roese <sr@denx.de>
2015-07-23 10:39:25 +02:00
Stefan Roese
f1df936445 arm: mvebu: Add Armada 38x DDR3 training code from Marvell bin_hdr
This patch adds the DDR3 setup and training code taken from the Marvell
U-Boot repository. This code used to be included as a binary (bin_hdr)
into the Armada A38x boot image. Not linked with the main U-Boot. With this
code addition and the serdes/PHY setup code, the Armada A38x support
in mainline U-Boot is finally self-contained. So the complete image
for booting can be built from mainline U-Boot. Without any additional
external inclusion.

Note:
This code has undergone many hours (days!) of coding-style cleanup and
refactoring. It still is not checkpatch clean though, I'm afraid. As the
factoring of the code has so many levels of indentation that many lines
are longer than 80 chars.

Signed-off-by: Stefan Roese <sr@denx.de>
2015-07-23 10:38:44 +02:00
Stefan Roese
ff9112df8b arm: mvebu: drivers/ddr: Move Armada XP DDR init code into new directory
With the upcoming addition of the Armada 38x DDR support, which is not
compatible to the Armada XP DDR init code, we need to introduce a new
directory infrastructure. To support multiple Marvell DDR controller.

This will be the new structure:

     drivers/ddr/marvell/axp
     Supporting Armada XP (AXP) devices (and perhaps Armada 370)

     drivers/ddr/marvell/a38x
     Supporting Armada 38x devices (and perhaps Armada 39x)

Signed-off-by: Stefan Roese <sr@denx.de>
2015-07-23 10:38:30 +02:00
York Sun
b92557cd3f driver/ddr/fsl: Add a hook to update SPD address
In case SPD address changes between board revisions, updating SPD
address can be called from board file.

Signed-off-by: York Sun <yorksun at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
2015-07-20 11:44:35 -07:00
Stefan Roese
144d509378 arm: mvebu: db-mv784mp-gp: Fix ECC I2C address
The macro to select the I2C address for ECC bus-width detection
was defined incorrectly for the Marvell DB-MV784MP-GP board. This
patch changes the macro to the correct value to fix this issue.

Signed-off-by: Stefan Roese <sr@denx.de>
2015-05-05 14:32:05 +02:00
York Sun
9f9f009373 driver/ddr/fsl: Add workaround for DDR erratum A008511
This erratum only applies to general purpose DDR controllers in LS2.
It shouldn't be applied to DP-DDR controller. Check DDRC versoin number
before applying workaround.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23 08:55:54 -07:00
York Sun
4516ff8160 driver/ddr/fsl: Add built-in memory test for DDR4 driver
Add built-in memory test to catch errors after DDR is initialized, before
any other transactions. To enable this test, define CONFIG_FSL_DDR_BIST.
An environmental variable "ddr_bist" is checked before starting test.
It takes a while (several seconds) depending on system memory size.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23 08:55:53 -07:00
York Sun
6b95be2280 driver/ddr/fsl: Fix driver to support empty first slot
CS0 was not allowed to be empty by u-boot driver in the past to simplify
the driver. This may be inconvenient for some debugging. This patch lifts
the restrictions. Controller interleaving still requires CS0 populated.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23 08:55:53 -07:00
York Sun
66869f9554 drivers/ddr/fsl: Update DDR driver for DDR4
Add/update registers for DDR4, including DQ mappings. Allow raw timing
method used for all controllers. Update mode_9 register to 0x500 for
improved stability. Check DDR controller version number individually
in case a SoC has multiple DDR controllers of different versions.
Increase read-write turnaround for DDR4 high speeds.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-04-23 08:55:53 -07:00
Curt Brune
d7c865bdf2 MPC8541/MPC8555: Enable SS_EN in DDR_SDRAM_CLK_CNLT register
According to the MPC8555/MPC8541 reference manual the SS_EN (source
synchronous enable) bit in the DDR_SDRAM_CLK_CNLT register must be set
during initialization.

>From section 9.4.1.8 of that manual:

   Source synchronous enable. This bit field must be set during
   initialization. See Section 9.6.1, "DDR SDRAM Initialization
   Sequence," details.

   0 - Reserved
   1 - The address and command are sent to the DDR SDRAMs source
       synchronously.

In addition, Freescale application note AN2805 is also very clear that
this bit must be set.

This patch reverts a change introduced by commit
457caecdbc.

Testing Done:

Compiled targets CONFIG_TARGET_MPC8555CDS and CONFIG_TARGET_MPC8541CDS
and inspected the generated assembly code to verify the SS_EN bit was being
set.  There is one extra instruction emitted:

  fff9b774: 65 29 80 00  oris    r9,r9,32768

Compiled the CONFIG_TARGET_MPC8548CDS target and verified that no
additional instructions were emitted related to this patch.

Booted an image on a MPC8541 based board successfully.

Signed-off-by: Curt Brune <curt@cumulusnetworks.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-04-20 10:15:28 -07:00
York Sun
e32d59a2fa driver/ddr/fsl: Add sync of refresh
Add sync of refresh for multiple DDR controllers. DDRC initialization
needs to complete first. Code is re-ordered to keep refresh close.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-02-24 13:09:42 -08:00
York Sun
dc1437afd7 driver/ddr/fsl: Fix a typo in timing_cfg_8 calculation
wwt_bg should match rrt_bg. It was a typo in driver.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-02-24 13:09:26 -08:00
York Sun
03e664d8f4 driver/ddr/fsl: Add support for multiple DDR clocks
Controller number is passed for function calls to support individual
DDR clock, depending on SoC implementation. It is backward compatible
with exising platforms. Multiple clocks have been verifyed on LS2085A
emulator.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-02-24 13:09:18 -08:00
York Sun
49fd1f3f26 driver/ddr/fsl: Add workround for erratumn A008514
Erratum A008514 workround requires writing register eddrtqcr1 with
value 0x63b20002.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-02-24 13:09:10 -08:00
York Sun
9955b4ab01 driver/ddr/fsl: Add workaround for A008336
Erratum A008336 requires setting EDDRTQCR1[2] in DDRC DCSR space
for 64-bit DDR controllers.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-02-24 13:09:06 -08:00
York Sun
1f3402e729 driver/ddr/fsl: Adjust CAS to preamble override for emulator
On ZeBu emulator, CAS to preamble overrides need to be set to
satisfy the timing. This only impact platforms with CONFIG_EMU.

These should be set before MEM_EN is set.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-02-24 13:09:02 -08:00
Stefan Roese
f8d25d7466 arm: mvebu: drivers/ddr: Add DDR3 driver with training code from Marvell bin_hdr
This patch adds the DDR3 setup and training code taken from the Marvell
U-Boot repository. This code used to be included as a binary (bin_hdr)
into the AXP boot image. Not linked with the main U-Boot. With this code
addition and the following serdes/PHY setup code, the Armada-XP support
in mainline U-Boot is finally self-contained. So the complete image
for booting can be built from mainline U-Boot. Without any additional
external inclusion. Hopefully other MVEBU SoC's will follow here.

Support for some SoC's has been removed in this version. This is:

MV_MSYS:
The code referred to by the MV_MSYS define is currently unused. And its
not really planned to support this in mainline. So lets remove it to
make the code clearer and increase the readability.

MV88F68XX (A38x):
The code referred to by the MV88F68XX define (A38x) is currently unused.
And its partial and not sufficient for this device in this stage.
So lets remove it to make the code clearer and increase the readability.

MV88F66XX (ALP):
The code referred to by the MV88F66XX define is currently unused. And its
not really planned to support this in mainline. So lets remove it to
make the code clearer and increase the readability.

MV88F78X60_Z1:
The code referred to by the MV88F78X60_Z1 define is currently unused. As the
Z1 revision of the AXP is not supported in mainline anymore.
So lets remove it to make the code clearer and increase the readability.

Remove support for Z1 & A0 AXP revisions (steppings). The current stepping
is B0 and this is the only one that is actively supported in this code
version.

Tested on AXP using a SPD DIMM setup on the Marvell DB-MV784MP-GP board and
on a custom fixed DDR configuration board (maxbcm).

Note:
This code has undergone many hours of coding-style cleanup and refactoring.
It still is not checkpatch clean though, I'm afraid. As the factoring of the
code has so many levels of indentation that many lines are longer than 80
chars. This might be some task to tackly later on.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
2015-02-06 17:25:03 +01:00
York Sun
dda3b610ee arm/ls1021a: Add workaround for DDR erratum A008378
Internal memory controller counters can reach a bad state after
training in DDR4 mode if accumulated ECC or DBI mode is eanbled.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-01-23 22:29:13 -06:00
York Sun
938bbb6013 driver/ddr/fsl: Fix MRC_CYC calculation for DDR3
For DDR controller version 4.7 or newer, MRC_CYC (mode register set
cycle time) is max(tMRD, tMOD). tMRD is 4nCK, or 8nCK (RDIMM). tMOD
is max(12nCK, 15ns) according to JEDEC spec.

DDR4 is not affected by this change.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-12-15 09:15:12 -08:00
Tang Yuantian
a7787b7850 fsl/sleep: updated the deep sleep framework for QorIQ platforms
With the introducing of generic board and ARM-based cores, current
deep sleep framework doesn't work anymore.
This patch will convert the current framework to adapt this change.
Basically it does:
1. Converts all the Freescale's DDR driver to support deep sleep.
2. Added basic framework support for ARM-based and PPC-based
cores separately.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:41:18 -08:00
York Sun
789b3447c0 driver/ddr/fsl: Add workaround for faulty SPD
Some UDIMMs have faulty SPD with wrong mapping for DQ[36-39].
Using raw card spec in case this error is detected.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:14 -08:00
York Sun
84baed2a2b driver/ddr/fsl: Adjust timing_cfg_0 to better support two DDR slots
Increase write-to-write and read-to-read turnaround time for two-slot DDR
configurations. Previously only quad-rank and two dual-rank configurations
have this additional turnaround time. A recent test on two single-rank
DIMMs shows the shorter additional turnaround time is also needed.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:11 -08:00
Masahiro Yamada
b41411954d linux/kernel.h: sync min, max, min3, max3 macros with Linux
U-Boot has never cared about the type when we get max/min of two
values, but Linux Kernel does.  This commit gets min, max, min3, max3
macros synced with the kernel introducing type checks.

Many of references of those macros must be fixed to suppress warnings.
We have two options:
 - Use min, max, min3, max3 only when the arguments have the same type
   (or add casts to the arguments)
 - Use min_t/max_t instead with the appropriate type for the first
   argument

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Pavel Machek <pavel@denx.de>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
[trini: Fixup arch/blackfin/lib/string.c]
Signed-off-by: Tom Rini <trini@ti.com>
2014-11-23 06:48:30 -05:00
York Sun
f80d6472b4 driver/ddr/fsl: Fix DDR4 driver
When accumulated ECC is enabled, the DQ_MAP for ECC[4:7] needs to be set
to 0, i.e. 0->0, 1->1, etc., required by controller logic, even these pins
are not actually connected.

Also fix a bug when reading from DDR register to use proper accessor for
correct endianess.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-09-25 08:36:20 -07:00
York Sun
bb5783224b driver/ddr/fsl: Fix tXP and tCKE
The driver was written using old DDR3 spec which only covers low speeds.
The value would be suboptimal for higher speeds. Fix both timing according
to latest DDR3 spec, remove tCKE as an config option.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-09-25 08:36:18 -07:00
York Sun
1d71efbb03 driver/ddr: Restruct driver to allow standalone memory space
U-boot has been initializing DDR for the main memory. The presumption
is the memory stays as a big continuous block, either linear or
interleaved. This change is to support putting some DDR controllers
to separated space without counting into main memory. The standalone
memory controller could use different number of DIMM slots.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-09-25 08:36:18 -07:00
York Sun
ef87cab664 driver/ddr/fsl: Add support of overriding chip select write leveling
JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This
is not an issue unless some DQ pins are not connected. If a platform uses
regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on
those floating pins for the second rank. The workaround is to use a known
good chip select for this purpose.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-09-08 10:30:34 -07:00
York Sun
5cb27c5d44 driver/ddr/freescale: Fix DDR3 driver for ARM
Reading DDR register should use ddr_in32() for proper endianess.
This patch fixes incorrect waiting time for ARM platforms.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-09-08 10:30:34 -07:00
York Sun
d28cb67142 driver/ddr/freescale: Add support of accumulate ECC
If less than 8 ECC pins are used for DDR data bus width smaller than 64
bits, the 8-bit ECC code will be transmitted/received across several beats,
and it will be used to check 64-bits of data once 8-bits of ECC are
accumulated.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-09-08 10:30:34 -07:00
York Sun
3d75ec95f5 driver/ddr: Fix DDR register timing_cfg_8
The field wrtord_bg should add 2 clocks if on the fly chop is enabled,
according to DDR controller manual for DDR4.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:55 -07:00
York Sun
8340e7ac86 driver/ddr: Fix DDR4 driver for ARM
Previously the driver was only tested on Power SoCs. Different barrier
instructions are needed for ARM SoCs.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-07-22 16:25:54 -07:00
York Sun
353527d527 driver/ddr/fsl: Fix printing unspecified module info for DDR4
The offset of module information is at 128, different from DDR3.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-06-05 13:45:07 -07:00
York Sun
9855b3beca powerpc/mpc85xx: Add workaround for DDR erratum A004508
When the DDR controller is initialized below a junction temperature of
0°C and then operated above a junction temperature of 65°C, the DDR
controller may cause receive data errors, resulting ECC errors and/or
corrupted data. This erratum applies to the following SoCs and their
variants: MPC8536, MPC8569, MPC8572, P1010, P1020, P1021, P1022, P1023,
P2020.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-06-05 13:45:07 -07:00
Simon Glass
e1bf824dfd Add cli_ prefix to readline functions
This makes it clear where the code resides.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-05-29 17:45:31 -04:00
Simon Glass
18d66533ac move CLI prototypes to cli.h and add comments
Move the CLI prototypes from common.h to cli.h as part of an effort to
reduce the size of common.h.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-05-29 17:45:31 -04:00
Tang Yuantian
aade20046b mpc85xx/t104x: Add deep sleep framework support
When T104x soc wakes up from deep sleep, control is passed to the
primary core that starts executing uboot. After re-initialized some
IP blocks, like DDRC, kernel will take responsibility to continue
to restore environment it leaves before.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:49 -07:00
York Sun
349689b802 drivers/ddr: Fix possible out of bounds error
This is a theoretical possible out of bounds error in DDR driver. Adding
check before using array index. Also change some runtime conditions to
pre-compiling conditions.

Signed-off-by: York Sun <yorksun@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:49 -07:00
York Sun
34e026f9b1 driver/ddr/fsl: Add DDR4 support to Freescale DDR driver
Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register
calculation and programming.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-04-22 17:58:48 -07:00
York Sun
6b1e1254f3 driver/ddr: Add 256 byte interleaving support
Freescale LayerScape SoCs support controller interleaving on 256 byte size.
This interleaving is mandoratory.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-02-21 11:06:13 -05:00
York Sun
6b9e309a8a Driver/ddr: Add support of different DDR base address
DDR base address has been the same from the view of core and DDR
controllers. This has changed for Freescale ARM-based SoCs. Controllers
setup DDR memory in a contiguous space and cores view it at separated
locations.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-02-21 11:06:13 -05:00
York Sun
4e5b1bd0df driver/ddr: Change Freescale ARM DDR driver to support both big and little endian
Initially it was believed the DDR controller on Freescale ARM would have
big endian. But some platform will have little endian.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-02-21 11:06:13 -05:00
York Sun
76356eb57c powerpc/mpc85xx: Revise workaround for DDR-A003
Existing workaround only handles one RDIMM on reference design. In case
of two RDIMMs being used, the workaround requires two separate writes to
DDR_SDRAM_MD_CNTL register.

This patch also restores two debug registers changed by the workaround.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Ben Collins <ben.c@servergy.com>
CC: James Yang <James.Yang@freescale.com>
2014-01-21 13:40:52 -08:00
York Sun
00ec3fd211 Driver/DDR: Update DDR driver to allow non-zero base address
The DRAM base has been zero for Power SoCs. It could be non-zero
for ARM SoCs. Use a macro instead of hard-coding to zero.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-11-25 11:43:47 -08:00
York Sun
d4263b8adb powerpc/mpc8xxx: Extend DDR registers' fields
Some DDR registers' fields have expanded to accommodate larger values.
These changes are backward compatible. Some fields are removed for newer
DDR controllers. Writing to those fields are safely ignored.

TIMING_CFG_2 register is fixed. Additive latency is added to RD_TO_PRE
automatically. It was a misunderstanding in commit c360ceac.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-11-25 11:43:46 -08:00
York Sun
9ac4ffbde1 Driver/DDR: Add Freescale DDR driver for ARM
Make PowerPC specific code conditional so ARM SoCs can reuse
this driver. Add DDR3 driver for ARM.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-11-25 11:43:46 -08:00
York Sun
9a17eb5b7e Driver/DDR: combine ccsr_ddr for 83xx, 85xx and 86xx
Fix ccsr_ddr structure to avoid using typedef. Combine DDR2 and DDR3
structure for 83xx, 85xx and 86xx.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-11-25 11:43:46 -08:00
York Sun
5614e71b49 Driver/DDR: Moving Freescale DDR driver to a common driver
Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs.
The similar DDR controllers will be used for ARM-based SoCs.

Signed-off-by: York Sun <yorksun@freescale.com>
2013-11-25 11:43:43 -08:00