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driver/ddr: Add 256 byte interleaving support
Freescale LayerScape SoCs support controller interleaving on 256 byte size. This interleaving is mandoratory. Signed-off-by: York Sun <yorksun@freescale.com>
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6b9e309a8a
commit
6b1e1254f3
6 changed files with 26 additions and 2 deletions
5
README
5
README
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@ -497,6 +497,11 @@ The following options need to be configured:
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same as CONFIG_SYS_DDR_SDRAM_BASE for all Power SoCs. But
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it could be different for ARM SoCs.
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CONFIG_SYS_FSL_DDR_INTLV_256B
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DDR controller interleaving on 256-byte. This is a special
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interleaving mode, handled by Dickens for Freescale layerscape
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SoCs with ARM core.
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- Intel Monahans options:
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CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO
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@ -145,6 +145,7 @@ static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
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if (!popts->memctl_interleaving)
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break;
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switch (popts->memctl_interleaving_mode) {
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case FSL_DDR_256B_INTERLEAVING:
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case FSL_DDR_CACHE_LINE_INTERLEAVING:
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case FSL_DDR_PAGE_INTERLEAVING:
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case FSL_DDR_BANK_INTERLEAVING:
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@ -291,6 +291,7 @@ static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo,
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for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
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if (pinfo->memctl_opts[i].memctl_interleaving) {
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switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
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case FSL_DDR_256B_INTERLEAVING:
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case FSL_DDR_CACHE_LINE_INTERLEAVING:
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case FSL_DDR_PAGE_INTERLEAVING:
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case FSL_DDR_BANK_INTERLEAVING:
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@ -818,21 +818,33 @@ unsigned int populate_memctl_options(int all_dimms_registered,
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* If memory controller interleaving is enabled, then the data
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* bus widths must be programmed identically for all memory controllers.
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*
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* XXX: Attempt to set all controllers to the same chip select
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* Attempt to set all controllers to the same chip select
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* interleaving mode. It will do a best effort to get the
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* requested ranks interleaved together such that the result
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* should be a subset of the requested configuration.
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*
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* if CONFIG_SYS_FSL_DDR_INTLV_256B is defined, mandatory interleaving
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* with 256 Byte is enabled.
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*/
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#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
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if (!hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf))
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#ifdef CONFIG_SYS_FSL_DDR_INTLV_256B
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;
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#else
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goto done;
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#endif
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if (pdimm[0].n_ranks == 0) {
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printf("There is no rank on CS0 for controller %d.\n", ctrl_num);
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popts->memctl_interleaving = 0;
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goto done;
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}
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popts->memctl_interleaving = 1;
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#ifdef CONFIG_SYS_FSL_DDR_INTLV_256B
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popts->memctl_interleaving_mode = FSL_DDR_256B_INTERLEAVING;
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popts->memctl_interleaving = 1;
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debug("256 Byte interleaving\n");
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goto done;
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#endif
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/*
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* test null first. if CONFIG_HWCONFIG is not defined
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* hwconfig_arg_cmp returns non-zero
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@ -1085,6 +1097,7 @@ void check_interleaving_options(fsl_ddr_info_t *pinfo)
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"Memory controller interleaving disabled.\n");
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} else {
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switch (check_intlv) {
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case FSL_DDR_256B_INTERLEAVING:
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case FSL_DDR_CACHE_LINE_INTERLEAVING:
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case FSL_DDR_PAGE_INTERLEAVING:
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case FSL_DDR_BANK_INTERLEAVING:
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@ -228,6 +228,9 @@ void board_add_ram_info(int use_default)
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puts(" DDR Controller Interleaving Mode: ");
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switch ((cs0_config >> 24) & 0xf) {
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case FSL_DDR_256B_INTERLEAVING:
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puts("256B");
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break;
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case FSL_DDR_CACHE_LINE_INTERLEAVING:
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puts("cache line");
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break;
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@ -76,6 +76,7 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
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#define FSL_DDR_PAGE_INTERLEAVING 0x1
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#define FSL_DDR_BANK_INTERLEAVING 0x2
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#define FSL_DDR_SUPERBANK_INTERLEAVING 0x3
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#define FSL_DDR_256B_INTERLEAVING 0x8
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#define FSL_DDR_3WAY_1KB_INTERLEAVING 0xA
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#define FSL_DDR_3WAY_4KB_INTERLEAVING 0xC
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#define FSL_DDR_3WAY_8KB_INTERLEAVING 0xD
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