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driver/ddr/fsl: Adjust timing_cfg_0 to better support two DDR slots

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Increase write-to-write and read-to-read turnaround time for two-slot DDR
configurations. Previously only quad-rank and two dual-rank configurations
have this additional turnaround time. A recent test on two single-rank
DIMMs shows the shorter additional turnaround time is also needed.

Signed-off-by: York Sun <yorksun@freescale.com>
This commit is contained in:
York Sun 2014-11-07 12:14:36 -08:00
parent 9a7eeb9c9f
commit 84baed2a2b
1 changed files with 25 additions and 6 deletions
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31
drivers/ddr/fsl/ctrl_regs.c
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@ -253,22 +253,30 @@ static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
/* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
#if !defined(CONFIG_SYS_FSL_DDR1)
/*
* Check DIMM configuration, return 2 if quad-rank or two dual-rank
* Return 1 if other two slots configuration. Return 0 if single slot.
*/
static inline int avoid_odt_overlap(const dimm_params_t *dimm_params)
{
#if CONFIG_DIMM_SLOTS_PER_CTLR == 1
if (dimm_params[0].n_ranks == 4)
return 1;
return 2;
#endif
#if CONFIG_DIMM_SLOTS_PER_CTLR == 2
if ((dimm_params[0].n_ranks == 2) &&
(dimm_params[1].n_ranks == 2))
return 1;
return 2;
#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
if (dimm_params[0].n_ranks == 4)
return 1;
return 2;
#endif
if ((dimm_params[0].n_ranks != 0) &&
(dimm_params[2].n_ranks != 0))
return 1;
#endif
return 0;
}
@ -316,6 +324,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
#elif defined(CONFIG_SYS_FSL_DDR3)
unsigned int data_rate = get_ddr_freq(0);
int txp;
int odt_overlap;
/*
* (tXARD and tXARDS). Empirical?
* The DDR3 spec has not tXARD,
@ -331,13 +340,23 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
/* set the turnaround time */
/*
* for single quad-rank DIMM and two dual-rank DIMMs
* for single quad-rank DIMM and two-slot DIMMs
* to avoid ODT overlap
*/
if (avoid_odt_overlap(dimm_params)) {
odt_overlap = avoid_odt_overlap(dimm_params);
switch (odt_overlap) {
case 2:
twwt_mclk = 2;
trrt_mclk = 1;
break;
case 1:
twwt_mclk = 1;
trrt_mclk = 0;
break;
default:
break;
}
/* for faster clock, need more time for data setup */
trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1;
@ -383,7 +402,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
);
debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
}
#endif /* defined(CONFIG_SYS_FSL_DDR2) */
#endif /* !defined(CONFIG_SYS_FSL_DDR1) */
/* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,