Commit graph

85390 commits

Author SHA1 Message Date
Pali Rohár
a190667b11 tools: kwboot: Add check that kwbimage contains DDR init code
Some NOR images may be execute-in-place and do not contain DDR init code in
its kwbimage header. Such images cannot be booted over UART as BootROM
loads them to RAM. Add check that kwbimage contains DDR init code in its
header (either as binary code header or as the simple register-value set).

In some cases it is possible to load very small image into L2SRAM and when
DDR init code is not required. So check for L2SRAM load address and skip
DDR init code check in this case.

Signed-off-by: Pali Rohár <pali@kernel.org>
2023-03-01 06:39:17 +01:00
Pali Rohár
53ee6ec827 tools: kwboot: Validate optional kwbimage v1 headers
Before starting parsing of kwbimage, first validate that all optional v1
headers and correct. This prevents kwboot crashes on invalid input.

Signed-off-by: Pali Rohár <pali@kernel.org>
2023-03-01 06:39:17 +01:00
Pali Rohár
7665ed2fa0 tools: kwboot: Fix parsing UART image without data checksum
The 32-bit data checksum in UART image is not checked by the BootROM and
also Marvell tools do not generate it.

So if data checksum stored in UART image does not match calculated checksum
from the image then treat those checksum bytes as part of the executable
image code (and not as the checksum) and for compatibility with the rest of
the code manually insert data checksum into the in-memory image after the
executable code, without overwriting it.

This should allow to boot UART images generated by Marvell tools.

Signed-off-by: Pali Rohár <pali@kernel.org>
2023-03-01 06:39:17 +01:00
Pali Rohár
fa03279e19 tools: kwboot: Add image type documentation
Add information of all available image types and where they should be
stored. Storage location offsets where documented from the disassembly of
the A385 BootROM image dump.

Signed-off-by: Pali Rohár <pali@kernel.org>
2023-03-01 06:39:17 +01:00
Pali Rohár
29b92bb790 tools: kwboot: Add more documentation references
Add reference to Avanta Boot Flow documentation, BobCat2, AlleyCat3 and
PONCat3 BootROM Firmware documentation and links to public Marvell tools:
hdrparser.c and doimage.c

Signed-off-by: Pali Rohár <pali@kernel.org>
2023-03-01 06:39:17 +01:00
Pali Rohár
913d7561c0 arm: mvebu: spl: Fix support for loading U-Boot proper from SD card
Marvell BootROM loads MMC image from sector 0 (HW boot or data partition)
and SD image from sector 1.

So for SD card booting it is needed to not use constant CONFIG MMC options
and instead of them it is needed to define functions spl_mmc_boot_mode()
spl_mmc_get_uboot_raw_sector() which determinate offsets at SPL runtime
based on MMC or SD card.

Calculation of SD card sector expects following values:
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET=0
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0

Fixes: 2226ca1734 ("arm: mvebu: Load U-Boot proper binary in SPL code based on kwbimage header")
Signed-off-by: Pali Rohár <pali@kernel.org>
2023-03-01 06:39:17 +01:00
Pali Rohár
718d1c749f spl: mmc: Allow to disable SYS_MMCSD_FS_BOOT_PARTITION
On some platforms is SYS_MMCSD_FS_BOOT_PARTITION unsupported. So allow to
completely disable MMC FS Boot support via new option SYS_MMCSD_FS_BOOT.

By default MMC FS Boot support is enabled (like it was before) except for
ARCH_MVEBU where MMC FS Boot supported is unsupported due to Marvell
BootROM limitations.

Signed-off-by: Pali Rohár <pali@kernel.org>
2023-03-01 06:39:17 +01:00
Pali Rohár
2f27db2fbd arm: mvebu: spl: Load proper U-Boot from selected eMMC boot partition
When eMMC boot is selected then BootROM loads kwbimage header (U-Boot SPL)
from the selected eMMC boot partition. So for eMMC boot ensure that U-Boot
SPL loads U-Boot proper (from kwbimage) also from the same selected eMMC
boot partition.

Fixes: 2226ca1734 ("arm: mvebu: Load U-Boot proper binary in SPL code based on kwbimage header")
Signed-off-by: Pali Rohár <pali@kernel.org>
2023-03-01 06:39:17 +01:00
Pali Rohár
8b49e63e09 arm: mvebu: spl: Remove checks for BOOT_DEVICE_MMC2 and BOOT_DEVICE_MMC2_2
BOOT_DEVICE_MMC2 and BOOT_DEVICE_MMC2_2 are representing mmc dev 1 but all
Armada SoCs have only one mmc controller. So remove references to
non-existent second mmc controller.

Fixes: f830703f42 ("arm: mvebu: Check that kwbimage blockid matches boot mode")
Signed-off-by: Pali Rohár <pali@kernel.org>
2023-03-01 06:39:17 +01:00
Pali Rohár
a2cd076b7f cmd: mvebu/bubt: Fix parsing SATA kwbimage
Despite the official specification, Marvell BootROM does not interpret
srcaddr from SATA image as number of sectors the beginning of the hard
drive, but as number of sectors relative to the main header.

Reject invalid and accept valid SATA images.

Fixes: 5a06534933 ("cmd: mvebu/bubt: Check for A38x image data checksum")
Signed-off-by: Pali Rohár <pali@kernel.org>
2023-03-01 06:39:17 +01:00
Pali Rohár
d4aa210432 arm: mvebu: spl: Fix parsing SATA kwbimage
Despite the official specification, Marvell BootROM does not interpret
srcaddr from SATA image as number of sectors the beginning of the hard
drive, but as number of sectors relative to the main header.

To process SATA kwbimage and load U-Boot proper from it in the same way as
Marvell BootROM, it is needed to interpret srcaddr as relative offset to
the main header. This change fixes booting of U-Boot proper from SPL code
in SATA image.

Fixes: 2226ca1734 ("arm: mvebu: Load U-Boot proper binary in SPL code based on kwbimage header")
Signed-off-by: Pali Rohár <pali@kernel.org>
2023-03-01 06:39:17 +01:00
Pali Rohár
e1c4ed57d5 tools: kwboot: Fix parsing SATA kwbimage
Despite the official specification, Marvell BootROM does not interpret
srcaddr from SATA image as number of sectors the beginning of the hard
drive, but as number of sectors relative to the main header.

To parse SATA kwbimage in the same way as Marvell BootROM, it is needed to
interpret srcaddr as relative offset to the main header. This change fixes
loading of SATA images via kwboot over UART.

Fixes: 792e423550 ("tools: kwboot: Patch source address in image header")
Signed-off-by: Pali Rohár <pali@kernel.org>
2023-03-01 06:39:17 +01:00
Pali Rohár
954c94aacc tools: kwbimage: Fix generating, verifying and extracting SATA kwbimage
Despite the official specification, Marvell BootROM does not interpret
srcaddr from SATA image as number of sectors the beginning of the hard
drive, but as number of sectors relative to the main header.

The main header is stored at absolute sector number 1. So do not add or
subtract it when calculating with relative offsets to the main header.

Fixes: 501a54a29c ("tools: kwbimage: Fix generation of SATA, SDIO and PCIe images")
Fixes: 5c61710c98 ("tools: kwbimage: Properly set srcaddr in kwbimage v0")
Fixes: e0c243c398 ("tools: kwbimage: Validate data checksum of v1 images")
Fixes: aa6943ca31 ("kwbimage: Add support for extracting images via dumpimage tool")
Signed-off-by: Pali Rohár <pali@kernel.org>
2023-03-01 06:39:17 +01:00
Pali Rohár
eb2c8f3805 cmd: mvebu/bubt: Fix parsing SDIO kwbimage
Despite the official specification, Marvell BootROM does not interpret
srcaddr from SDIO image as offset in number of sectors (like for SATA
image), but as offset in bytes (like for all other images except SATA).

To ensure that we do not store invalid SDIO image to the boot location
(read by the Marvell BootROM), we need to check that image is valid
and srcaddr is intepreted in bytes, in the same way as it is done by
Marvell BootROM.

This fixes rejecting valid and accepting invalid SDIO images by bubt command.

Fixes: 5a06534933 ("cmd: mvebu/bubt: Check for A38x image data checksum")
Signed-off-by: Pali Rohár <pali@kernel.org>
2023-03-01 06:39:17 +01:00
Pali Rohár
353bdaecee arm: mvebu: spl: Fix parsing SDIO kwbimage
Despite the official specification, Marvell BootROM does not interpret
srcaddr from SDIO image as offset in number of sectors (like for SATA
image), but as offset in bytes (like for all other images except SATA).

To process SDIO kwbimage and load U-Boot proper from it in the same way as
Marvell BootROM, it is needed to interpret srcaddr in bytes. This change
fixes booting of U-Boot proper from SPL code stored in SDIO image.

Fixes: 2226ca1734 ("arm: mvebu: Load U-Boot proper binary in SPL code based on kwbimage header")
Signed-off-by: Pali Rohár <pali@kernel.org>
2023-03-01 06:39:17 +01:00
Pali Rohár
8562a1c6a4 tools: kwboot: Fix parsing SDIO kwbimage
Despite the official specification, Marvell BootROM does not interpret
srcaddr from SDIO image as offset in number of sectors (like for SATA
image), but as offset in bytes (like for all other images except SATA).

To parse SDIO kwbimage in the same way as Marvell BootROM, it is needed to
interpret srcaddr in bytes. This change fixes loading of SDIO images via
kwboot over UART.

Fixes: 792e423550 ("tools: kwboot: Patch source address in image header")
Signed-off-by: Pali Rohár <pali@kernel.org>
2023-03-01 06:39:17 +01:00
Pali Rohár
14b866e6d6 tools: kwbimage: Fix generating, verifying and extracting SDIO kwbimage
Despite the official specification, Marvell BootROM does not interpret
srcaddr from SDIO image as offset in number of sectors (like for SATA
image), but as offset in bytes (like for all other images except SATA).

To generate SDIO kwbimage compatible with Marvell BootROM, it is needed to
have srcaddr in bytes. This change fixes SDIO images for Armada 38x SoCs.

Fixes: 501a54a29c ("tools: kwbimage: Fix generation of SATA, SDIO and PCIe images")
Fixes: 5c61710c98 ("tools: kwbimage: Properly set srcaddr in kwbimage v0")
Fixes: e0c243c398 ("tools: kwbimage: Validate data checksum of v1 images")
Fixes: aa6943ca31 ("kwbimage: Add support for extracting images via dumpimage tool")
Signed-off-by: Pali Rohár <pali@kernel.org>
2023-03-01 06:39:17 +01:00
Tom Rini
daaca13b52 Merge tag 'u-boot-rockchip-20230228' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
Please pull the updates for rockchip platform:
- Add support for rk3588 soc;
- Add rk3588 Edgeble Neu6 board and Radxa ROCK5B board;
- Add rk3308 Radxa ROCK Pi S board;
- Add rk3568 Radxa ROCK 3 board,
- Add rk3566 Radxa Compute Module 3 board;
- Add support for sdram reg info version 3
- Refactor rockchip OTP/eFuse driver and add more soc support;
- Add external TPL support for binman;

binman support for mkimage ignore missing entry is based on [1];

[1] https://patchwork.ozlabs.org/project/uboot/patch/20230219220158.4160763-7-jonas@kwiboo.se/
2023-02-28 20:24:25 -05:00
Tom Rini
f10905b4b7 TPM auto startup and testing
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Merge tag 'tpm-next-28022023' of https://source.denx.de/u-boot/custodians/u-boot-tpm into next

TPM auto startup and testing:

Due to U-Boot's lazy binding we always relied on command line tools to
initialize the TPM subsystem and devices.  One exception is the EFI
subsystem.  When compiled with TCG2 measured boot support the TPM was
automatically initialized.

However that init was not complete.  The TCG specs [0] (and specifically
§12.3 Self-test modes) describe how self-tests on the device should be
performed.  This PR is adding an extra API function, that can be used to
initialize the TPM2.0 properly.

Simon added the equivalent for TPM1.2 and refactored the DM tests to
include the new funtion.

[0] https://trustedcomputinggroup.org/wp-content/uploads/TPM-Rev-2.0-Part-1-Architecture-01.07-2014-03-13.pdf
2023-02-28 09:50:16 -05:00
Tom Rini
c12fe739ea Pull request for u-boot-nand-20230227
- mark reserved blocks from Ashok Reddy Soma
 - backport BRCMNAND changes from Linux from Linus Walleij
 - fix display of unknown raw ID from Patrice Chotard
 - show reserved block in chip.erase from Michael Trimarchi
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Merge tag 'u-boot-nand-20230227' of https://source.denx.de/u-boot/custodians/u-boot-nand-flash into next

Pull request for u-boot-nand-20230227

- mark reserved blocks from Ashok Reddy Soma
- backport BRCMNAND changes from Linux from Linus Walleij
- fix display of unknown raw ID from Patrice Chotard
- show reserved block in chip.erase from Michael Trimarchi
2023-02-28 09:46:07 -05:00
Eugen Hristev
a6e85a35b5 board: rock5b-rk3588: add memory gaps into kernel's DTB
RK3588 has two memory gaps when using 16 GiB DRAM size:
[0x3fc000000 , 0x3fc500000]
and
[0x3fff00000 , 0x3ffffffff]

If the kernel is agnostic to these gaps, accessing the area causes
a SError panic.

Hence, add reserved memory areas in kernel's DTB before booting.

Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:29 +08:00
Eugen Hristev
3bf8e40807 board: rockchip: add Radxa ROCK5B Rk3588 board
ROCK 5B is a Rockchip RK3588 based SBC (Single Board Computer) by Radxa.

There are tree variants depending on the DRAM size : 4G, 8G and 16G.

Specification:

    Rockchip Rk3588 SoC
    4x ARM Cortex-A76, 4x ARM Cortex-A55
    4/8/16GB memory LPDDR4x
    Mali G610MC4 GPU
    MIPI CSI 2 multiple lanes connector
    eMMC module connector
    uSD slot (up to 128GB)
    2x USB 2.0, 2x USB 3.0
    2x HDMI output, 1x HDMI input
    Ethernet port
    40-pin IO header including UART, SPI, I2C and 5V DC power in
    USB PD over USB Type-C
    Size: 85mm x 54mm

Kernel commits:
a1d3281450ab ("arm64: dts: rockchip: Add rock-5b board")
6fb13f888f2a ("arm64: dts: rockchip: Update sdhci alias for rock-5b")

Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:29 +08:00
Vasily Khoruzhick
f0eb365e21 clk: rockchip: rk3568: add more supported clk rates for sdmmc and emmc
SDHCI driver may attempt to set 26MHz clock, but clk_rk3568
will return error in this case. Apparently, SDHCI silently ignores the
error and as a result eMMC initialization fails.

Add 25 MHz and 26 MHz clk rates for sdmmc and emmc on rk3568 to fix that.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:29 +08:00
Jonas Karlman
3a539e0862 rockchip: rk3588: Read cpuid from otp
Read cpuid from otp and set ethaddr for RK3588.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:29 +08:00
Jonas Karlman
2eedb6d93f rockchip: rk3568: Read cpuid from otp
The cpuid on RK3568 is located at 0xa instead of 0x7 as all other SoCs.
Add and use a CFG_CPUID_OFFSET to define this offset.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:28 +08:00
Jonas Karlman
628fb0683b rockchip: misc: Set eth1addr mac address
Set eth1addr in addition to ethaddr.

Also allow fdt fixup of ethernet mac addresses when CMD_NET is disabled.
Set ethaddr and eth1addr based on HASH and SHA256 options.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:28 +08:00
Jonas Karlman
dd5684b878 rockchip: efuse: Add support for RK3036
Add support for rk3036 compatible.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:28 +08:00
Jonas Karlman
16e8afa802 rockchip: efuse: Add support for RK3128
Add support for rk3128 compatible.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:28 +08:00
Jonas Karlman
b0828cf989 rockchip: efuse: Add support for RK3328
Add support for rk3328 compatible.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:28 +08:00
Jonas Karlman
6f95b3e103 rockchip: efuse: Add support for RK3288 and more
Add support for rk3066a, rk3188, rk322x and rk3288 compatible.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:28 +08:00
Jonas Karlman
433260ac1a rockchip: efuse: Refactor to use driver data and ops
Refactor the driver to use driver data and ops to simplify handling
of SoCs that require a unique read op.

Move handling of the aligned bounce buffer to main read op in order to
keep the SoC unique read op simple.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:28 +08:00
Jonas Karlman
9a850d1fcd rockchip: otp: Add dump_otp debug command
Add a simple debug command to dump the content of the otp.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:28 +08:00
Jonas Karlman
f888098229 rockchip: otp: Add support for RK3588
Add support for rk3588 compatible.

Adjust offset using driver data in main read op.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:28 +08:00
Jonas Karlman
d58d55d242 rockchip: otp: Add support for RK3568
Add support for rk3568 compatible.

Handle allocation of an aligned bounce buffer in main read op in order
to keep the SoC unique read op simple.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:28 +08:00
Jonas Karlman
8fa1870e11 rockchip: otp: Refactor to use driver data and ops
Refactor the driver to use driver data and ops to simplify handling
of SoCs that require a unique read op.

Use readl_poll_sleep_timeout instead of a custom poll loop, and add
validation of input parameter to main read op.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:28 +08:00
Jagan Teki
15b2d1fb72 board: rockchip: Add Edgeble Neural Compute Module 6
Neural Compute Module 6(Neu2) is a 96boards SoM-CB compute module
based on Rockchip RK3588 from Edgeble AI.

General features:
- Rockchip RK3588
- up to 32GB LPDDR4x
- up to 128GB eMMC
- 2x MIPI CSI2 FPC

On module WiFi6/BT5 is available in the following Neu6 variants.

Neural Compute Module 6(Neu6) IO board is an industrial form factor
ready-to-use IO board from Edgeble AI.

IO board offers plenty of peripherals and connectivity options and
this patch enables basic eMMC and UART which is enough to successfully
boot Linux.

Neu6 needs to mount on top of this IO board in order to create a
complete Edgeble Neural Compute Module 6(Neu6) IO platform.

Boot log for the record,

DDR Version V1.08 20220617
LPDDR4X, 2112MHz
channel[0] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
channel[1] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
channel[2] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
channel[3] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
Manufacturer ID:0x6
CH0 RX Vref:31.7%, TX Vref:21.8%,21.8%
CH1 RX Vref:30.7%, TX Vref:22.8%,23.8%
CH2 RX Vref:30.7%, TX Vref:22.8%,22.8%
CH3 RX Vref:30.7%, TX Vref:21.8%,21.8%
change to F1: 528MHz
change to F2: 1068MHz
change to F3: 1560MHz
change to F0: 2112MHz
out

U-Boot SPL 2023.01-00952-g1d1785a516-dirty (Jan 30 2023 - 19:53:55 +0530)
Trying to boot from MMC1
INFO:    Preloader serial: 2
NOTICE:  BL31: v2.3():v2.3-391-g856309329:derrick.huang
NOTICE:  BL31: Built : 14:15:50, Jul 18 2022
INFO:    ext 32k is not valid
INFO:    GICv3 without legacy support detected.
INFO:    ARM GICv3 driver initialized in EL3
INFO:    system boots from cpu-hwid-0
INFO:    idle_st=0x21fff, pd_st=0x11fff9, repair_st=0xfff70001
INFO:    dfs DDR fsp_params[0].freq_mhz= 2112MHz
INFO:    dfs DDR fsp_params[1].freq_mhz= 528MHz
INFO:    dfs DDR fsp_params[2].freq_mhz= 1068MHz
INFO:    dfs DDR fsp_params[3].freq_mhz= 1560MHz
INFO:    BL31: Initialising Exception Handling Framework
INFO:    BL31: Initializing runtime services
WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE initialization. SMC`s destined for OPTEE will return SMC_UNK
ERROR:   Error initializing runtime service opteed_fast
INFO:    BL31: Preparing for EL3 exit to normal world
INFO:    Entry point address = 0xa00000
INFO:    SPSR = 0x3c9

U-Boot 2023.01-00952-g1d1785a516-dirty (Jan 30 2023 - 19:53:55 +0530)

Model: Edgeble Neu6A IO Board
DRAM:  7.5 GiB (effective 3.7 GiB)
Core:  71 devices, 15 uclasses, devicetree: separate
MMC:   mmc@fe2c0000: 0
Loading Environment from nowhere... OK
In:    serial@feb50000
Out:   serial@feb50000
Err:   serial@feb50000
Model: Edgeble Neu6A IO Board
Net:   No ethernet found.
Hit any key to stop autoboot:  0
=>

Add support for Edgeble Neu6 Model A IO Board.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:28 +08:00
Jagan Teki
95c8656b72 ARM: dts: rockchip: rk3588s-u-boot: Add sdmmc node
Booting from SDMMC is one of the fast and easy booting methods
for initial support of any SoC to upstream more features. 

This patch is trying to add the sdmmc node for rk3588 and added
as u-boot specific node in -u-boot.dtsi as upstream Linux is not
supporting yet.

As soon as Linux supports it, a sync of the Linux device tree
would eventually drop this node. 

Clock properties as added according to the rockchip mmc driver
but the actual definition might add scmi clocks into 0 and 1
indexes. This is due to scmi clock are not supporting in upstream
U-Boot. Properly addition of scmi clock would eventually follow
sdmmc clock definition of Linux once they upstreamed.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
2023-02-28 18:07:28 +08:00
Jagan Teki
2a8481ec16 ARM: dts: rockchip: Add rk3588-u-boot.dtsi
Add u-boot,dm-spl and u-boot,dm-pre-reloc related properties
for Rockchip RK3588 SoC to boot the SPL.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:28 +08:00
Jagan Teki
f5bc9929a2 arm: rockchip: Add RK3588 arch core support
The Rockchip RK3588 is a ARM-based SoC with quad-core Cortex-A76
and quad-core Cortex-A55 including NEON and GPU, 6TOPS NPU,
Mali-G610 MP4, HDMI Out, HDMI In, DP, eDP, MIPI DSI, MIPI CSI2,
LPDDR4/4X/5, eMMC5.1, SD3.0/MMC4.5, USB OTG 3.0, Type-C, USB 2.0,
PCIe 3.0, SATA 3, Ethernet, SDIO3.0 I2C, UART, SPI, GPIO and PWM.

Add arch core support for it.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:28 +08:00
Jagan Teki
5457e15272 arm64: dts: rockchip: rk3588: Add Edgeble Neu6 Model A IO
Neural Compute Module 6(Neu6) IO board is an industrial form factor
ready-to-use IO board from Edgeble AI.

IO board offers plenty of peripherals and connectivity options and
this patch enables basic eMMC and UART which is enough to successfully
boot Linux.

Neu6 needs to mount on top of this IO board in order to create a
complete Edgeble Neural Compute Module 6(Neu6) IO platform.

commit <a5079a534554> ("arm64: dts: rockchip: rk3588: Add Edgeble Neu6
Model A IO")

Add support for Edgeble Neu6 Model A IO Board.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:28 +08:00
Jagan Teki
a0e94b877c arm64: dts: rockchip: rk3588: Add Edgeble Neu6 Model A SoM
Neural Compute Module 6(Neu2) is a 96boards SoM-CB compute module
based on Rockchip RK3588 from Edgeble AI.

General features:
- Rockchip RK3588
- up to 32GB LPDDR4x
- up to 128GB eMMC
- 2x MIPI CSI2 FPC

On module WiFi6/BT5 is available in the following Neu6 variants.

Neu6 needs to mount on top of associated Edgeble IO boards for
creating complete platform solutions.

Enable eMMC for now to boot Linux successfully.

commit <3d9a2f7e7c5e> ("arm64: dts: rockchip: rk3588: Add Edgeble Neu6
Model A SoM")

Add support for Edgeble Neu6 Model A SoM.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:28 +08:00
Jagan Teki
515773ba9d arm64: dts: rockchip: Add base DT for rk3588 SoC
This initial version supports CPU, dma, interrupts, timers, UART and
SDHCI (everything necessary to boot Linux on this system on chip) as
well as Ethernet, I2C, PWM and SPI.

The DT is split into rk3588 and rk3588s, which is a reduced version
(i.e. with less peripherals) of the former.

commit <9fb232e9911f> (" arm64: dts: rockchip: Add base DT for rk3588
SoC")
commit <d68a97d501f8> ("arm64: dts: rockchip: Add rk3588 pinctrl data")

Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:28 +08:00
Jagan Teki
d8656cb647 arm: rockchip: Add ioc header for rk3588
Add IOC unit header include for rk3588.

Signed-off-by: Steven Liu <steven.liu@rock-chips.com>
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:28 +08:00
Jagan Teki
a0f5a61dc1 dt-bindings: reset: add rk3588 reset definitions
Add reset ID defines for rk3588.

commit <0a8eb7dae617> ("dt-bindings: reset: add rk3588 reset
definitions")

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:28 +08:00
Jagan Teki
a8ac0d53f9 dt-bindings: power: Add power-domain header for rk3588
Add power-domain header for RK3588 SoC from description in TRM.

commit <67944950c2d0> ("dt-bindings: power: add power-domain header for
rk3588")

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:28 +08:00
Jagan Teki
3b7f29f2c8 ram: rockchip: Add rk3588 ddr driver support
Add ddr driver for rk3588 to get the ram capacity.

Co-developed-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:27 +08:00
Jagan Teki
b851c006a1 clk: rockchip: pll: Add pll_rk3588 type for rk3588
Add RK3588 pll set and get rate clock support.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:27 +08:00
Jagan Teki
7a474df740 clk: rockchip: Add rk3588 clk support
Add clock driver support for Rockchip RK3588 SoC.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:27 +08:00
Jagan Teki
f71feb4738 dt-bindings: clk: Add dt-binding header for RK3588
Add the dt-bindings header for the Rockchip RK3588, that gets
shared between the clock controller and the clock references
in the dts.

commit <f204a60e545c> ("dt-bindings: clock: add rk3588 clock
definitions")

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:27 +08:00
Jagan Teki
73a21ebf47 arm: rockchip: Add grf header for rk3588
Add GRF header for Rockchip RK3588.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2023-02-28 18:07:27 +08:00