To resolve DCNANO underrun issue, change the DDR Port 0 arbitration
from round robin fashion to fixed priority level 1, while other ports
are not assigned any priority, so they will be serviced in round robin
fashion if there is no active request from Port 0.
Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
The ECC fuse on 8ULP can't be written twice. If any user did it, the
ECC value would be wrong then cause accessing problem to the fuse.
The patch will lock the ECC fuse word to avoid this problem.
For iMX9, the OTP controller automatically prevents an ECC fuse word to
be written twice. So it does not need the setting.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Since new 8ULP A1 S400 FW (v0.0.8-e329b760) can support to read
more fuses: like PMU trim, Test flow/USB, GP1-5, GP8-10. Update
the u-boot driver for the new mapping.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Alice Guo <alice.guo@nxp.com>
From Sentinel FW v0.0.9-9df0f503, the response message of get info API
is changed to add OEM SRK and some states (IMEM, CSAL, TRNG).
With old structure, we get failure from sentinel due to the buffer
size can't fit with new response message. So update the API structure
to fix the issue.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
This patch is used to support DBD owner fuse changed to S400 only.
The XRDC PDAC2 for LPAV pbridge5 and MSC1/2/3 for GPIO and LPAV are not
configured by S400 default setting. So these PDAC and MSC are invalid,
only DBD owner can access the corresponding resources.
We have to configure necessary PDAC and MSC for SPL before DDR
initialization.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
To clean the upower codes by aligning codes format, check err_code
and add detail bits list for the memory magic number
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
The swton indicates the logic switch, magic number 0xfff80 is hard
to understand, so use macro.
Some board design may not have MIPI_CSI voltage input connected per
data sheet. In that case, the upower power on API may dead loop mu to wait
response, however there is no response. So remove MIPI_CSI here, let
linux power domain driver to runtime enable the power domain.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
At present, in cgc1_pll3_init we don't set the pll3pfd div values,
just use the default 0. But on A1 part, ROM will set PLL3 pfd1div2
to 1 and pfd2div1 to 3.
This finally causes some clocks' rate decreased, for example USDHC.
So clear the PLL3DIV_PFD dividers to get correct rate.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Some space in SRAM0 will be protected by S400 to allow RX SecPriv mode
access only for boot purpose. Since SW will reuse the SRAM0 as SCMI
buffer and SPL container loading buffer, need to reconfigure MRC3.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
To align with ARM trusted firmware's change, adjust DRAM timing
save area to new position 0x20055000. So we can release the space
since 0x2006c000 for the NOBITS region of ARM trusted firmware
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Need to add DRAM access permission for S400, as S400 needs to access
it When SPL calls image authentication
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
To fit the DBD_EN fused part, we re-design the TRDC and XRDC assignment.
M33 will be the TRDC owner and needs to configure TRDC. A35 is the
XRDC owner, ATF will configure XRDC.
The handshake between U-boot and M33 image is used to sync TRDC and
XRDC configuration completion. Once the handshake is done, A35 and M33
can access the allowed resources in others domain.
The handshake is needed when M33 is booted or DBD_EN fused, because both
cases will enable the TRDC. If handshake is timeout, the boot will hang.
We use SIM GPR0 to pass the info from SPL to u-boot, because before the
handshake, u-boot can't access SEC SIM and FSB.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
As M33 is responsible for TRDC configuration, the settings for A35
nonsecure world access and DMA0 access are moved to M33 image.
So remove the codes to release TRDC and configure it. Just keep
the configurations for reference.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
iMX8ULP A1 S400 ROM removes the setting for MRC4/5. So we have to set
them in SPL to allow access to DDR from A35 and APD PER masters
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Since A1 ROM has fixed the ROM API eMMC issue, we should only use
the workaround for A0.1 part. Add a SOC revision check.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
In both SPL and u-boot, after probing the S400 MU, get the chip revision,
lifecycle and UID from Sentinel.
Update get_cpu_rev to use the chip revision not hard coded it for A0
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Since latest DTS has added multiple MU nodes, using compatible
string to find the device node is not proper. It finds the first
node with the compatible string matched even the node is disabled.
Signed-off-by: Ye Li <ye.li@nxp.com>
-----BEGIN PGP SIGNATURE-----
iQFQBAABCgA6FiEEqxhEmNJ6d7ZdeFLIHrMeAg6sL8gFAmQirs0cHGV1Z2VuLmhy
aXN0ZXZAY29sbGFib3JhLmNvbQAKCRAesx4CDqwvyIWBCACz3Bh76v3vbqhaQPBq
ZGB+jnaZQsWW9r285dCmQFA/xGLbQoMVIhzvLVmEcZdr0d9wHUEsy1IzC6tak2MJ
NkiYcNRb3lnYEDthvjGdpz6QIGZBBOj8l8ha70z4ZvzBwTfOReB04N5207n5Tzq/
hAFAWcM3VxfVXF2Xb8O/HbyEbOVXKY65xWinAIZqvGscox+vx3Vj9m1aLqcQP0Wy
bCZowynfyKWiFrHr5TYgpmL4ROsj3jbnRhC0dqyB+ewRdRAK4uVJXRj23ywwDcGH
VqlYFVFT8EY5HSzCG8VGMtGqV+H4+K4RYiTLtDwtbHWdXnUKLKORXtXi2xcHHxS1
rj5U
=kb6/
-----END PGP SIGNATURE-----
Merge tag 'u-boot-at91-2023.07-a' of https://source.denx.de/u-boot/custodians/u-boot-at91 into next
First set of u-boot-at91 features for the 2023.07 cycle:
This feature set includes the clock changes required for sam9x60 SoC to
support USB host.
While this change is correct for v2023.04 it is not correct for next
(where this is right now) nor post-v2023.04.
This reverts commit 8653e5d3b7.
Signed-off-by: Tom Rini <trini@konsulko.com>
- A series of minor cleanups to DISTRO_DEFAULTS and BOOTSTD so that the
rk3399 bootstd migration can be complete and functional now, and make
future migrations easier.
The defined altbootcmd was specific to distro_bootcmd which is not
longer in use on these platforms, so drop it.
Tested-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Tom Rini <trini@konsulko.com>
When we do not enable DISTRO_DEFAULTS (generally, to get distro_bootcmd)
we instea do want to imply BOOTSTD_DEFAULTS so that when using bootstd
the general distro boot functionality will still work.
Signed-off-by: Tom Rini <trini@konsulko.com>
These board have moved to standard boot but the old 'distro_bootcmd'
command is still active. Disable DISTRO_DEFAULTS to fix this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Vagrant Cascadian <vagrant@debian.org>
These two features use a lot of common options. Move them into a common
CONFIG to reduce duplication.
Use 'select' for most options since these are things that boards aren't
supposed to override. For now it is not possible to disable
BOOT_DEFAULTS but we may take another look later.
Note that five options use 'imply' to match existing behaviour.
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Rework a bit so we don't grow so many platforms unintentionally]
Signed-off-by: Tom Rini <trini@konsulko.com>
Unfortunately the IRAM used to stash the bootstage records in TPL
becomes inaccessible after SPL runs. Presumably this is because of ATF
taking it over.
We could move the stash to another address in SPL, before passing it to
U-Boot proper. But it seems easier to wait until we have support for
standard passage[1] which should not be too far away.
For now, disable it in TPL and SPL.
[1] https://patchwork.ozlabs.org/project/uboot/cover/
20220117150428.1580273-1-sjg@chromium.org/
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Vagrant Cascadian <vagrant@debian.org>
Add the configs required to use the SAM9X60's USB clock.
Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
[claudiu.beznea: added CONFIG_AT91_SAM9X60_USB to
sam9x60_curiosity_mmc1_defconfig]
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
In order for some of the functionalities, such as the USB clocks,
to work properly we need some clocks to be properly initialised
at the very beginning of booting.
Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Clock setup was intended for setting clocks at boot time on SAMA7G5,
e.g. for root clocks like PLLs, that were used to feed IPs needed alive
in u-boot (e.g. Ethernet clock feed by a PLL). Export this functionality
to all at91 clocks as it may be necessary on other SoCs.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Register into DM the clocks required to properly enable USB functionality
within the bootloader.
Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Implement sam9x60 USB clock driver. This clock has
three parents: PLLA, UPLL and MAINXTAL. The driver is
aware of the three possible parents with the help of the
two mux tables provied to the driver during the registration
of the clock.
Signed-off-by: Sergiu Moga <sergiu.moga@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
With recent CONFIG_TEXT_BASE changes, there are inconsistencies between
several settings.
Adjust CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC
cache out of the way too.
Fixes: e23cae3080 ("x86: som-db5800-som-6867: Adjust CONFIG_TEXT_BASE")
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
With recent CONFIG_TEXT_BASE changes, there are inconsistencies between
several settings.
Adjust CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC
cache out of the way too.
Fixes: 5d1c8342ae ("x86: dfi-bt700: Adjust CONFIG_TEXT_BASE")
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
With recent CONFIG_TEXT_BASE changes, there are inconsistencies between
several settings.
Adjust CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC
cache out of the way too.
Fixes: 388f93f963 ("x86: conga-qeval20-qa3-e3845: Adjust CONFIG_TEXT_BASE")
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
With recent CONFIG_TEXT_BASE changes, there are inconsistencies between
several settings.
Adjust CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC
cache out of the way too.
Fixes: f38be30868 ("x86: bayleybay: Adjust CONFIG_TEXT_BASE")
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
With recent CONFIG_TEXT_BASE changes, there are inconsistencies between
several settings.
Adjust CONFIG_SYS_MONITOR_LEN to allow more code space. Move the MRC
cache out of the way too.
Add documentation on how to make this change safely.
Fixes: 66e2c665f3 ("x86: minnowmax: Adjust CONFIG_TEXT_BASE")
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Documenation:
* add man-page for efi command
UEFI:
* Let EFI app call ExitBootServices() before legacy booting kernel
* Support zboot and bootm in the EFI app
* Let efi command show configuration tables
* Support booting a 64-bit kernel from 64-bit EFI app
* Allocate device-tree copy from high memory
* simplify efi_str_to_u16()
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEEbcT5xx8ppvoGt20zxIHbvCwFGsQFAmQfHDAACgkQxIHbvCwF
GsRCWg/8DOCb1igYd8D2nnCTfNEQRkkRvOyc8W3O687fX04e9N3eV8eEFvgBnecL
zF2OT+VmQPq2eWIopOfqCWrIFDr1sbSUAdcPT8aM3s/2/ONFTnnUsvt8G3Qp8vyY
nY+M466bl8Fh841aGtmqsuwBHTddjF8WFUcsj2FAG3laHbnSsVANHDPhSe7C6Fg+
g3FtXZf51SEudTTK8RLa/+df4tji/UX0BLOIr6JZ+xqb+y/Tg/P2N5DAqIQCBTL1
BZ7U/yVXs8M9MHU8T5TtshUL1WvFogbZYkx1kRAH3Rkg0ArD1rxV0Xd64Gmrdoyi
71filEFNV860ytsxBjCbE+YaczqRR1oteyPlak0ApmGf+FRKIU047hpuS2RBsJqv
g1xZg9EsoU4wbsOfVd7FHER63YGPfmH9pa5A5ULpq60tYuoTthToV1up2XVjxiZm
hSxWGmz7dzMlqtuJiKm1R2Nug4N6a+SPSA+l8JDWSBxXZ5Ld5HZaZ99DR+phYcbE
nzZfIePoPq8JCVb7vMpIi7m1MdUEjNUNAWEjHa1Gug71qbgULQ4mi+z192F+h51E
HQ8qs+T6GFzFBrNPrem4wxfNa3UeBQzyTbYiaAcQgSuY942jn9ZrZ78epZbBbPCI
r6LSgBlmtkQoyuPzgk6oX7NRU7Mqd9jOEQaWo7RF8LjdO5UgIrM=
=a5J7
-----END PGP SIGNATURE-----
Merge tag 'efi-next-20230325' of https://source.denx.de/u-boot/custodians/u-boot-efi into next
Pull request for efi-next-20230325
Documenation:
* add man-page for efi command
UEFI:
* Let EFI app call ExitBootServices() before legacy booting kernel
* Support zboot and bootm in the EFI app
* Let efi command show configuration tables
* Support booting a 64-bit kernel from 64-bit EFI app
* Allocate device-tree copy from high memory
* simplify efi_str_to_u16()
UEFI:
* Create unique device paths for USB devices with the same vendor
and product id.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEEbcT5xx8ppvoGt20zxIHbvCwFGsQFAmQewugACgkQxIHbvCwF
GsSLMA/+LlG5/QsfJC++3i6v1QtDNksv2VNyEXIUnane2QGj/Ch7fwoK3nKm9KOD
KEOnYKONFZfiPKK1On7ITJwnhR8dsag/5x+JAsjmFc4n2TE1XqN5H0JmCc1X7Ees
bB92jSlaMpYi2wZQ2CPmzTOsG9jSVOv0u+CrL3cbrIuuXmsKY8MpfDeuvHCwiEXJ
w5WhAwJoS1LF6rqndHZJIczI74S3ixAQ4BhpiMxNvNdm2Vl/0A43SuxlEIU16HMz
tTiwKCc0IrQg03CF8atFPfJCq4v0xF2cjBV9hn93BZiKety6YCQptdmCjyNjUnuZ
mrT3Wqth6vcYmL16FIkbZl7GADMt8d5sA5daORI56qSseEVtHYmJ3RqO6ZgYebNP
hQwGwVB23lGF742hB1IXvjXVeqHoIGFSDb/aI1IZ3zdZJ/OFOqSkFe8CfTLq3rR9
SB6pbxsOzL7jwi4MbcWrdByk79933XMUfr8fm+yIkqf3yhWlihnQmr6au/X27SmW
veAXfQmjrPsMYFlEgVI+oFXYUKRp0McO0tLO3gNd/ROMNAs0w1f3NV5hz8dCx0Sp
r4Fi+pthrG41fF8Vcc4bK6XqddXONfhZ4uOWGLoGr9lAnixw4iF6oN7lYPvBJL/T
ej2zCL/vLRWawJ9OJ97uA10FFtUKla6JpD1b2JscQNWGJxspj58=
=oE1C
-----END PGP SIGNATURE-----
Merge tag 'efi-2023.04-rc5' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request for efi-2023.04-rc5
UEFI:
* Create unique device paths for USB devices with the same vendor
and product id.
The bootefi command creates a copy of the device-tree within the first
127 MiB of memory. This may lead to overwriting previously loaded binaries
(e.g. kernel, initrd).
Linux EFI stub itself copies U-Boot's copy of the device-tree. This means
there is not restriction for U-Boot to place the device-tree copy to any
address. (Restrictions existed for 32bit ARM before Linux commit
7a1be318f579 ("ARM: 9012/1: move device tree mapping out of linear region")
for legacy booting.
Reported-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Tested-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Add an option to package a kernel into the debugging script used for
EFI.
The name of the kernel must be added to the script. By default it is
assumed that the kernel is built in the /tmp/kernel directory.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add a command (for the app and payload) to display the tables provided
by EFI. Note that for the payload the tables should always be present, so
an error message is unnecessary and would bloat the code.
Signed-off-by: Simon Glass <sjg@chromium.org>
