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34 commits

Author SHA1 Message Date
Jean-Christophe PLAGNIOL-VILLARD
6d0f6bcf33 rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-10-18 21:54:03 +02:00
Stefan Roese
d1631fe1a0 ppc4xx: Consolidate PPC4xx UIC defines
This 2nd patch now removes all UIC mask bit definition. They should be
generated from the vectors by using the UIC_MASK() macro from now on.
This way only the vectors need to get defined for new PPC's.

Also only the really used interrupt vectors are now defined. This makes
definitions for new PPC versions easier and less error prone.

Another part of this patch is that the 4xx emac driver got a little
cleanup, since now the usage of the interrupts is clearer.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-07-11 13:18:14 +02:00
Stefan Roese
7ee2619c20 ppc4xx: Consolidate PPC4xx EBC defines
This patch removes all EBC related defines from the PPC4xx headers
ppc405.h and ppc440.h and introduces a new header

include/asm-ppc/ppc4xx-ebc.h

with all those defines.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-07-11 13:18:13 +02:00
Grant Erickson
103201731b ppc4xx: Add SDR0_SRST Mnemonics for the 405EX(r)
This patch adds bit field mnemonics for the 405EX(r) SDR0_SRST soft reset register.

Signed-off-by: Grant Erickson <gerickson@nuovations.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-07-11 13:18:13 +02:00
Stefan Roese
36ea16f6a0 ppc4xx: Consolidate PPC4xx SDRAM/DDR/DDR2 defines, part1
This patch removes all SDRAM related defines from the PPC4xx headers
ppc405.h and ppc440.h. This is needed since now some 405 PPC's use
the same SDRAM controller as 440 systems do (like 405EX and 440SP).

It also introduces new defines for the equipped SDRAM controller based on
which PPC variant is used. There new defines are:

used on 405GR/CR/EP and some Xilinx Virtex boards.

used on 440GP/GX/EP/GR.

used on 440EPx/GRx.

used on 405EX/r/440SP/SPe/460EX/GT.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-06-03 20:21:53 +02:00
Grant Erickson
c821b5f120 ppc4xx: Enable Primordial Stack for 40x and Unify ECC Handling
This patch (Part 1 of 2):

* Rolls up a suite of changes to enable correct primordial stack and
  global data handling when the data cache is used for such a purpose
  for PPC40x-variants (i.e. CFG_INIT_DCACHE_CS).

* Related to the first, unifies DDR2 SDRAM and ECC initialization by
  eliminating redundant ECC initialization implementations and moving
  redundant SDRAM initialization out of board code into shared 4xx
  code.

* Enables MCSR visibility on the 405EX(r).

* Enables the use of the data cache for initial RAM on
  both AMCC's Kilauea and Makalu and removes a redundant
  CFG_POST_MEMORY flag from each board's CONFIG_POST value.

  - Removed, per Stefan Roese's request, defunct memory.c file for
    Makalu and rolled sdram_init from it into makalu.c.

With respect to the 4xx DDR initialization and ECC unification, there
is certainly more work that can and should be done (file renaming,
etc.). However, that can be handled at a later date on a second or
third pass. As it stands, this patch moves things forward in an
incremental yet positive way for those platforms that utilize this
code and the features associated with it.

Signed-off-by: Grant Erickson <gerickson@nuovations.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-06-03 20:20:50 +02:00
Wolfgang Denk
53677ef18e Big white-space cleanup.
This commit gets rid of a huge amount of silly white-space issues.
Especially, all sequences of SPACEs followed by TAB characters get
removed (unless they appear in print statements).

Also remove all embedded "vim:" and "vi:" statements which hide
indentation problems.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-05-21 00:14:08 +02:00
Stefan Roese
6f2eb3f3d8 ppc4xx: Add basic support for AMCC 460EX/460GT (4/5)
This patch adds basic support for the AMCC 460EX/460GT PPC's.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-15 07:28:04 +01:00
Niklaus Giger
8cc10d06b8 ppc4xx: PPC405GPr fix missing register definitions
Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
2008-02-16 06:39:46 +01:00
Stefan Roese
7cfc12a7dc ppc4xx: 405EX: Correctly enable USB pins
This patch selects the USB data pins in the 405EX GPIO and MFC (multi
function control) registers. This is done for the AMCC Kilauea and
Makalu eval boards.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-12-08 14:47:34 +01:00
Stefan Roese
aee747f19b ppc4xx: Enable 440 GPIO init table CFG_440_GPIO_TABLE for 405 platforms
- Rename CFG_440_GPIO_TABLE to CFG_4xx_GPIO_TABLE
- Cleanup of the 4xx GPIO functions
- Move some GPIO defines from the cpu headers ppc405.h/ppc440.h into gpio.h

Signed-off-by: Stefan Roese <sr@denx.de>
2007-11-15 14:23:55 +01:00
Stefan Roese
9b94ac61d2 ppc4xx: Rework 4xx cache support
New cache handling functions added and all existing functions
moved from start.S into seperate cache.S.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:21:46 +01:00
Stefan Roese
087dfdb79b ppc4xx: Consolidate some of the 405 and 440 macros/structs into 4xx
This patch moves some common 4xx macros and the PPC405_SYS_INFO/
PPC440_SYS_INFO structure into the common ppc4xx.h header.

Lot's of other macros are good candidates to be consolidated this way
in the future.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:50 +01:00
Stefan Roese
db3232ddb0 ppc4xx: Fix small merge problems with CPCI440 and Acadia boards
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:50 +01:00
Stefan Roese
dbbd125721 ppc4xx: Add PPC405EX support
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:49 +01:00
Stefan Roese
34886bbea2 Merge with /home/stefan/git/u-boot/zeus 2007-08-14 15:00:42 +02:00
Stefan Roese
779e975117 ppc4xx: Add initial Zeus (PPC405EP) board support
Signed-off-by: Stefan Roese <sr@denx.de>
2007-08-14 14:44:41 +02:00
Stefan Roese
273db7e1bd ppc4xx: Fix problem in PLL clock calculation
This patch was originall provided by David Mitchell <dmitchell@amcc.com>
and fixes a bug in the PLL clock calculation.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-08-13 09:05:33 +02:00
Wolfgang Denk
1636d1c852 Coding stylke cleanup; rebuild CHANGELOG 2007-06-22 23:59:00 +02:00
Grzegorz Bernacki
efa35cf12d ppc4xx: Clean up 440 exceptions handling
- Introduced dedicated switches for building 440 and 405 images required
  for 440-specific machine instructions like 'rfmci' etc.

- Exception vectors moved to the proper location (_start moved away from
  the critical exception handler space, which it occupied)

- CriticalInput now serviced (with default handler)

- MachineCheck properly serviced (added a dedicated handler and return
  subroutine)

- Overall cleanup of exceptions declared with STD_EXCEPTION macro (unused,
  unhandled and those not relevant for 4xx were eliminated)

- Eliminated Linux leftovers, removed dead code

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-15 11:19:28 +02:00
Stefan Roese
c440bfe6d6 ppc4xx: Add NAND booting support for AMCC Acadia (405EZ) eval board
This patch adds NAND booting support for the AMCC Acadia eval board.

Please make sure to configure jumper J7 to position 2-3 when booting
from NOR, and to position 1-2 when booting for NAND.

I also added a board command to configure the I2C bootstrap EEPROM
values. Right now only 267MHz is support for booting either via NOR
or NAND FLASH. Here the usage:

=> bootstrap 267 nor	;to configure the board for 267MHz NOR booting
=> bootstrap 267 nand	;to configure the board for 267MHz NNAND booting

Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-06 11:42:13 +02:00
Stefan Roese
9f0077abd6 ppc4xx: Use do { ... } while (0) for CPR & SDR access macros
Signed-off-by: Stefan Roese <sr@denx.de>
2007-05-22 12:48:09 +02:00
Stefan Roese
90e6f41cf0 ppc4xx: Add output for bootrom location to 405EZ ports
Now 405EZ ports also show upon bootup from which boot device
they are configured to boot:

U-Boot 1.2.0-gd3832e8f-dirty (Apr 18 2007 - 07:47:05)

CPU:   AMCC PowerPC 405EZ Rev. A at 199.999 MHz (PLB=133, OPB=66, EBC=66 MHz)
       Bootstrap Option E - Boot ROM Location EBC (32 bits)
       16 kB I-Cache 16 kB D-Cache
Board: Acadia - AMCC PPC405EZ Evaluation Board

Signed-off-by: Stefan Roese <sr@denx.de>
2007-04-18 12:05:59 +02:00
Stefan Roese
e01bd218b0 [PATCH] Add AMCC PPC405EZ support
This patch adds support for the new AMCC 405EZ PPC. It is in
preparation for the AMCC Acadia board support.

Please note that this Acadia/405EZ support is still in a beta stage.
Still lot's of cleanup needed but we need a preliminary release now.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-21 13:38:59 +01:00
Stefan Roese
4745acaa1a [PATCH] Add support for the AMCC Katmai (440SPe) eval board
Signed-off-by: Stefan Roese <sr@denx.de>
2007-02-20 10:57:08 +01:00
Heiko Schocher
ca43ba18e9 Added support for the SOLIDCARD III board from Eurodesign
Signed-off-by: Heiko Schocher <hs@denx.de>
2007-01-11 15:44:44 +01:00
wdenk
efe2a4d5cf Code cleanup. 2004-12-16 21:44:03 +00:00
stroese
44acc8d334 new 405ep defines added 2004-12-16 18:03:44 +00:00
wdenk
cea655a224 Add support for the second Ethernet interface for the 'PPChameleon' board. 2004-06-06 23:53:59 +00:00
stroese
e075fbe66c Updated for PPC405EP boards. 2003-12-09 14:59:11 +00:00
wdenk
8bde7f776c * Code cleanup:
- remove trailing white space, trailing empty lines, C++ comments, etc.
  - split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c)

* Patches by Kenneth Johansson, 25 Jun 2003:
  - major rework of command structure
    (work done mostly by Michal Cendrowski and Joakim Kristiansen)
2003-06-27 21:31:46 +00:00
stroese
b867d705b6 PPC405EP support added. 2003-05-23 11:18:02 +00:00
stroese
97a43d641d Added edge conditioning register (ecr) for PPC405GPr. 2003-03-20 15:27:41 +00:00
wdenk
0442ed869c Initial revision 2002-11-03 10:24:00 +00:00