Enable Atmel sama5d3xek boart spl boot support, which can load u-boot
from SD card with FAT file system.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
The MPDDRC supports different type of SDRAM
This patch add ddr2 initialization function
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Enable the PIO peripherals early than other peripherals.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
The offset of MULA field in PLLA register in sama5d3 is 18,
and the length only 7 bits.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
The PLLADIV2 bit is not defined in at91sam9261 SoC, so remove it.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
As the DBGU and PIT has its own ID on sama5d3 SoC, while not share
with SYS ID. So, correct them.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
The SPI section is already defined in this file (lines 268-288) so we can
remove the duplicate definitions. While at it, also fix one tiny whitespace
typo.
Signed-off-by: Luka Perkov <luka@openwrt.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
uDoo uses APX823-31W5 watchdog chip. Timeout is about 1.2 seconds.
To disabled watchdog during kernel boot, WDI pin of that chip needs to be
in "high impedance" state. I.mx6 gpio configuration does not contemplate
tristate, so pin is set as input in high impedance.
Signed-off-by: Giuseppe Pagano <giuseppe.pagano@seco.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
Add Ethernet and networking support on uDoo board (FEC +phy Micrel KSZ9031).
Ethernet speed is currently limited to 10/100Mbps.
Signed-off-by: Giuseppe Pagano <giuseppe.pagano@seco.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
Previous uDoo configuration adopts register settings for DDR3, clock, muxing,
etc. taken from Nitrogen6x. uDoo schematics is rather different from that board,
and it needs customized setting for most of the registers.
All this changes can be considered atomical since it is part of initial support
of the board.
Patch changes uDoo configuration files path to a specific one, and adopt
optimized value for every configured register.
Signed-off-by: Giuseppe Pagano <giuseppe.pagano@seco.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
CC: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
mx6sabre board has a m25p32 SPI NOR connected to ECSPI1 port.
Add support for it.
This patch allows the SPI NOR flash to be succesfully detected:
=> sf probe
SF: Detected M25P32 with page size 256 Bytes, erase size 64 KiB, total 4 MiB
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Currently HDMI splash screen is selected by default on mx6sabresd boards.
As LVDS is also enabled, this causes incorrect colors to be displayed im the
LVDS panel.
Fix this by selecting the LVDS panel as the default splash output and only keep
HDMI or LVDS turned on at the same time.
Acked-by: Liu Ying <Ying.Liu@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
There is no need to pass p->bus differently when the PMIC is connected via SPI
or via I2C.
Handle the both cases in the same way.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
On efikamx board the PMIC is connected via SPI interface, so it does not make
sense to pass I2C_PMIC into the pmic_init() interface.
Pass the SPI bus number via CONFIG_FSL_PMIC_BUS option instead.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
On mx31pdk board the PMIC is connected via SPI interface, so it does not make
sense to pass I2C_PMIC into the pmic_init() interface.
Pass the SPI bus number via CONFIG_FSL_PMIC_BUS option instead.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
On mx51evk board the PMIC is connected via SPI interface, so it does not make
sense to pass I2C_PMIC into the pmic_init() interface.
Pass the SPI bus number via CONFIG_FSL_PMIC_BUS option instead.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
OCOTP driver is currently selected via CONFIG_MXC_OCOTP option.
Remove the old OCOTP related options, as they are not used anymore.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Eric Nelson <eric.nelson@boundarydevices.com>
Whilst U-boot does not require this itself, Linux currently relies upon
it having been muxed and enabled by the bootloader. Thus in order to
preserve compatibility with current kernels before a fix is merged in
Linux we will enable the SERIRQ interrupt and mux it to its pin.
Without doing this current kernels will never receive serial port
interrupts and the end result is typically that userland appears to
hang.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
CONFIG_SYS_NS16550_CLK specifies the rate of the clock 16x the baud
rate. The SMSC FDC37M81x datasheet states that a divider of 1 results in
a UART at 115200 baud, thus the x16 clock rate is 115200 * 16.
Previously the divider was left at 0 which led to a rate of 38400 baud
regardless of CONFIG_BAUDRATE or the baudrate environment variable.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
The baudrate passed to Linux in the environment was hardcoded at 38400.
Instead pass the correct baudrate from global data, allowing Linux to
correctly inherit the baudrate used by U-boot when console setup is not
explicitly specified.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Add the default RCW(SerDes 0x66_0x16) and PBI configure file for
T2080QDS board, so we can use PBL tool to generate the ramboot
image to support boot from NAND/SPI/SD.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
The T2080QDS is a high-performance computing evaluation, development and
test platform supporting the T2080 QorIQ Power Architecture processor.
T2080QDS feature overview
Processor:
- T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
Memory:
- Single memory controller capable of supporting DDR3 and DDR3-LV devices
- Two DDR3 DIMMs up to 4GB, Dual rank @ 2133MT/s and ECC support
Ethernet interfaces:
- Two 1Gbps RGMII on-board ports
- Four 10Gbps XFI on-board cages
- 1Gbps/2.5Gbps SGMII Riser card
- 10Gbps XAUI Riser card
Accelerator:
- DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
SerDes:
- 16 lanes up to 10.3125GHz
- Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, XFI and XAUI
IFC:
- 128MB NOR Flash, 512MB NAND Flash, PromJet debug port and FPGA
eSPI:
- Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040)
USB:
- Two USB2.0 ports with internal PHY (one Type-A + one micro Type-AB)
PCIE:
- Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
SATA:
- Two SATA 2.0 ports on-board
SRIO:
- Two Serial RapidIO 2.0 ports up to 5 GHz
eSDHC:
- Supports SD/SDHC/SDXC/eMMC Card
I2C:
- Four I2C controllers.
UART:
- Dual 4-pins UART serial ports
System Logic:
- QIXIS-II FPGA system controll
Debug Features:
- Support Legacy, COP/JTAG, Aurora, Event and EVT
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
[York Sun: removed Makefile blank line at EOF,
fix conflicts with moving DDR driver]
Acked-by: York Sun <yorksun@freescale.com>
Add support for Freescale T2080/T2081 SoC.
T2080 includes the following functions and features:
- Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
- 2MB L2 cache and 512KB CoreNet platform cache (CPC)
- Hierarchical interconnect fabric
- One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
- 16 SerDes lanes up to 10.3125 GHz
- 8 mEMACs for network interfaces (four 1Gbps MACs and four 10Gbps/1Gbps MACs)
- High-speed peripheral interfaces
- Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
- Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
- Additional peripheral interfaces
- Two serial ATA (SATA 2.0) controllers
- Two high-speed USB 2.0 controllers with integrated PHY
- Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC)
- Enhanced serial peripheral interface (eSPI)
- Four I2C controllers
- Four 2-pin UARTs or two 4-pin UARTs
- Integrated Flash Controller supporting NAND and NOR flash
- Three eight-channel DMA engines
- Support for hardware virtualization and partitioning enforcement
- QorIQ Platform's Trust Architecture 2.0
Differences between T2080 and T2081:
Feature T2080 T2081
1G Ethernet numbers: 8 6
10G Ethernet numbers: 4 2
SerDes lanes: 16 8
Serial RapidIO,RMan: 2 no
SATA Controller: 2 no
Aurora: yes no
SoC Package: 896-pins 780-pins
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>
There are more than two 10GEC in single FMAN in some SoCs(e.g. T2080).
This patch adds support for 10GEC3 and 10GEC4.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Freescale IFC controller has been used for mpc8xxx. It will be used
for ARM-based SoC as well. This patch moves the driver to driver/misc
and fix the header file includes.
Signed-off-by: York Sun <yorksun@freescale.com>
The DRAM base has been zero for Power SoCs. It could be non-zero
for ARM SoCs. Use a macro instead of hard-coding to zero.
Signed-off-by: York Sun <yorksun@freescale.com>
Some DDR registers' fields have expanded to accommodate larger values.
These changes are backward compatible. Some fields are removed for newer
DDR controllers. Writing to those fields are safely ignored.
TIMING_CFG_2 register is fixed. Additive latency is added to RD_TO_PRE
automatically. It was a misunderstanding in commit c360ceac.
Signed-off-by: York Sun <yorksun@freescale.com>
Fix ccsr_ddr structure to avoid using typedef. Combine DDR2 and DDR3
structure for 83xx, 85xx and 86xx.
Signed-off-by: York Sun <yorksun@freescale.com>
Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs.
The similar DDR controllers will be used for ARM-based SoCs.
Signed-off-by: York Sun <yorksun@freescale.com>
The default partition table matches the .dts files for these boards in
Linux. This allows these partitions to be used by name with U-Boot's
"nand" command.
Signed-off-by: Zhao Qiang <B45475@freescale.com>
The offset of register address within GPIO module is just
CONFIG_SYS_MPC85xx_GPIO_ADDR. So, fix it. The following platforms
are confirmed: MPC8572, P1023, P1020, P1022, P2020, P4080,
P5020, P5040, T4240, B4860.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
The use of 'bool' data types in globally used header files cases build
errors like this:
In file included from arch/blackfin/include/asm/blackfin.h:13:0,
from include/common.h:92,
from cmd_test.c:17:
arch/blackfin/include/asm/blackfin_local.h:54:1: error: unknown type name 'bool'
Use plain 'int' instead to avoid such kind of trouble.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Some board have multiple configurations.
For example, the board "m54455evb" has many configurations:
M54455EVB, M54455EVB_a66, M54455EVB_i66, M54455EVB_intel, ...
When we modify board-related files, we need to test
all configurations based on such a board.
In such a case, the new option -b is useful.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
All objects under api/ and examples/api/ directories are selected
by CONFIG_API.
So we can move CONFIG_API switch to the top Makefile.
In order to use CONFIG_API, the definition of SUBDIR_EXAMPLES-y
must be moved after "sinlude $(obj)include/autoconf.mk".
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
The directory tools/ is always built before common/.
So when envcrc tool is necessary in common/Makefile,
it already exists.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
