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https://github.com/AsahiLinux/u-boot
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udoo: Add ethernet support (FEC + Micrel KSZ9031).
Add Ethernet and networking support on uDoo board (FEC +phy Micrel KSZ9031). Ethernet speed is currently limited to 10/100Mbps. Signed-off-by: Giuseppe Pagano <giuseppe.pagano@seco.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com> CC: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com>
This commit is contained in:
Giuseppe Pagano
Stefano Babic
parent
953ab736af
commit
078813d21d
3 changed files with 161 additions and 0 deletions
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@ -9,6 +9,7 @@
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#include <asm/arch/clock.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux.h>
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#include <malloc.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/errno.h>
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#include <asm/gpio.h>
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@ -18,6 +19,9 @@
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#include <asm/arch/crm_regs.h>
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#include <asm/io.h>
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#include <asm/arch/sys_proto.h>
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#include <micrel.h>
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#include <miiphy.h>
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#include <netdev.h>
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DECLARE_GLOBAL_DATA_PTR;
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@ -25,6 +29,9 @@ DECLARE_GLOBAL_DATA_PTR;
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
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#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
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PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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@ -58,6 +65,99 @@ static iomux_v3_cfg_t const wdog_pads[] = {
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MX6_PAD_EIM_D19__GPIO3_IO19,
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};
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int mx6_rgmii_rework(struct phy_device *phydev)
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{
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/*
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* Bug: Apparently uDoo does not works with Gigabit switches...
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* Limiting speed to 10/100Mbps, and setting master mode, seems to
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* be the only way to have a successfull PHY auto negotiation.
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* How to fix: Understand why Linux kernel do not have this issue.
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*/
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phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00);
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/* control data pad skew - devaddr = 0x02, register = 0x04 */
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ksz9031_phy_extended_write(phydev, 0x02,
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MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
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MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
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/* rx data pad skew - devaddr = 0x02, register = 0x05 */
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ksz9031_phy_extended_write(phydev, 0x02,
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MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
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MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
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/* tx data pad skew - devaddr = 0x02, register = 0x05 */
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ksz9031_phy_extended_write(phydev, 0x02,
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MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
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MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
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/* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
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ksz9031_phy_extended_write(phydev, 0x02,
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MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
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MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
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return 0;
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}
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static iomux_v3_cfg_t const enet_pads1[] = {
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MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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/* RGMII reset */
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MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* Ethernet power supply */
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MX6_PAD_EIM_EB3__GPIO2_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* pin 32 - 1 - (MODE0) all */
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MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* pin 31 - 1 - (MODE1) all */
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MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* pin 28 - 1 - (MODE2) all */
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MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* pin 27 - 1 - (MODE3) all */
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MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
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/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
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MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static iomux_v3_cfg_t const enet_pads2[] = {
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MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
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};
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static void setup_iomux_enet(void)
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{
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imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
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udelay(20);
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gpio_direction_output(IMX_GPIO_NR(2, 31), 1); /* Power supply on */
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gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* assert PHY rst */
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gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
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gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
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gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
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gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
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gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
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udelay(1000);
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gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* deassert PHY rst */
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/* Need 100ms delay to exit from reset. */
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udelay(1000 * 100);
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gpio_free(IMX_GPIO_NR(6, 24));
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gpio_free(IMX_GPIO_NR(6, 25));
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gpio_free(IMX_GPIO_NR(6, 27));
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gpio_free(IMX_GPIO_NR(6, 28));
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gpio_free(IMX_GPIO_NR(6, 29));
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imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
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}
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static void setup_iomux_uart(void)
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{
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imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
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@ -77,6 +177,37 @@ int board_mmc_getcd(struct mmc *mmc)
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return 1; /* Always present */
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}
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int board_eth_init(bd_t *bis)
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{
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uint32_t base = IMX_FEC_BASE;
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struct mii_dev *bus = NULL;
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struct phy_device *phydev = NULL;
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int ret;
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setup_iomux_enet();
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#ifdef CONFIG_FEC_MXC
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bus = fec_get_miibus(base, -1);
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if (!bus)
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return 0;
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/* scan phy 4,5,6,7 */
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phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
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if (!phydev) {
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free(bus);
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return 0;
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}
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printf("using phy at %d\n", phydev->addr);
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ret = fec_probe(bis, -1, base, bus, phydev);
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if (ret) {
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printf("FEC MXC: %s:failed\n", __func__);
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free(phydev);
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free(bus);
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}
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#endif
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return 0;
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}
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int board_mmc_init(bd_t *bis)
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{
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imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
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@ -94,6 +225,15 @@ int board_early_init_f(void)
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return 0;
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}
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int board_phy_config(struct phy_device *phydev)
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{
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mx6_rgmii_rework(phydev);
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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int board_init(void)
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{
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/* address of boot parameters */
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@ -34,6 +34,22 @@
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#define CONFIG_MXC_UART
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#define CONFIG_MXC_UART_BASE UART2_BASE
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/* Network support */
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_NET
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#define CONFIG_FEC_MXC
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#define CONFIG_MII
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#define IMX_FEC_BASE ENET_BASE_ADDR
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#define CONFIG_FEC_XCV_TYPE RGMII
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#define CONFIG_ETHPRIME "FEC"
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#define CONFIG_FEC_MXC_PHYADDR 6
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_MICREL
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#define CONFIG_PHY_MICREL_KSZ9031
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_CONS_INDEX 1
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@ -15,6 +15,11 @@
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#define MII_KSZ9031_MOD_DATA_POST_INC_RW 0x8000
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#define MII_KSZ9031_MOD_DATA_POST_INC_W 0xC000
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#define MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW 0x4
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#define MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW 0x5
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#define MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW 0x6
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#define MII_KSZ9031_EXT_RGMII_CLOCK_SKEW 0x8
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struct phy_device;
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int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val);
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int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum);
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