Commit graph

8538 commits

Author SHA1 Message Date
Priyanka Jain
7fb79e6552 armv8/ls2085aqds: enable 32KHz rtc output
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-09-01 21:37:42 -05:00
Tom Rini
b7e84c93c4 Merge branch 'master' of http://git.denx.de/u-boot-sunxi 2015-08-31 12:12:27 -04:00
Misha Komarovskiy
057d2f4973 exynos: Rise ARM voltage to 1.1V for chained bootloaders
If board uses downstream Chrome OS U-Boot as first stage
bootloader and upstream version is chained second stage,
1.1V is minimum voltage borderline.

Signed-off-by: Misha Komarovskiy <zombah@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-08-31 07:57:27 -06:00
Hans de Goede
3537a0e8ca sunxi: Fix MAINTAINERS board sorting
The boards are sorted by SoC, move the Mele_A1000G_quad entry to the list
of sun6i boards where it belongs.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-08-31 08:43:42 +02:00
Marcus Cooper
50222f3bab sunxi: Add support for the Olimex A20 EVB
Signed-off-by: Marcus Cooper <codekipper@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
2015-08-31 08:43:42 +02:00
Hans de Goede
4ddcf1df17 sunxi: Add inet98v_rev2 defconfig and dts file
The inet98v_rev2 is a pcb used in generic A13 based tablets. It features
volume buttons, a power barrel, micro-usb otg, headphone connector and
a power button.

The dts file is identical to the one submitted to the upstream kernel.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-08-31 08:43:42 +02:00
Hans de Goede
1f554906c3 sunxi: Add inet97fv2_defconfig
The inet97fv2 is a board found in the first generation of cheap allwinner
A10 based 7" tablets.

Note that this patch does not add a dts file as we already have one from
our dts syncs with the kernel.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-08-31 08:43:42 +02:00
Hans de Goede
e526861687 sunxi_nand_spl: Rename SPL_NAND_SUNXI to NAND_SUNXI
We eventually want to add full nand support, since it makes no sense
to build SPL with nand support and u-boot without, or the other way
around, a single option will suffice.

Renaming the Kconfig option now makes things easier when we add full
nand support in the future.

The "obj-$(CONFIG_NAND_SUNXI) += sunxi_nand_spl.o" is moved to an
"ifdef CONFIG_SPL_BUILD" block in the Makefile.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-08-31 08:43:42 +02:00
Hans de Goede
022a99d8b2 sunxi_nand_spl: Add support for sun4i and sun5i SoCs
Other then having a few less chip-select lines the nand controller
on sun4i, sun5i and sun7i is identical.

Note this patch also muxes GPC7 to the NAND on sun7i where as before
it was not muxed this way. GPC7 is a standard NAND pin, so it should
always be muxed to the NAND when in use.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-08-31 08:43:42 +02:00
Hans de Goede
31c21471de sunxi_nand_spl: Make sure the DMA controller is enabled
We use DMA for nand data transfers in the SPL, so make sure the DMA
controller is enabled.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-08-31 08:43:41 +02:00
Hans de Goede
f62bfa56da sunxi_nand_spl: Use SYS_NAND_SELF_INIT and only do nand init when necessary
Use SYS_NAND_SELF_INIT and only setup the pinmux and clocks when we are
actually using the nand.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-08-31 08:43:41 +02:00
Hans de Goede
8addd3ed7e sunxi: Drop LCD_MODE from A13-OLinuxIno defconfigs
With the unified / cleaned up default display output selection changes,
which were done as part of adding composite video out support, our
example LCD_MODE line in the A13-OLinuxIno defconfigs causes the display
code to setup a LCD console by default, rather then a VGA console.

Given that the LCD console is only useful for people who have hooked up
the exact lcd-panel from the config, while most people will not have any
lcd panel connected to these boards, this is not a good default.

Dropping the LCD_MODE line which was intended as an example fixes this,
instead add a link to the LCD_MODE help text pointing to
http://linux-sunxi.org/LCD which contains the removed and other example
modes.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-08-31 08:43:41 +02:00
Hans de Goede
f9a37289b8 sunxi: Add support for gt90h-v4 tablets
The gt90h is a pcb found in generic 9" tablets with an A23 soc, 1G RAM
and 8G nand, rtl8723as usb wifi, 1 micro usb port and 1 micro sd slot.

The pmic setup on this board is somewhat special, dcdc2 MUST be set
to 1.1V instead of the usual 1.2V otherwise the board is very unstable.
aldo1 is used to power the micro sd slot, dldo1 is used for wifi.

This commit adds a defconfig + dts (as submitted to the kernel) for
the gt90h-v4 pcb.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-08-31 08:43:41 +02:00
Hans de Goede
7a0bbe64d8 sunxi: axp221: Allow specifying dcdc2 voltage via Kconfig
Allow specifying the axp221 dcdc2 voltage via Kconfig, this is necessary
because on some boards the 1.2V default does not work reliable.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2015-08-31 08:43:41 +02:00
Kishon Vijay Abraham I
6f1af1e358 board: ti: invoke clock API to enable and disable clocks
invoke enable_usb_clocks during board_usb_init and disable_usb_clocks
during board_usb_exit to enable and disable clocks respectively.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-08-28 12:33:22 -04:00
Kishon Vijay Abraham I
7ba792c044 board: ti: OMAP5: added USB initializtion code
Implemented board_usb_init(), board_usb_cleanup() and
usb_gadget_handle_interrupts() in omap5 board file that
can be invoked by various gadget drivers.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-08-28 12:33:21 -04:00
Kishon Vijay Abraham I
7c379aaa03 board: ti: beagle_x15: added USB initializtion code
Implemented board_usb_init(), board_usb_cleanup() and
usb_gadget_handle_interrupts() in beagle_x15 board file that
can be invoked by various gadget drivers.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-08-28 12:33:20 -04:00
Kishon Vijay Abraham I
03c128c949 board: ti: remove duplicate initialization of vbus_id_status
vbus_id_status is initialized in board_usb_init. So remove it
while creating dwc3_device objects.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-08-28 12:33:20 -04:00
Andreas Bießmann
610751e94f at91sam9260ek: add missing files to MAINTAINERS
This fixes the following genboardscfg.py warnings:

---8<---
WARNING: no status for 'at91sam9g20ek_2mmc'
WARNING: no maintainers for 'at91sam9g20ek_2mmc'
--->8---

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-08-28 12:33:18 -04:00
Andreas Bießmann
7751604ca9 at91sam9rlek: add missing files to MAINTAINERS
This fixes following genboardscfg.py warning:

---8<---
WARNING: no status for 'at91sam9rlek_mmc'
WARNING: no maintainers for 'at91sam9rlek_mmc'
--->8---

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-08-28 12:33:18 -04:00
Stefan Roese
80999a5277 arm: spear: Fix booting - relocate vector table to 0 (low-vector)
Booting SPEAr600 eval board doesn't work with current mainline U-Boot. With
this patch the low-vector bit is left to '0'. Resulting in the common
relocation of the vectors to 0 (SDRAM) to work correctly.

Tested on the SPEAr600 EVB.

Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Vipin Kumar <vk.vipin@gmail.com>
2015-08-28 12:33:16 -04:00
Lokesh Vutla
76b3f195e9 ARM: k2l: Fix device speeds
ARM supported speeds and init value of core_pll for SDP1200
are programmed wrong as part for the device speed cleanups.
Fixing it here.
Thanks to "Vitaly Andrianov <vitalya@ti.com>" for bisecting this issue

Fixes: c37ed9f11b61 ("ARM: keystone2: Fix dev and arm speed detection")
Tested-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-08-28 12:33:16 -04:00
Lokesh Vutla
be8ce70c02 ARM: keystone2: Update README
Update README to include uart boot mode support and makefile
changes.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-08-28 12:33:15 -04:00
Lokesh Vutla
5f586e9fa1 ARM: keystone2: Rename u-boot-nand.gph to MLO
NAND boot mode, ROM expects an image with a gp header in the
beginning and an 8bytes filled with zeros at the end. The same is
true for SD boot on K2G platforms but the file name should be MLO.

Renaming u-boot-nand.gph to MLO, so that same image can be used for
NAND and SD boots. And also not including all the u-boot only images
under CONFIG_SPL_BUILD.

Reported-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2015-08-28 12:33:15 -04:00
Nishanth Menon
76cff2b108 ARM: DRA74-evm: Use SMA_1 spare register to workaround DP83865 phy on SR2.0
DP83865 ethernet phy used on DRA74x-evm is quirky and the datasheet
provided IODELAY values for standard RGMII phys do not work.

Silicon Revision(SR) 2.0 provides an alternative bit configuration
that allows us to do a "gross adjustment" to launch the data off a
different internal clock edge. Manual IO Delay overrides are still
necessary to fine tune the clock-to-data delays. This is a necessary
workaround for the quirky ethernet Phy we have on the platform.

NOTE: SMA registers are spare "kitchen sink" registers that does
contain bits for other workaround as necessary as well. Hence the
control for the same is introduced in a generic SoC specific, board
generic location.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-08-28 12:33:13 -04:00
Nishanth Menon
0358923409 ARM: DRA74-evm: Add iodelay values for SR2.0
Silicon revision 2.0 has new signal routing hence has an updated set of
iodelay parameters to be used. Update the configuration for the same.
Padmux remains the same.

Based on data from VayuES2_EVM_Base_Config-20150807.

NOTE: With respect to the RGMII values, the Manual IODelay values
are used for the fine adjusments needed to meet the tight RGMII
specification.

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2015-08-28 12:33:13 -04:00
Kun-Hua Huang
b3537c08e1 NDS32: Generic Board Support and Unsupport
Remove ag101 and ag102 support

Signed-off-by: Kun-Hua Huang <kunhua@andestech.com>
2015-08-28 11:46:35 -04:00
Kun-Hua Huang
2e88bb28d8 NDS32: Generic Board Support and Unsupport
Add nds32 ag101p generic board support.

Signed-off-by: Kun-Hua Huang <kunhua@andestech.com>
2015-08-28 11:46:35 -04:00
Bin Meng
4dd02a752c x86: crownbay: Enable on-board SMSC superio keyboard controller
So far we only enabled one legacy serial port on the SMSC LPC47m
superio chipset on Intel Crown Bay board. As the board also has
dual PS/2 ports routed out, enable the keyboard controller which
is i8042 compatible so that we can use PS/2 keyboard and mouse.

In order to make PS/2 keyboard work with the VGA console, remove
CONFIG_VGA_AS_SINGLE_DEVICE. To boot Linux kernel with PIC mode
using PIRQ routing table, adjust the mask in the device tree to
reserve irq12 which is used by PS/2 mouse.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-08-26 07:54:16 -07:00
Tom Rini
c851a2458f Merge git://git.denx.de/u-boot-socfpga
Conflicts:
	configs/socfpga_arria5_defconfig
	configs/socfpga_cyclone5_defconfig
	configs/socfpga_socrates_defconfig

Merged these by hand and re-ran savedefconfig on them.

Signed-off-by: Tom Rini <trini@konsulko.com>
2015-08-23 20:44:25 -04:00
Marek Vasut
29aa439759 arm: socfpga: Fix ArriaV SoCDK PLL config
Pull out the ArriaV SoCDK clock config from ancient Altera U-Boot
"rel_socfpga_v2013.01.01_15.05.01_pr" and implant those values into
mainline to get a booting ArriaV SoCDK.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-23 11:56:21 +02:00
Marek Vasut
d418301167 arm: socfpga: Fix MAINTAINERS entry for CV/AV SoCDK
Repair the maintainer entries so they match the current state of code.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-23 11:56:20 +02:00
Marek Vasut
cc9429a556 arm: socfpga: Make the pinmux table const u8
Now that we're actually converting the QTS-generated header files,
we can even adjust their data types. A good candidate for this is
the pinmux table, where each entry can have value in the range of
0..3, but each element is declared as unsigned long. By changing
the type to u8, we can save over 600 Bytes from the SPL, so do it.
This patch also constifies the array.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-23 11:56:20 +02:00
Marek Vasut
f6badb0d89 arm: socfpga: Switch to filtered QTS files
Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-23 11:56:20 +02:00
Marek Vasut
37b3a30ae6 arm: socfpga: Remove AV-specific parts from CV-SoCDK
Just remove the ArriaV specific parts from the CycloneV SoCDK board
and they are no longer needed now.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-23 11:56:20 +02:00
Marek Vasut
c68eea0492 arm: socfpga: Remove CV-specific parts from AV-SoCDK
Just remove the CycloneV specific parts from the ArriaV SoCDK board
and they are no longer needed now.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-23 11:56:20 +02:00
Marek Vasut
f089240128 arm: socfpga: Split Altera socfpga into AV and CV SoCDK
The board/altera/socfpga directory is not a generic SoCFPGA machine
anymore, but instead it represents the Altera SoCDK board. To make
matters more complicated, it represents both CycloneV and ArriaV
variant.

On the other hand, nowadays, the content of this board directory is
mostly comprised of QTS-generated header files, while all the generic
code is in arch/arm/mach-socfpga already.

Thus, this patch splits the board/altera/socfpga into a separate
board directory for ArriaV SoCDK and CycloneV SoCDK, so that each
can be populated with the correct QTS-generated header files for
that particular board.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-23 11:56:19 +02:00
Marek Vasut
ca62d2e1fc arm: socfpga: Move wrappers into platform directory
Move the wrappers for QTS-generated files into platform directory
out of the board directory. The trick here is to add -I to CFLAGS
such that it points to the board directory in source tree and thus
the qts/ directory there is still reachable.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-23 11:56:19 +02:00
Wu, Josh
89a3658ac0 ARM: at91: sama5d3xek: use a $dtb_name to load dtb
Since sama5d3xek boards has different type of dtb blobs, so we need to detect
the cpu type in runtime.

So we add a new variable $dtb_name. if $dtb_name is not defined, we just use
	at91-${board_name}.dtb

as the $dtb_name. Otherwise, we will just load the dtb with
	$dtb_name.

For sama5d3xek, we will detect cpu type and make up $dtb_name in
runtime.

Signed-off-by: Josh Wu <josh.wu@atmel.com>
2015-08-21 15:47:04 +02:00
Erik van Luijk
bfc37f3cb8 arm: at91: add support for mini-box picosam9g45 board
Bootlog:
U-Boot SPL 2015.10-rc1-00452-g96a7ed1 (Aug 17 2015 - 10:32:21)
mci: setting clock 258000 Hz, block size 512
mci: setting clock 258000 Hz, block size 512
mci: setting clock 258000 Hz, block size 512
mci: setting clock 33024000 Hz, block size 512
reading u-boot.img
reading u-boot.img

U-Boot 2015.10-rc1-00452-g96a7ed1 (Aug 17 2015 - 10:32:21 +0000)

CPU: AT91SAM9G45
Crystal frequency:       12 MHz
CPU clock        :      400 MHz
Master clock     :  133.333 MHz
       Watchdog enabled
DRAM:  256 MiB
WARNING: Caches not enabled
MMC:   mci: 0
mci: setting clock 260416 Hz, block size 512
mci: setting clock 260416 Hz, block size 512
mci: setting clock 260416 Hz, block size 512
mci: setting clock 33333333 Hz, block size 512
reading uboot.env
In:    serial
Out:   serial
Err:   serial
Net:   macb0
Error: macb0 address not set.

Hit any key to stop autoboot:  0
U-Boot>

Signed-off-by: Erik van Luijk <evanluijk@interact.nl>
[add 'picosam9g45_defconfig' to MAINTAINERS]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-08-21 15:47:04 +02:00
Erik van Luijk
c982f6b9bf arm: at91: pmc: replace the constant with a define in at91_pmc.h
To enable the clocks on the at91 boards a constant (0x4) is used.
This is replaced with a define in at91_pmc.h (1 <<  2).

Signed-off-by: Erik van Luijk <evanluijk@interact.nl>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-08-21 15:47:03 +02:00
Erik van Luijk
6560491fe5 arm: at91: at91sam9m10g45ek/corvus remove useless chip select 1 init
On these boards the DDR is connected to a dedicated controller and not
to chip select 1 of the EBI.

Signed-off-by: Erik van Luijk <evanluijk@interact.nl>
Tested-by: Erik van Luijk <evanluijk@interact.nl>
2015-08-21 15:47:03 +02:00
Erik van Luijk
0c01c3e876 arm: at91: mpddr: allow multiple DDR controllers
The mpddr.c depends on ATMEL_BASE_MPDDRC for the base address to configure the controller.
This cannot be used when there is more than one controller (i.e. AT91SAM9G45, AT91SAM9M10).

Signed-off-by: Erik van Luijk <evanluijk@interact.nl>
[remove 'new blank line at EOF']
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-08-21 15:47:02 +02:00
Masahiro Yamada
8d77576371 ARM: davinci: remove support for cam_enc_4xx
This has not been converted to Generic Board, so should be removed.
(See doc/README.generic-board for details.)

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Heiko Schocher <hs@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
2015-08-20 12:55:50 -04:00
Siva Durga Prasad Paladugu
16fa00a711 zynqmp: usb: Add usb dwc3 driver support for zynqmp
Added usb dwc3 driver support for zynqmp
this also supports the DFU and LTHOR to download
the linux images on to RAM and cen be booted from
those linux images.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-08-19 11:27:30 +02:00
Siva Durga Prasad Paladugu
84696ff57b board: Xilinx: zynqmp: Define checkboard() function
Define checkboard() function for zynqMP

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-08-19 11:26:59 +02:00
Masahiro Yamada
0f9258228e of: clean up OF_CONTROL ifdef conditionals
We have flipped CONFIG_SPL_DISABLE_OF_CONTROL.  We have cleansing
devices, $(SPL_) and CONFIG_IS_ENABLED(), so we are ready to clear
away the ugly logic in include/fdtdec.h:

 #ifdef CONFIG_OF_CONTROL
 # if defined(CONFIG_SPL_BUILD) && !defined(SPL_OF_CONTROL)
 #  define OF_CONTROL 0
 # else
 #  define OF_CONTROL 1
 # endif
 #else
 # define OF_CONTROL 0
 #endif

Now CONFIG_IS_ENABLED(OF_CONTROL) is the substitute.  It refers to
CONFIG_OF_CONTROL for U-boot proper and CONFIG_SPL_OF_CONTROL for
SPL.

Also, we no longer have to cancel CONFIG_OF_CONTROL in
include/config_uncmd_spl.h and scripts/Makefile.spl.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
2015-08-18 13:46:05 -04:00
Masahiro Yamada
d6c2ac5b75 spl: move SPL driver entries to driver/Makefile
Just preparing for upcoming cleaning.

The board-specific linker script  board/vpac270/u-boot-spl.lds
has been touched to avoid build error.  It does not change the
size of spl/u-boot-spl.bin for this board, so it should be OK.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-08-18 13:46:00 -04:00
Stefan Roese
ce2cb1d3ed arm: mvebu: db-88f6820-gp: Enable PCI support
This patch enabled the MVEBU PCIe support on the db-88f6820-gp A38x
eval board. It also enabled the Intel E1000 driver support and
adds the initialization of PCIe network controllers to the
board code.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Anton Schubert <anton.schubert@gmx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <eibach@gdsys.de>
2015-08-17 18:49:52 +02:00
Stefan Roese
41e705ac79 arm: mvebu: db-mv784mp-gp: Enable PCI support
This patch enabled the MVEBU PCIe support on the db-mv784mp-gp AXP
eval board. It also enabled the Intel E1000 driver support and
adds the initialization of PCIe network controllers to the
board code.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Anton Schubert <anton.schubert@gmx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-08-17 18:49:47 +02:00