On the MPC85xx platform if we have SATA its connected on SERDES.
Determing if SATA is enabled via sata_initialize should not be board
specific and thus we move it out of the MPC8536DS board code.
Additionally, now that we have is_serdes_configured() we can determine
if the given SATA port is enabled and error out if its not in the
driver.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The x86 architecture exclusively uses Port-Mapped I/O (inb/outb) to access
the 16550 UARTs. This patch mimics how Linux selects between Memory-Mapped
and Port-Mapped I/O. This allows x86 boards to use CONFIG_SERIAL_MUTLI and
drop the custom serial port driver
Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
In order to do this cleanly, the register accesses have to be converted to
a C struct (base pointer), so do that in the process.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
The RTC is part of the Freescale's PMIC controller.
Use general function to access to PMIC internal registers.
Signed-off-by: Stefano Babic <sbabic@denx.de>
Tested-by: Magnus Lilja <lilja.magnus@gmail.com>
The patch add supports for the Freescale's Power
Management Controller (known as Atlas) used together with i.MX31/51
processors. It was tested with a MC13783 (MX31) and
MC13892 (MX51).
Signed-off-by: Stefano Babic <sbabic@denx.de>
Added a new function kwgbe_write_hwaddr for programming egiga
controller's hardware address.
This function will be called for each egiga port being used
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
This driver supports the Altera triple speeds 10/100/1000 ethernet
mac.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
This patch ports the opencore 10/100 ethernet mac driver ethoc.c
from linux kernel to u-boot.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
SMSC911x chips have alignment function to allow frame payload data
(which comes after 14-bytes ethernet header) to be aligned at some
boundary when reading it from fifo (usually - 4 bytes boundary).
This is done by inserting fake zeros bytes BEFORE actual frame data when
reading from SMSC's fifo.
This function controlled by RX_CFG register. There are bits that
represents amount of fake bytes to be inserted.
Linux uses alignment of 4 bytes. Ethernet frame header is 14 bytes long,
so we need to add 2 fake bytes to get payload data aligned at 4-bytes
boundary.
Linux driver does this by adding IP_ALIGNMENT constant (defined at
skb.h) when calculating fifo data length. All network subsystem of Linux
uses this constant too when calculating different offsets.
But u-boot does not use any packet data alignment, so we don't need to
add anything when calculating fifo data length.
Moreover, driver zeros the RX_CFG register just one line up, so chip
does not insert any fake data at the beginig. So calculated data length
is always bigger by 1 word.
It seems that at almost every packet read we get an underflow condition
at fifo and possible corruption of data. Especially at continuous
transfers, such as tftp.
Just after removing this magic addition, I've got tftp transfer speed as
it aught to be at 100Mbps. It was really slow before.
It seems that fifo underflow occurs only when using byte packing on
32-bit blackfin bus (may be because of very small delay between reads).
Signed-off-by: Valentin Yakovenkov <yakovenkov@niistt.ru>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Cosmetic changes: Few comments updated
Functionality: Rx packet frame size is programming should
be done when port is in disabled state. this is corrected
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Fix MX27 FEC logic to check validity of the MAC address in fuse.
Only null (empty fuse) or invalid MAC address was retrieved from mx27 fuses before this change.
Signed-off-by: Eric Jarrige <jorasse@armadeus.org>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
When gracefully stopping the controller, the driver was continuing if
*either* RX or TX had stopped. We need to wait for both, or the
controller could get into an invalid state.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
The current dm9000x driver accesses its memory mapped registers directly
instead of using the standard I/O accessors. This can cause problems on
Blackfin systems as the accesses can get out of order. So convert the
direct volatile dereferences to use the normal in/out macros.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
This saves the autonegotation delay when not using ethernet in U-Boot
Signed-off-by: Detlev Zundel <dzu@denx.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Avoid using the internal eeprom on MX25 like MX51 already does.
Signed-off-by: John Rigby <jcrigby@gmail.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
This patch enabled support for having PHYs on bitBang MII and uec MII
operating at the same time. Modeled after the MPC8360ADS implementation.
Added the ability to specify which ethernet interfaces have bitbang SMI
on the board header file.
Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
For code archeologists, this is a nice example of copy and paste history.
Signed-off-by: Detlev Zundel <dzu@denx.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
This patch fixes following build warnings for kirkwood_egiga.c
kirkwood_egiga.c: In function "kwgbe_init":
kirkwood_egiga.c:448: warning: dereferencing type-punned pointer will break strict-aliasing rules
kirkwood_egiga.c: In function "kwgbe_recv":
kirkwood_egiga.c:609: warning: dereferencing type-punned pointer will break strict-aliasing rules
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Because of s5pc1xx gpio is same as s5p seires SoC,
move gpio functions to drvier/gpio/
and modify structure's name from s5pc1xx_ to s5p_.
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Because of other s5p series SoC will use these serial functions,
modify function's name and structure's name.
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
For P1022 SATA host controller, the data snoop bit of DW3 in PRDT
is moved to bit28.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
After power on, the SATA host controller of P1022 Rev1 is configured
in legacy mode instead of the expected enterprise mode.
Software needs to clear bit[28] of HControl register to change to
enterprise mode after bringing the host offline.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This patch adds an option to bypass output waiting when there
is no jtag connection. This allows the jtag uart work similar
to a serial uart, ie, boot even without connection.
This option is enabled with CONFIG_ALTERA_JTAG_UART_BYPASS
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
Subsequent patch extends mpc512x serial driver to support
multiple PSC ports. The driver will provide an uninit()
function to stop the serial controller and to disable the
controller's clock. Adding uninit() entry to struct serial_device
allows disabling the serial controller after usage of
a stdio serial device.
This patch adds uninit() entry to the struct serial_device
and fixes initialization of this structure in the code
accordingly.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
On some Freescale SoC Internal DMA of eSDHC controller has bug.
So PIO Mode has been introduced to do data transfer using CPU.
Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com>
As discussed on the list, move "arch/ppc" to "arch/powerpc" to
better match the Linux directory structure.
Please note that this patch also changes the "ppc" target in
MAKEALL to "powerpc" to match this new infrastructure. But "ppc"
is kept as an alias for now, to not break compatibility with
scripts using this name.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
Acked-by: Detlev Zundel <dzu@denx.de>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Cc: Peter Tyser <ptyser@xes-inc.com>
Cc: Anatolij Gustschin <agust@denx.de>
This patch adds a callpoint in i2c_init that allows board specific
i2c board initialization (typically for i2c bus reset) that is called
after i2c_init operations, allowing the i2c_board_late_init function
to use the pre-configured i2c bus speed and slave address.
The appropriate include/asm-$ARCH directory should already by symlinked
to include/asm so using the whole "asm-$ARCH" path is unnecessary.
This change should also allow us to move the include/asm-$ARCH
directories into their appropriate lib/$ARCH/ directories.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Add NEC EHCI controller to the list of the supported devices.
Signed-off-by: Sergei Shtylyov <sshtylyov@mvista.com>
drivers/usb/host/ehci-pci.c | 1 +
1 file changed, 1 insertion(+)
Commit b416191a14 (Fix EHCI port reset.) didn't
move the code that checked for successful clearing of the port reset bit from
ehci_submit_root(), relying on wait_ms() call instead. The mentioned code also
erroneously reported port reset state when the reset was already completed.
Signed-off-by: Sergei Shtylyov <sshtylyov@mvista.com>
USB devices on the 2nd port are not detected and I get the following message:
The request port(1) is not configured
That's with default CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS value of 2. 'req->index'
is 1-based, so the comparison in ehci_submit_root() can't be correct.
Signed-off-by: Sergei Shtylyov <sshtylyov@mvista.com>
On little endian machines, EHCI root hub's USB revision is reported as 0.2 --
cpu_to_le16() was missed in the initializer for the 'bcdUSB' descriptor field.
The same should be done for the 'bcdDevice' field.
Signed-off-by: Sergei Shtylyov <sshtylyov@mvista.com>
Fixes this warning:
ati_radeon_fb.c: In function 'radeon_probe':
ati_radeon_fb.c:598: warning: format '%x' expects type 'unsigned int',
but argument 2 has type 'void *'
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Use pci_bus_to_virt() to convert the bus address from the BARs to
virtual address' to eliminate the direct mapping requirement.
Rename variables to better match usage (_phys -> _bus or no-suffix)
This fixes the mpc8572ds CONFIG_PHYS_64BIT mode failure:
"videoboot: Video ROM failed to map!"
Tested on mpc8572ds with and without CONFIG_PHYS_64BIT.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Console was being switched to video even if emulator fails and
causing this hang:
Scanning PCI bus 04
04 00 1095 3132 0104 00
PCIE3 on bus 03 - 04
Video: ATI Radeon video card (1002, 5b60) found @(2:0:0)
videoboot: Booting PCI video card bus 2, function 0, device 0
videoboot: Video ROM failed to map!
640x480x8 31kHz 59Hz
radeonfb: FIFO Timeout !
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Tested-by: Anatolij Gustschin <agust@denx.de>
This patch adds reset_timer() before the flash status check
waiting loop.
Since the timer is basically running asynchronous to the cfi
code, it is possible to call get_timer(0), then only a few
_SYSCLK_ cycles later an interrupt is generated. This causes
timeout even though much less time has elapsed. So the timer
period registers should be reset before get_timer(0) is
called.
There is similar usage in nand_base.c.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Stefan Roese <sr@denx.de>
There are various locations that we have chip specific info:
* Makefile for which ddr code to build
* Added P1012/P1013/P1021/P1022 to cpu_type_list and SVR list
* Added number of LAWs for P1012/P1013/P1021/P1022
* Set CONFIG_MAX_CPUS to 2 for P1021/P1022
* PCI port config
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
If the PCI controller wasn't configured or enabled delete from the
device tree (include its alias).
For the case that we didn't even configure u-boot with knowledge of
the controller we can use the fact that the pci_controller pointer
is NULL to delete the node in the device tree. We determine that
a controller was not setup (because of HW config) based on the fact
that cfg_addr wasn't setup.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
When we set the read or write watermark in WML we should maintain the
rest of the register as is, rather than using some hard coded value.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
To support multiple block read command we must set abort or use auto
CMD12. If we booted from eSDHC controller neither of these are used
and thus we need to reset the controller to allow multiple block read
to function.
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We need to stop the clocks on 83xx/85xx as well as imx. No need to make
this code conditional to just imx.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Acked-by: Stefano Babic <sbabic@denx.de>
This patch moves the PPC4xx specific I2C device driver into the I2C
drivers directory. All 4xx config headers are updated to include this
driver.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch is part of migrating the AT91 support towards
using C struct for all SOC access.
It removes one more CONFIG_AT91_LEGACY warning.
at91_pmc.h needs cleanup after migration of the drivers
has been done.
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
The outx/writex macros were using writex(addr, val) rather than
the standard writex(val, addr), resulting in incompatibilty with
architecture independent components. This change set uses standard
parameter order.
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
The standard Altera UART & JTAG UART as well as the OpenCores
YANU driver are now in individual files in drivers/serial
rather than a single file uner cpu/nios2.
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
Only fill the device enetaddr with the contents of the eeprom,
do not program it in MAC address registers
Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Ben Warren <biggerbadderben@gmail.com>
This patch adds status polling method to offer an alternative to
data toggle method for amd flash chips.
This patch is needed for nios2 cfi flash interface, where the bus
controller performs 4 bytes read cycles for a single byte read
instruction. The data toggle method can not detect chip busy
status correctly. So we have to poll DQ7, which will be inverted
when the chip is busy.
This feature is enabled with the config def,
CONFIG_SYS_CFI_FLASH_STATUS_POLL
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Stefan Roese <sr@denx.de>
With old configuration it could happen tout=0 if CONFIG_SYS_HZ<1000.
Signed-off-by: Renato Andreola <renato.andreola@imagos.it>
Signed-off-by: Alessandro Rubini <rubini@gnudd.com>
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Stefan Roese <sr@denx.de>
Using seperate function calls for each bit-bang of slave serial
load can be painfully slow. This patch adds the possibility to
supply a block write function that loads the complete block of
data in one call (like it can already be done with Altera FPGAs).
On an MCF5373L (240 MHz) loading an XC3S4000 this reduces the load
time from around 15 seconds to around 3 seconds
Signed-off-by: Wolfgang Wegner <w.wegner at astro-kom.de>
This is a patch to use the hardware ECC controller of
the AT91SAM9260 for the AT91 nand. Taken from the kernel 2.6.33.
Signed-off-by: Nikolay Petukhov <Nikolay.Petukhov@gmail.com>
If a splashscreen is used the console scrolling used the
scroll size as needed when a logo was displayed. This
patch sets the scroll size to the whole screen if
a splashscreen is shown.
Signed-off-by: Matthias Weisser <matthias.weisser@graf-syteco.de>
I executed 'find . -name "*.[chS]" -perm 755 -exec chmod 644 {} \;'
Signed-off-by: Thomas Weber <swirl@gmx.li>
Add some more: neither Makefile nor config.mk need execute permissions.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Some registers of the mxcmmc driver were accessed using
16 bit accessor functions, because only the LSB is
significant. This is not needed and generates
warnings.
Signed-off-by: Stefano Babic <sbabic@denx.de>
If a splashscreen is used the console scrolling used the
scroll size as needed when a logo was displayed. This
patch sets the scroll size to the whole screen if
a splashscreen is shown.
Signed-off-by: Matthias Weisser <matthias.weisser@graf-syteco.de>
This code has compile problems and the company does not even exist any
more. So we take the liberty to drop support for it.
Signed-off-by: Detlev Zundel <dzu@denx.de>
CC: Wolfgang Denk <wd@denx.de>
CC: Ben Warren <biggerbadderben@gmail.com>
There is be a path through mmc_read in drivers/mmc/mmc.c where
malloc'd memory is not freed before exiting mmc_read: it occurs if
mmc_set_blocklen() returns a non-zero value.
Reported-by: Quentin Armitage <Quentin@Armitage.org.uk>
Signed-off-by: Wolfgang Denk <wd@denx.de>
general cleanup
move clock init to cpu_eth_init in cpu/arm926ejs/mx27/generic.c
make MX27 specific phy init conditional on CONFIG_MX27
replace call to imx_get_ahbclk with one to imx_get_fecclk
and define imx_get_fecclk in include/asm-arm/arch-mx27/clock.h
Signed-off-by: John Rigby <jcrigby@gmail.com>
CC: Ben Warren <biggerbadderben@gmail.com>
CC: Fred Fan <fanyefeng@gmail.com>
CC: Tom <Tom.Rix@windriver.com>
ARM926EJS core with MX31 peripherals.
Signed-off-by: John Rigby <jcrigby@gmail.com>
Earlier Version Signed-off-by: Wolfgang Denk <wd@denx.de>
CC: Fred Fan <fanyefeng@gmail.com>
CC: Tom <Tom.Rix@windriver.com>
The esdhc controller in the mx51 processor is quite
the same as the one in some powerpc processors
(MPC83xx, MPC85xx). This patches adapts the driver
to support the arm mx51.
Signed-off-by: Stefano Babic <sbabic@denx.de>
Most controllers can check if there is a card in the slot.
However, they require pins that could be not available because
required by other functions and the detection of a card must
be performed in another way. This patch adds a weak function
that a board can implement to add its internal custom way
to check the presence of a MMC/SD card.
Signed-off-by: Stefano Babic <sbabic@denx.de>
Most cards do not answer if some reserved bits
in the ocr are set. However, some controllers
can set bit 7 (reserved for low voltages), but
how to manage low voltages SD card is not yet
specified.
Signed-off-by: Stefano Babic <sbabic@denx.de>
For platforms with flash below ram addresses, the current check to
activate monitor protection is wrong/insufficient. This patch fixes
CONFIG_MONITOR_IS_IN_RAM for these systems by adding a check for
this configuration.
Signed-off-by: Wolfgang Wegner <w.wegner@astro-kom.de>
Signed-off-by: Stefan Roese <sr@denx.de>
* add's a warning to all files, which need update to new SoC access
* convert common files in cpu/../at91 and a lot of drivers to use
c stucture SoC access
Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
* add a real AT91 GPIO driver instead of header inline code
* resolve the mixing of port and pins
* change board config files to use new driver
* add macros to gpio to realize backward compatibility
Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
Commit f9b6a1575d, "i.MX31: fix SPI
driver for shorter than 32 bit" broke 32 bit transfers. This patch
makes single 32 bit transfer work again.
Transfer lengths that are known not to work will abort and print
an error message.
Tested on i.MX31 Litekit and i.MX31 PDK using 32 bit transfers to
the MC13783/ATLAS chip (using the 'date' command).
Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
This adds a driver for the SPI controller found on davinci
based SoCs from Texas Instruments.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
The patch add support for the Freescale mx51 processor
to the FEC ethernet driver.
Signed-off-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Although the datasheet mentions seperate smi registers for each
port, using Port 1 smi register to access ethernet phys does not
work. Hence only Port 0 smi register should be used to access all
devices connected to the smi bus. This behavior is consistant with
the mv643xx driver in the linux kernel.
Signed-off-by: Siddarth Gore <gores@marvell.com>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
ns16550 busyloops waiting for incoming byte causing watchdog to reboot
while waiting for a key press. A call to WATCHDOG_RESET in NS16550_getc
loop fixes it.
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
The conversion from offsets to C structs lost a little padding in the DMA
register map. Accessing endpoints other than ep0 with DMA would fail as
the addresses wouldn't be adjusted correctly.
Signed-off-by: Cliff Cai <cliff.cai@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
eraseregions numblocks was sometimes one less than actual, possibly producing
erase regions with zero blocks. As MTD code touches eraseregions only if
numeraseregions is greater that zero, allocate eraseregions only for non
uniform erase size flash.
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Signed-off-by: Stefan Roese <sr@denx.de>
* add's at91_emac (AT91RM9200) network driver (NET_MULTI api)
* enable driver with CONFIG_DRIVER_AT91EMAC
* generic PHY initialization
* modify AT91RM9200 boards to use NET_MULTI driver
* the drivers has been tested with LXT971 Phy and DM9161 Phy at
MII and RMII interface
Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
There's no sensible reason to unite speed and interface type into
one variable. So split this variable enet_interface into two
vars: enet_interface_type, which hold the interface type and speed.
Also: add the possibility for switching between 10 and 100 MBit
interfaces on the fly, when running in FAST_ETH mode.
Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
The EMAC IP on DM365, DM646x and DA830 is slightly different
from that on DM644x. This change updates the DaVinci EMAC driver
so that EMAC becomes operational on SOCs with EMAC v2.
Signed-off-by: Nick Thompson <nick.thompson@ge.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Enabling CONFIG_CMD_MII in AVR32 boards was not possible due to
compile errors.
This patch fixes miiphy_read and miiphy_write functions and
registers them properly.
Signed-off-by: Semih Hazar <semih.hazar@indefia.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
The TSEC_FIBER flag should be set when a PHY is operating with an
external fiber interface. Currently it is only used to notify a user
that the PHY is operating in fiber mode.
A short description was also added to the other TSEC flag defines so
that it is clear how they differ from one another.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
The BCM5482 PHY supports both copper and fiber as an ethernet medium.
By enabling its copper/fiber mode auto-detection feature it can
dynamically determine if it should be configured for copper or fiber.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
This is generally good practice and saves ~150 bytes.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
- Remove unnecessary printing "Enet starting in <speed>/<duplex>"
This same information is already printed during normal ethernet
operation in the form "Speed: 1000, full duplex".
- Add a check for link before determining link speed and duplex
If there is no link, speed/duplex don't matter. This also removes
the annoying and unneeded "Auto-neg error, defaulting to 10BT/HD"
message that occurs when no link is detected.
- Whitespace and line > 80 characters cleanup
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
In SGMII mode the link between a processor's internal TBI PHY and an
external PHY should always be 1000Mbps, full duplex. Also, the SGMII
interface between an internal TBI PHY and external PHY does not
support in-band auto-negotation.
Previously, when configured for SGMII mode a TBI PHY would attempt to
restart auto-negotation during initializtion. This auto-negotation
between a TBI PHY and external PHY would fail and result in unusable
ethernet operation.
Forcing the TBI PHY and and external PHY to link at 1000Mbps full duplex
in SGMII mode resolves this issue of auto-negotation failing.
Note that 10Mbps and 100Mbps operation is still possible on the external
side of the external PHY even when SGMII is operating at 1000Mbps.
The SGMII interface still operates at 1000Mbps, but each byte of data
is repeated 100 or 10 times for 10/100Mbps and the external PHY handles
converting this data stream into proper 10/100Mbps signalling.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
This patch turns off MAC address mismatch warning when
optional eeprom programmed with MAC address is not available.
In that case, smc911x's MAC address register has its default
value ff:ff:ff:ff:ff:ff and it's not a valid address. This
makes eth_initialize() show the warning which has no
meaningful information while environment variable ethaddr
overrides the address read from the register. If there's no
eeprom and the value of MAC address register is not valid
after initialization, dev->enetaddr had better not be updated
and maintain its initial value 00:00:00:00:00:00, which I
think is what eth_initialize() expects. This is not a bug fix.
Even without this patch, the driver works fine. It's just for
enhancing the way of displaying messages.
Signed-off-by: Seunghyeon Rhee <seunghyeon@lpmtec.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
This adds support for the CLCD logic cell. It accepts precompiled
register values for specific configuration through a board-supplied
data structure. It is used by the Nomadik nhk8815, added by a later
patch in this series.
Signed-off-by: Alessandro Rubini <rubini@unipv.it>
Acked-by: Andrea Gallo <andrea.gallo@stericsson.com>
Add support for version 1.1 of the nfc nand flash
controller which is on the i.mx25 soc.
Signed-off-by: John Rigby <jcrigby@gmail.com>
CC: Scott Wood <scottwood@freescale.com>
SPEAr SoCs contain a synopsys usb device controller.
USB Device IP can work in 2 modes
- DMA mode
- Slave mode
The driver adds support only for slave mode operation of usb
device IP. This driver is used along with standard USBTTY
driver to obtain a tty interface over USB on the host
Signed-off-by: Vipin <vipin.kumar@st.com>
SPEAr SoCs contain an FSMC controller which can be used to interface
with a range of memories eg. NAND, SRAM, NOR.
Currently, this driver supports interfacing FSMC with NAND memories
Signed-off-by: Vipin <vipin.kumar@st.com>
SPEAr SoCs contain a serial memory interface controller. This
controller is used to interface with spi based memories.
This patch adds the driver for this IP.
Signed-off-by: Vipin <vipin.kumar@st.com>
These are few files directly imported from Linux kernel source.
Those are not modifyed at all ar per strategy.
These files contains source with GPLv2 only
whereas u-boot expects GPLv2 or latter
These files are updated for the same from prior permission from original writes
Acked-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
The list of 4xx SoCs that should send type 1 PCI transactions
is not defined correctly. As a result PCI-PCI bridges and devices
behind them are not identified. The following 4xx variants should
send type 1 transactions: 440GX, 440GP, 440SP, 440SPE, 460EX and 460GT.
Signed-off-by: Felix Radensky <felix@embedded-sol.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Import the large page oob layout from Linux mxc_nand.c driver.
The CONFIG_SYS_NAND_LARGEPAGE option is used to activate
the large page oob layout. Run time detection is not supported
as this moment.
This has been tested on the i.MX31 PDK board with a large
page NAND device.
Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
When referring to PCIe and USB 'endpoint' is the standard naming
convention.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Remy Bohmer <linux@bohmer.net>
If the requested clock cannot be exactly obtained, round it up so that we
err on the side of slightly slower rather than slightly faster.
Signed-off-by: Cliff Cai <cliff.cai@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Some SPI devices like to see high idle values rather than low.
Signed-off-by: Cliff Cai <cliff.cai@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
For MUSB devices that do not support multipoint (hubs), we have to emulate
a root hub so that we can support core operations like resetting ports.
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Cliff Cai <cliff.cai@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
In USB ehci driver, the port reset is not terminated. EHCI spec says "A host
controller must terminate the reset and stabilize the state of the port within
2 milliseconds". Without termination, a port stays at reset state. This is
observed on ppc4xx(sequoia) boards.
Signed-off-by: Chris Zhang <chris@seamicro.com>
This patch fixes this warning during compile:
omap3.c: In function 'musb_platform_init':
omap3.c:126: warning: label 'end' defined but not used
Problem reported by: Dirk Behme[dirk.behme@googlemail.com]
Signed-off-by: Sanjeev Premi <premi@ti.com>
The RX Control/Status register has bits that we want to preserve, so don't
just write out a single bit. Preserve the others bits in the process.
The original code posted to the u-boot list had this behavior, but looks
like it was lost somewhere along the way to merging.
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Cliff Cai <cliff.cai@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Remy Bohmer <linux@bohmer.net>
The multipoint handling under MUSB is optional, and some parts (like the
Blackfin processor) do not implement support for it.
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Cliff Cai <cliff.cai@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Remy Bohmer <linux@bohmer.net>
The dynamic FIFO handling under MUSB is optional, and some parts (like
the Blackfin processor) do not implement support for it.
Due to this, the FIFO reading/writing steps need special handling, so
mark the common versions weak so drivers can override.
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Cliff Cai <cliff.cai@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Remy Bohmer <linux@bohmer.net>
Introduces various optimisations that approximately triple the
read data rate from NAND when run on da830evm.
Most of these optimisations depend on the endianess of the machine
and most of them are very similar to optimisations already present
in the Linux Kernel.
Signed-off-by: Nick Thompson <nick.thompson@ge.com>
All users of is_fsl_pci_agent have been converted to fsl_is_pci_agent
that uses the standard PCI programming model to determine host vs
agent/end-point.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Moved the mdio regs out of the tsec structure,and
provided different offsets for tsec base and mdio
base so that provision for etsec2.0 can be provided.
This patch helps in providing the support for etsec2.0
In etsec2.0, the MDIO register space and the etsec reg
space are different.
Also, moved the TSEC_BASE_ADDR and MDIO_BASE_ADDR definitons into
platform specific files.
Signed-off-by: Sandeep Gopalpet <sandeep.kumar@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Davinci: NAND enable ECC even when not in NAND boot mode
On Davinci platforms, the default NAND device is enabled (for ECC)
in low level boot code when NAND boot mode is used. If booting in
another mode, NAND ECC is not enabled. The driver should make
sure ECC is enabled regardless of boot mode if NAND is configured
in U-Boot.
Signed-off-by: Nick Thompson <nick.thompson@ge.com>
Davinci: Configurable NAND chip selects
Add a CONFIG_SYS_NAND_CS setting to all davinci configs and
use it to setup the NAND controller in the davinci_nand
mtd driver.
Signed-off-by: Nick Thompson <nick.thompson@gefanuc.com>
Not all boards have both LEDs hooked, so enabling both on
boards with single LED will just waste power. Make it
possible to choose LEDs by adding argument to
twl4030_led_init().
Using this turn on only LEDB for pandora, leave both LEDs
on for all other boards, as it was before this patch.
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Prototype for gunzip/zunzip was only in lib_generic/gunzip.c and thus
repeated in every file using it. This patch moves the prototypes to
common.h and removes all prototypes distributed anywhere else.
Signed-off-by: Wolfgang Wegner <w.wegner@astro-kom.de>
OMAP3EVM uses ISP1504 phy and so twl4030 related init is not required.
Submitted-by: Ajay Kumar Gupta <ajay.gupta@ti.com>
Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
This change adds the usb device support for musb.
Omap3 platform support added at the same level as davinci.
The interface for usbtty to use the musb device support was added.
Verified on omap3 beagle, zoom1 and zoom2.
Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
The twl4030 provides a PHY device for connecting a link device,
like musb, to physical connection.
This change adds the twl4030 usb registers and functions for
initializing the PHY as required by omap3.
Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
The header files usb.h and usbdescriptors.h have the same nameed
structure definitions for
usb_config_descriptor
usb_interface_descriptor
usb_endpoint_descriptor
usb_device_descriptor
usb_string_descriptor
These are out right duplicates in usb.h
usb_device_descriptor
usb_string_descriptor
This one has extra unused elements
usb_endpoint_descriptor
unsigned char bRefresh
unsigned char bSynchAddress;
These in usb.h have extra elements at the end of the usb 2.0
specified descriptor and are used.
usb_config_descriptor
usb_interface_descriptor
The change is to consolidate the definition of the descriptors
to usbdescriptors.h. The dublicates in usb.h are removed.
The extra element structure will have their name shorted by
removing the '_descriptor' suffix.
So
usb_config_descriptor -> usb_config
usb_interface_descriptor -> usb_interface
For these, the common descriptor elements are accessed now
by an element 'desc'.
As an example
- if (iface->bInterfaceClass != USB_CLASS_HUB)
+ if (iface->desc.bInterfaceClass != USB_CLASS_HUB)
This has been compile tested on MAKEALL arm, ppc and mips.
Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
make -C drivers/bios_emulator/
make[2]: Entering directory
`drivers/bios_emulator'
In file included from atibios.c:49:
biosemui.h:47:21: error: biosemu.h: No such file or directory
...
x86emu/decode.c:40:28: error: x86emu/x86emui.h: No such file or directory
...
Due to lack of proper CPPFLAGS being passed to .depend generation rule
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
commit 60f61e6d76 breaks compile with gcc by introducing __func__
instead of constant string "func" in the macro call but missed to change the macro.
Signed-off-by: Thomas Weber <weber@corscience.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
fec_init() will only allocate fec->base_ptr if it is non-NULL. But
the cleanup routine on error will free the pointer without setting
it to NULL. This means that a later call to fec_init() would result
in using an invalid pointer.
Signed-off-by: John Ogness <john.ogness@linutronix.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
This chip is equipped for example on the esd PMC-ETH2-GB board. So let's
add it to the list of supported chips to the e1000 driver.
Signed-off-by: Reinhard Arlt <reinhard.arlt@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Make the lan91c96 driver capable of CONFIG_NET_MULTI
to be clean for the new arch, add a a lil detect function
Most of the formatting change was done to keep checkpatch
silent, but a few functions and #if 0ed code which
does not make sense for NET_MULTI have been removed
Now, use the lan91c96_initialize() function to init the driver
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Currently, the last block of NAND devices can't be accessed. This patch
fixes this issue by correcting the boundary checking (off-by-one error).
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Wolfgang Denk <wd@denx.de>
There is more and more usage of printing 64bit values,
so enable this feature generally, and delete the
CONFIG_SYS_64BIT_VSPRINTF and CONFIG_SYS_64BIT_STRTOUL
defines.
Signed-off-by: Heiko Schocher <hs@denx.de>
Depending on offset, flash size and the number of bad blocks,
get_len_incl_bad may return a too small value which may lead to:
1) If there are no bad blocks, nand_{read,write}_skip_bad chooses the
bad block aware read/write code. This may hurt performance, but does
not have any adverse effects.
2) If there are bad blocks, the nand_{read,write}_skip_bad may choose
the bad block unaware read/write code (if len_incl_bad == *length)
which leads to corrupted data.
Signed-off-by: Daniel Hobi <daniel.hobi@schmid-telecom.ch>
This patch adds a unified s3c24x0 cpu header file that selects the header
file for the specific s3c24x0 cpu from the SOC and CPU configs defined in
board config file. This removes the current chain of s3c24-type #ifdef's
from the s3c24x0 code.
Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Because of Frame error, Parity error and Overrun error are occured only receive
operation, need to masking when error checking.
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch moves the s3c24x0 header files from include/ to
include/asm-arm/arch-s3c24x0/.
checkpatch.pl showed 2 errors and 3 warnings. The 2 errors were both due
to a non-UTF8 character in David M?ller's name:
ERROR: Invalid UTF-8, patch and commit message should be encoded in UTF-8
#489: FILE: include/asm-arm/arch-s3c24x0/s3c2410.h:3:
+ * David M?ller ELSOFT AG Switzerland. d.mueller@elsoft.ch
As David's name correctly contains a non-UTF8 character I haven't fixed
these errors.
The 3 warnings were all because of the use of 'volatile' in s3c24x0.h:
WARNING: Use of volatile is usually wrong: see Documentation/volatile-considered-harmful.txt
#673: FILE: include/asm-arm/arch-s3c24x0/s3c24x0.h:35:
+typedef volatile u8 S3C24X0_REG8;
+typedef volatile u16 S3C24X0_REG16;
+typedef volatile u32 S3C24X0_REG32;
I'll fix these errors in another patch.
Tested by running MAKEALL for ARM8 targets and ensuring there were no new
errors or warnings.
Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch adds support for NAND devices with a page size of
4K in the DaVinci NAND driver. The layout matches the layout that TI uses
for 4K page size NAND devices in the kernel NAND driver.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This patch add nand_read_buf() for S3C2410 NAND SPL.
In nand_spl/nand_boot.c, nand_boot() will check nand->select_chip,
so nand->select_chip should also be initialized.
Signed-off-by: Hui.Tang <zetalabs@gmail.com>
This patch updates a check condition in the NAND driver.
The check condition is similat to what is in linux/next.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Add support to use second and third I2C bus, too.
Bus 0 is still the default, but by calling i2c_set_bus_num(1/2) before doing
I2C accesses, code can switch to bus 1 and 2, too. Don't forget to switch
back afterwards, then.
Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
This patch adds support for Flex-OneNAND devices.
Signed-off-by: Rohit Hagargundgi <h.rohit@samsung.com>
Signed-off-by: Amul Kumar Saha <amul.saha@samsung.com>
The commit 66372fe2 manually relocated the bbt pattern pointer,
which can be removed by using full relocation.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
The syndrome based page read/write routines store ECC, and possibly other
"OOB" data, right after each chunk of ECC'd data. With ECC chunk size of
512 bytes and a large page (2KiB) NAND, the layout is:
data-0 OOB-0 data-1 OOB-1 data-2 OOB-2 data-3 OOB-3 OOB-leftover
Where OOBx is (prepad, ECC, postpad). However, the current "raw" routines
use a traditional layout -- data OOB, disregarding the prepad and postpad
values -- so when they're used with that type of ECC hardware, those calls
mix up the data and OOB. Which means, in particular, that bad block
tables won't be found on startup, with data corruption and related chaos
ensuing.
The current syndrome-based drivers in mainline all seem to use one chunk
per page; presumably they haven't noticed such bugs.
Fix this, by adding read/write page_raw_syndrome() routines as siblings of
the existing non-raw routines; "raw" just means to bypass the ECC
computations, not change data and OOB layout.
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
When computing oobavail from the list of free areas in the OOB,
don't assume there will always be an unused slot at the end.
This syncs up with the kernel NAND driver.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
The patch updates the check condition for determining
whether the ECC corrections has failed.
This makes it similar to what is in the kernel NAND driver.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This was originally part of Thomas Gleixner's patch for
adding support for 4KiB pages.
This is not part of the U-Boot NAND driver so updating the
driver with this to sync up with the kernel NAND driver.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This patch updates the "chip_shift" calculation in the
NAND driver. This is being done to sync up the NAND driver with
the kernel NAND driver.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This patch adds support for NANDs greater than 2 GB.
Patch is based on the MTD NAND driver in the kernel.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Make smc911x_initialize return -1 on error and number of interfaces
detected otherwise.
Signed-off-by: Mike Rapoport <mike@compulab.co.il>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Sometimes, inside NetLoop, eth_halt() is called before eth_init() has
been called. This is harmless except for free() calls to pointers
which have not been allocated yet.
This patch initializes those pointers to NULL and allocates them only
the first time. This way we can get rid of free calls in halt callback.
This has been tested in i.MX27 Litekit board and eldk-4.2 toolchains.
Signed-off-by: Javier Martin <javier.martin@vista-silicon.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
This patch fixes erroneous access to the ethernet PHY which broke the driver.
1. Selector field in the auto-negotiation register must be 0x00001 for
using 802.3, not 0x00000 which is reseved.
2. Access to the PHY address specified by CONFIG_FEC_MXC_PHYADDR, not
0x0 fixed address.
This has been tested in i.MX27 Litekit board and eldk-4.2 toolchains.
Now using proper defines for auto-negotiation register.
Signed-off-by: Javier Martin <javier.martin@vista-silicon.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
This patch fixes the following warnings:
Configuring for xaeniax board...
smc91111_eeprom.c: In function 'print_macaddr':
smc91111_eeprom.c:278: warning: suggest parentheses around + or - in operand of &
smc91111_eeprom.c:281: warning: suggest parentheses around + or - in operand of &
...
Configuring for xsengine board...
smc91111_eeprom.c: In function 'print_macaddr':
smc91111_eeprom.c:278: warning: suggest parentheses around + or - inside shift
smc91111_eeprom.c:281: warning: suggest parentheses around + or - inside shift
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
The following error was seen on impa7 board, due to its use of a 32-bit bus
on CS8900.
cs8900.c:137:37: error: macro "get_reg_init_bus" passed 2 arguments, but takes just 1
This patch gives the macro the correct number of arguments
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Ensure all CS8900 data structures are assigned before accessing device
Signed-off-by: Hui.Tang <zetalabs@gmail.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
commit 70ed869e broke fsl pcie end-point initialization.
Returning 0 is not correct. The function must return the first free
bus number for the next controller.
fsl_pci_init() must still be called and a bus allocated even if the
controller is an end-point.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Acked-by: Vivek Mahajan <vivek.mahajan@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This reverts commit 70ed869ea5.
There isn't any need to modify the API for fsl_pci_init_port to pass the
status of host/agent(end-point) status. We can determine that
internally to fsl_pci_init_port. Revert the patch that makes the API
change.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
In 16 bpp mode, the new IPEK01 board only requires swapping of D16 words
for D32 accesses due to the diffferent connecting to the GDC bus. This
patch introduces the configuration option VIDEO_FB_16BPP_WORD_SWAP,
which should be set for all board using the mb862xx in 16 bpp mode. For
the IPEK01, VIDEO_FB_16BPP_PIXEL_SWAP should not be set.
Signed-off-by: Wolfgang Grandegger <wg@denx.de>
The new IPEK01 board can use the 32 bpp mode for the Lime graphics
controller. For this mode, video accelaration does not work. This patch
makes the accelaration configurable via CONFIG_VIDEO_MB862xx_ACCEL,
which is enabled for the lwmon5 and the socrates board for backward
compatibility.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Wolfgang Grandegger <wg@denx.de>
To avoid board-specific code accessing the mb862xx registers directly,
the public function mb862xx_probe() has been introduced. Furthermore,
the "Change of Clock Frequency" and "Set Memory I/F Mode" registers
are now defined by CONFIG_SYS_MB862xx_CCF and CONFIG_SYS_MB862xx__MMR,
respectively. The BSPs for the socrates and lwmon5 boards have been
adapted accordingly.
Signed-off-by: Wolfgang Grandegger <wg@denx.de>
The current transfer code relies on ctrlc() to abort transfers, but this
requires user interactivity. Naturalize the process with a timeout.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Proper behavior is to pull MAC address from NVRAM in the initialization() an
stuff it in dev->address, then program the device from dev->address in
the init() function.
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Currently the CFI driver issues both AMD and Intel reset commands.
This is because the driver doesn't know yet which chips are connected.
This dual reset seems to cause problems with the M29W128G chips as
reported by Richard Retanubun. This patch now introduces a weak default
function for the CFI reset command, still with both resets. This can
be overridden by a board specific version if necessary.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Richard Retanubun <RichardRetanubun@ruggedcom.com>
Add missing newline.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Luigi Mantellini <luigi.mantellini@idf-hit.com>
Cc: Ben Warren <biggerbadderben@gmail.com>
Setup QE pin multiplexing for USB function, configure needed BCSRs
and add some fdt fixups.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Originally written by Jason Jin and Mingkai Hu for mpc8536.
When QorIQ based board is configured as a PCIe agent, then unlock/enable
inbound PCI configuration cycles and init a 4K inbound memory window;
so that a PCIe host can access the PCIe agents SDRAM at address 0x0
* Supported in fsl_pci_init_port() after adding pcie_ep as a param
* Revamped copyright in drivers/pci/fsl_pci_init.c
* Mods in 85xx based board specific pci init after this change
Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Some of the new spi flash files were missing explicit license lines.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
CC: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Move the test up in the function to not hang on systems without ethernet.
Signed-off-by: Steve Sakoman <sakoman@gmail.com>
Acked-by: Ben Warren <biggerbadderben@gmail.com>
fix the following compile warnings
warning: dereferencing type-punned pointer will break strict-aliasing rules
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch re-formats the arm920t s3c24x0 nand driver in preparation for changes
to add support for the Embest SBC2440-II Board.
The changes are as follows:
- re-indent the code using Lindent
- make sure register layouts are defined using a C struct
- replace the upper-case typedef'ed C struct names with lower case
non-typedef'ed ones
- make sure registers are accessed using the proper accessor functions
- run checkpatch.pl and fix any error reports
It assumes the following patch has been applied first:
- [U-Boot][PATCH-ARM] CONFIG_SYS_HZ fix for ARM902T S3C24X0 Boards, 05/09/2009
- patches 1/4, 2/4 and 3/4 of this series
Tested on an Embest SBC2440-II Board with local u-boot patches as I don't have
any s3c2400 or s3c2410 boards but need this patch applying before I can submit
patches for the SBC2440-II Board. Also, temporarily modified sbc2410x, smdk2400,
smdk2410 and trab configs to use the mtd nand driver (which isn't used by any
board at the moment), ran MAKEALL for all ARM9 targets and no new warnings or
errors were found.
Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch re-formats the arm920t s3c24x0 driver files, excluding the nand
driver, in preparation for changes to add support for the Embest SBC2440-II Board.
The changes are as follows:
- re-indent the code using Lindent
- make sure register layouts are defined using a C struct
- replace the upper-case typedef'ed C struct names with lower case
non-typedef'ed ones
- make sure registers are accessed using the proper accessor functions
- run checkpatch.pl and fix any error reports
It assumes the following patch has been applied first:
- [U-Boot][PATCH-ARM] CONFIG_SYS_HZ fix for ARM902T S3C24X0 Boards, 05/09/2009
- patches 1/4 and 2/4 of this series
Tested on an Embest SBC2440-II Board with local u-boot patches as I don't have
any s3c2400 or s3c2410 boards but need this patch applying before I can submit
patches for the SBC2440-II Board. Also, temporarily modified sbc2410x, smdk2400,
smdk2410 and trab configs to use the mtd nand driver (which isn't used by any
board at the moment), ran MAKEALL for all ARM9 targets and no new warnings or
errors were found.
Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch includes the serial driver for s5pc1xx.
s5pc1xx uart driver needs own register setting and clock configuration.
So, need to special driver.
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch includes the onenand driver for s5pc100
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Refactor the smc911x driver to allow for detecting when the chip is missing.
I.e. the detect_chip() function is called earlier and will abort gracefully
when the Chip ID read returns all 1's.
Signed-off-by: Olof Johansson <olof@lixom.net>
Acked-by: Dirk Behme <dirk.behme@googlemail.com>
Acked-by: Ben Warren <biggerbadderben@gmail.com>
Forcing the tables into got2 caused extra relocation when using -mrelocatable.
This patch requires any board defining CONFIG_BIOSEMU to use -mrelocatable.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Acked-by: Jin Zhengxiong <Jason.Jin@freescale.com>
This feature is useful when your board uses different mii buses for different
phys and all (or a part) of these buses are implemented via bit-banging mode.
The driver requires that the following macros should be defined into the board
configuration file:
CONFIG_BITBANGMII - Enable the miiphybb driver
CONFIG_BITBANGMII_MULTI - Enable the multi bus support
If the CONFIG_BITBANGMII_MULTI is not defined, the board's config file needs
to define at least the following macros:
MII_INIT - Generic code to enable the MII bus (optional)
MDIO_DECLARE - Declaration needed to access to the MDIO pin (optional)
MDIO_ACTIVE - Activate the MDIO pin as out pin
MDIO_TRISTATE - Activate the MDIO pin as input/tristate pin
MDIO_READ - Read the MDIO pin
MDIO(v) - Write v on the MDIO pin
MDC_DECLARE - Declaration needed to access to the MDC pin (optional)
MDC(v) - Write v on the MDC pin
The previous macros make the driver compatible with the previous version
(that didn't support the multi-bus).
When the CONFIG_BITBANGMII_MULTI is also defined, the board code needs to fill
the bb_miiphy_buses[] array with a record for each required bus and declare
the bb_miiphy_buses_num variable with the number of mii buses.
The record (struct bb_miiphy_bus) has the following fields/callbacks (see
miiphy.h for details):
char name[] - The symbolic name that must be equal to the MII bus
registered name
int (*init)() - Initialization function called at startup time (just
before the Ethernet initialization)
int (*mdio_active)() - Activate the MDIO pin as output
int (*mdio_tristate)() - Activate the MDIO pin as input/tristate pin
int (*set_mdio)() - Write the MDIO pin
int (*get_mdio)() - Read the MDIO pin
int (*set_mdc)() - Write the MDC pin
int (*delay)() - Delay function
void *priv - Private data used by board specific code
The board code will look like:
struct bb_miiphy_bus bb_miiphy_buses[] = {
{ .name = miibus#1, .init = b1_init, .mdio_active = b1_mdio_active, ... },
{ .name = miibus#2, .init = b2_init, .mdio_active = b2_mdio_active, ... },
...
int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
sizeof(bb_miiphy_buses[0]);
Signed-off-by: Luigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Modify all existing *.c files to use the new register names
as seen in the AMCC manuals.
Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org>
Signed-off-by: Stefan Roese <sr@denx.de>
if link up detection code is disabled through config option, it gives build warning.
This patch fixes the same
Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
