mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-29 08:01:08 +00:00
Merge branch 'next' of git://git.denx.de/u-boot-video into next
This commit is contained in:
Wolfgang Denk
commit
d793b6bb1e
7 changed files with 76 additions and 55 deletions
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@ -532,13 +532,6 @@ unsigned int board_video_init (void)
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udelay(500);
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gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1);
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/* Lime memory clock adjusted to 100MHz */
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out_be32((void *)CONFIG_SYS_LIME_SDRAM_CLOCK, CONFIG_SYS_LIME_CLOCK_100MHZ);
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/* Wait untill time expired. Because of requirements in lime manual */
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udelay(300);
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/* Write lime controller memory parameters */
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out_be32((void *)CONFIG_SYS_LIME_MMR, CONFIG_SYS_LIME_MMR_VALUE);
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mb862xx.winSizeX = 640;
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mb862xx.winSizeY = 480;
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mb862xx.gdfBytesPP = 2;
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@ -268,17 +268,6 @@ ft_board_setup(void *blob, bd_t *bd)
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}
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#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
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#define CONFIG_SYS_LIME_SRST ((CONFIG_SYS_LIME_BASE) + 0x01FC002C)
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#define CONFIG_SYS_LIME_CCF ((CONFIG_SYS_LIME_BASE) + 0x01FC0038)
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#define CONFIG_SYS_LIME_MMR ((CONFIG_SYS_LIME_BASE) + 0x01FCFFFC)
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/* Lime clock frequency */
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#define CONFIG_SYS_LIME_CLK_100MHZ 0x00000
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#define CONFIG_SYS_LIME_CLK_133MHZ 0x10000
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/* SDRAM parameter */
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#define CONFIG_SYS_LIME_MMR_VALUE 0x4157BA63
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#define DISPLAY_WIDTH 800
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#define DISPLAY_HEIGHT 480
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#define DEFAULT_BRIGHTNESS 25
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#define BACKLIGHT_ENABLE (1 << 31)
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@ -308,14 +297,12 @@ const gdc_regs *board_get_regs (void)
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return init_regs;
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}
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#define CONFIG_SYS_LIME_CID ((CONFIG_SYS_LIME_BASE) + 0x01FC00F0)
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#define CONFIG_SYS_LIME_REV ((CONFIG_SYS_LIME_BASE) + 0x01FF8084)
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int lime_probe(void)
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{
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volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
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uint cfg_br2;
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uint cfg_or2;
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uint reg;
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int type;
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cfg_br2 = memctl->br2;
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cfg_or2 = memctl->or2;
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@ -325,21 +312,15 @@ int lime_probe(void)
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memctl->or2 = 0xfc000410;
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memctl->br2 = (CONFIG_SYS_LIME_BASE) | 0x00001901;
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/* Try to access GDC ID/Revision registers */
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reg = in_be32((void *)CONFIG_SYS_LIME_CID);
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reg = in_be32((void *)CONFIG_SYS_LIME_CID);
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if (reg == 0x303) {
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reg = in_be32((void *)CONFIG_SYS_LIME_REV);
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reg = in_be32((void *)CONFIG_SYS_LIME_REV);
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reg = ((reg & ~0xff) == 0x20050100) ? 1 : 0;
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} else
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reg = 0;
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/* Get controller type */
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type = mb862xx_probe(CONFIG_SYS_LIME_BASE);
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/* Restore previous CS2 configuration */
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memctl->br2 = 0;
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memctl->or2 = cfg_or2;
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memctl->br2 = cfg_br2;
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return reg;
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return (type == MB862XX_TYPE_LIME) ? 1 : 0;
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}
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/* Returns Lime base address */
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@ -348,21 +329,8 @@ unsigned int board_video_init (void)
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if (!lime_probe())
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return 0;
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/*
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* Reset Lime controller
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*/
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out_be32((void *)CONFIG_SYS_LIME_SRST, 0x1);
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udelay(200);
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/* Set Lime clock to 133MHz */
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out_be32((void *)CONFIG_SYS_LIME_CCF, CONFIG_SYS_LIME_CLK_133MHZ);
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/* Delay required */
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udelay(300);
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/* Set memory parameters */
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out_be32((void *)CONFIG_SYS_LIME_MMR, CONFIG_SYS_LIME_MMR_VALUE);
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mb862xx.winSizeX = DISPLAY_WIDTH;
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mb862xx.winSizeY = DISPLAY_HEIGHT;
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mb862xx.winSizeX = 800;
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mb862xx.winSizeY = 480;
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mb862xx.gdfIndex = GDF_15BIT_555RGB;
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mb862xx.gdfBytesPP = 2;
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@ -146,9 +146,11 @@ CONFIG_VIDEO_HW_CURSOR: - Uses the hardware cursor capability of the
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#ifdef CONFIG_VIDEO_CORALP
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#define VIDEO_FB_LITTLE_ENDIAN
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#endif
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#ifdef CONFIG_VIDEO_MB862xx_ACCEL
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#define VIDEO_HW_RECTFILL
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#define VIDEO_HW_BITBLT
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#endif
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#endif
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/*****************************************************************************/
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/* Include video_fb.h after definitions of VIDEO_HW_RECTFILL etc */
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@ -319,7 +321,7 @@ void console_cursor (int state);
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#else
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#define SWAP16(x) (x)
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#define SWAP32(x) (x)
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#if defined(VIDEO_FB_16BPP_PIXEL_SWAP)
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#if defined(VIDEO_FB_16BPP_WORD_SWAP)
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#define SHORTSWAP32(x) ( ((x) >> 16) | ((x) << 16) )
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#else
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#define SHORTSWAP32(x) (x)
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@ -89,6 +89,7 @@ unsigned int fr_div[] = { 0x00000f00, 0x00000900, 0x00000500 };
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(GC_DISP_BASE | GC_L0PAL0) + \
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((idx) << 2)), (val))
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#if defined(CONFIG_VIDEO_MB862xx_ACCEL)
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static void gdc_sw_reset (void)
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{
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GraphicDevice *dev = &mb862xx;
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@ -129,6 +130,7 @@ static void de_wait_slots (int slots)
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break;
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}
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}
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#endif
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#if !defined(CONFIG_VIDEO_CORALP)
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static void board_disp_init (void)
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@ -144,11 +146,13 @@ static void board_disp_init (void)
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#endif
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/*
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* Init drawing engine
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* Init drawing engine if accel enabled.
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* Also clears visible framebuffer.
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*/
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static void de_init (void)
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{
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GraphicDevice *dev = &mb862xx;
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#if defined(CONFIG_VIDEO_MB862xx_ACCEL)
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int cf = (dev->gdfBytesPP == 1) ? 0x0000 : 0x8000;
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dev->dprBase = dev->frameAdrs + GC_DRAW_BASE;
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@ -174,6 +178,14 @@ static void de_init (void)
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DE_WR_FIFO (dev->winSizeY << 16 | dev->winSizeX);
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/* sync with SW access to framebuffer */
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de_wait ();
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#else
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unsigned int i, *p;
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i = dev->winSizeX * dev->winSizeY;
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p = (unsigned int *)dev->frameAdrs;
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while (i--)
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*p++ = 0;
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#endif
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}
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#if defined(CONFIG_VIDEO_CORALP)
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@ -340,6 +352,30 @@ unsigned int card_init (void)
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}
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#endif
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#if !defined(CONFIG_VIDEO_CORALP)
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int mb862xx_probe(unsigned int addr)
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{
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GraphicDevice *dev = &mb862xx;
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unsigned int reg;
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dev->frameAdrs = addr;
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dev->dprBase = dev->frameAdrs + GC_DRAW_BASE;
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/* Try to access GDC ID/Revision registers */
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reg = HOST_RD_REG (GC_CID);
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reg = HOST_RD_REG (GC_CID);
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if (reg == 0x303) {
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reg = DE_RD_REG(GC_REV);
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reg = DE_RD_REG(GC_REV);
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if ((reg & ~0xff) == 0x20050100)
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return MB862XX_TYPE_LIME;
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}
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return 0;
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}
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#endif
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void *video_hw_init (void)
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{
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GraphicDevice *dev = &mb862xx;
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@ -359,8 +395,16 @@ void *video_hw_init (void)
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if ((dev->frameAdrs = board_video_init ()) == 0) {
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puts ("Controller not found!\n");
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return NULL;
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} else
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} else {
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puts ("Lime\n");
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/* Set Change of Clock Frequency Register */
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HOST_WR_REG (GC_CCF, CONFIG_SYS_MB862xx_CCF);
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/* Delay required */
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udelay(300);
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/* Set Memory I/F Mode Register) */
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HOST_WR_REG (GC_MMR, CONFIG_SYS_MB862xx_MMR);
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}
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#endif
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de_init ();
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@ -389,6 +433,7 @@ void video_set_lut (unsigned int index, unsigned char r,
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L0PAL_WR_REG (index, (r << 16) | (g << 8) | (b));
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}
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#if defined(CONFIG_VIDEO_MB862xx_ACCEL)
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/*
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* Drawing engine Fill and BitBlt screen region
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*/
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@ -430,3 +475,4 @@ void video_hw_bitblt (unsigned int bpp, unsigned int src_x,
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DE_WR_FIFO ((height << 16) | width);
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de_wait (); /* sync */
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}
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#endif
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@ -344,10 +344,12 @@
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/* Video console */
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#define CONFIG_VIDEO
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#define CONFIG_VIDEO_MB862xx
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#define CONFIG_VIDEO_MB862xx_ACCEL
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#define CONFIG_CFB_CONSOLE
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_CONSOLE_EXTRA_INFO
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#define VIDEO_FB_16BPP_PIXEL_SWAP
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#define VIDEO_FB_16BPP_WORD_SWAP
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#define CONFIG_VGA_AS_SINGLE_DEVICE
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#define CONFIG_VIDEO_SW_CURSOR
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@ -495,8 +497,6 @@
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/*-----------------------------------------------------------------------
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* Graphics (Fujitsu Lime)
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*----------------------------------------------------------------------*/
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/* SDRAM Clock frequency adjustment register */
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#define CONFIG_SYS_LIME_SDRAM_CLOCK 0xC1FC0038
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/* Lime Clock frequency is to set 100MHz */
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#define CONFIG_SYS_LIME_CLOCK_100MHZ 0x00000
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#if 0
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@ -504,15 +504,15 @@
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#define CONFIG_SYS_LIME_CLOCK_133MHZ 0x10000
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#endif
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/* SDRAM Parameter register */
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#define CONFIG_SYS_LIME_MMR 0xC1FCFFFC
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/* SDRAM parameter value; was 0x414FB7F2, caused several vertical bars
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and pixel flare on display when 133MHz was configured. According to
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SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed Grade */
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#ifdef CONFIG_SYS_LIME_CLOCK_133MHZ
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#define CONFIG_SYS_LIME_MMR_VALUE 0x414FB7F3
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#define CONFIG_SYS_MB862xx_MMR 0x414FB7F3
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#define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_133MHZ
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#else
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#define CONFIG_SYS_LIME_MMR_VALUE 0x414FB7F2
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#define CONFIG_SYS_MB862xx_MMR 0x414FB7F2
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#define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_100MHZ
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#endif
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/*-----------------------------------------------------------------------
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@ -198,11 +198,13 @@
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#define CONFIG_VIDEO
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#define CONFIG_VIDEO_MB862xx
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#define CONFIG_VIDEO_MB862xx_ACCEL
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#define CONFIG_CFB_CONSOLE
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_VIDEO_BMP_LOGO
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#define CONFIG_CONSOLE_EXTRA_INFO
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#define VIDEO_FB_16BPP_PIXEL_SWAP
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#define VIDEO_FB_16BPP_WORD_SWAP
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#define CONFIG_VGA_AS_SINGLE_DEVICE
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV
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#define CONFIG_VIDEO_SW_CURSOR
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@ -210,6 +212,11 @@
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#define CONFIG_VIDEO_BMP_GZIP
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#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */
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/* SDRAM Clock frequency, 100MHz (0x0000) or 133MHz (0x10000) */
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#define CONFIG_SYS_MB862xx_CCF 0x10000
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/* SDRAM parameter */
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#define CONFIG_SYS_MB862xx_MMR 0x4157BA63
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/* Serial Port */
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#define CONFIG_CONS_INDEX 1
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@ -32,6 +32,8 @@
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#define PCI_DEVICE_ID_CORAL_P 0x2019
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#define PCI_DEVICE_ID_CORAL_PA 0x201E
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#define MB862XX_TYPE_LIME 0x1
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#define GC_HOST_BASE 0x01fc0000
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#define GC_DISP_BASE 0x01fd0000
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#define GC_DRAW_BASE 0x01ff0000
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@ -39,6 +41,7 @@
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/* Host interface registers */
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#define GC_SRST 0x0000002c
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#define GC_CCF 0x00000038
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#define GC_CID 0x000000f0
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#define GC_MMR 0x0000fffc
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/*
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@ -99,6 +102,7 @@
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#define GC_FC 0x00000480
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#define GC_BC 0x00000484
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#define GC_FIFO 0x000004a0
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#define GC_REV 0x00008084
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#define GC_GEO_FIFO 0x00008400
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typedef struct {
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@ -106,6 +110,7 @@ typedef struct {
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unsigned int value;
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} gdc_regs;
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int mb862xx_probe(unsigned int addr);
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const gdc_regs *board_get_regs (void);
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unsigned int board_video_init (void);
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void board_backlight_switch(int);
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