* 'master' of git://git.denx.de/u-boot-usb:
usb_storage: fix ehci driver max transfer size
smsc95xx: align buffers to cache line size
ehci-hcd: change debug() to printf() in case of errors
usb: check return value of submit_{control, bulk}_msg
usb: pass cache-aligned buffer to usb_get_descriptor()
ehci-hcd: fix external buffer cache handling
ehci-hcd.c, musb_core, usb.h: Add USB_DMA_MINALIGN define for cache alignment
ehci-hcd: program asynclistaddr before every transfer
common.h: Introduce DEFINE_CACHE_ALIGN_BUFFER
ehci-omap: Do not call dcache_off from omap_ehci_hcd_init
Signed-off-by: Wolfgang Denk <wd@denx.de>
* 'sf' of git://git.denx.de/u-boot-blackfin:
sf: spansion: inline useless id defines
sf: drop unused/duplicate command defines
Signed-off-by: Wolfgang Denk <wd@denx.de>
In an effort to unify the spi flash drivers further, drop all the
unused and/or duplicate command defines.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Now that common code doesn't declare these as volatile, we don't need to
either anymore. This fixes the build warning:
bfin_mac.c: In function 'bfin_EMAC_recv':
bfin_mac.c:193:23: warning: assignment discards qualifiers from pointer target type
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Buffer coming from upper layers should be cacheline aligned/padded
to perform safe cache operations. For now we don't do bounce
buffering so getting unaligned buffer is an upper layer error.
We can't check if the buffer is properly padded with current
interface so just assume it is (consider changing with in the
future). The following changes are done:
1. Remove useless length alignment check. We get actual transfer
length not the size of the underlying buffer so it's perfectly
valid for it to be unaligned.
2. Move flush_dcache_range() out of while loop or it will
flush too much.
3. Don't try to fix buffer address before calling invalidate:
if it's unaligned it's an error anyway so let cache subsystem
cry about that.
4. Fix end buffer address to be cacheline aligned assuming upper
layer reserved enough space. This is potentially dangerous
operation so upper layers should be careful about that.
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
The USB spec says that 32 bytes is the minimum required alignment.
However on some platforms we have a larger minimum requirement for cache
coherency. In those cases, use that value rather than the USB spec
minimum. We add a cpp check to <usb.h> to define USB_DMA_MINALIGN and
make use of it in ehci-hcd.c and musb_core.h. We cannot use MAX() here
as we are not allowed to have tests inside of align(...).
Signed-off-by: Tom Rini <trini@ti.com>
[marek.vasut]: introduce some crazy macro voodoo
Signed-off-by: Marek Vasut <marex@denx.de>
[ilya.yanok]: moved external buffer fixes to separate patch,
we use {ALLOC,DEFINE}_ALIGN_BUFFER macros with alignment of USB_DMA_MINALIGN
for qh_list, qh and qtd structures to make sure they are proper aligned
for both controller and cache operations.
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
Move or_asynclistaddr programming to ehci_submit_async()
function to make sure queue head is properly programmed
before every transfer. This solves the problem with changing
qh address.
Also remove unneeded qh_list->qh_link reprogramming at the
end of transfer.
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
This has never been completely sufficient and now happens too late to
paper over the cache coherency problems with the current USB stack.
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
* 'next' of git://git.denx.de/u-boot-video:
ipu_common: Add ldb_clk for use in parenting the pixel clock
ipu_common: Do not hardcode the ipu_clk frequency
ipu_common: Rename MXC_CCM_BASE
ipu_common: Let clk_ipu_enable/disable only run on MX51 and MX53
ipu_common: Only apply the erratum to MX51
video: Rename CONFIG_VIDEO_MX5
mx6: Allow mx6 to access the IPUv3 registers
common lcd: minor coding style changes
Signed-off-by: Wolfgang Denk <wd@denx.de>
For FSL low-end processors (VVN2.2), in order to detect the SD card,
we should enable PEREN, HCKEN and IPGEN to enable the clock.
Otherwise, after booting the u-boot, and then inserting the SD card,
the SD card can't be detected.
For SDHC VVN2.3 IP, these bits are reserved, and SDCLKEN is used.
And when accessing to these reserved bit, no any impact happened.
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
CC: Andy Fleming <afleming@gmail.com>
CC: Marek Vasut <marex@denx.de>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Use the function 'mmc_send_status' to check the card status.
only when the card is ready, driver can send the next erase command
to the card, otherwise, the erase will failed:
=> mmc erase 0 1
MMC erase: dev # 0, block # 0, count 1 ... 1 blocks erase: OK
=> mmc erase 0 2
MMC erase: dev # 0, block # 0, count 2 ... mmc erase failed
1 blocks erase: ERROR
=> mmc erase 0 4
MMC erase: dev # 0, block # 0, count 4 ... mmc erase failed
1 blocks erase: ERROR
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
CC: Andy Fleming <afleming@gmail.com>
CC: Marek Vasut <marex@denx.de>
Signed-off-by: Andy Fleming <afleming@freescale.com>
This code adds call to mmc_init(), for partition related commands (e.g.
fatls, fatinfo etc.).
It is safe to call mmc_init() multiple times since mmc->has_init flag
prevents from multiple initialization.
The FAT related code calls get_dev high level method and then uses
elements from mmc->block_dev, which is uninitialized until the mmc_init
(and thereof mmc_startup) is called.
This problem appears on boards, which don't use mmc as the default
place for envs
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Andy Fleming <afleming@gmail.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
mmc_set_clock is set to the hard-coding.
But i think good that use the tran_speed value.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
* 'master' of git://git.denx.de/u-boot-i2c:
mx28evk: Add I2C support
mxs-i2c: Fix internal address byte order
mxc_i2c: remove setting speed at each start
mx6qsabrelite: add i2c support
mxc_i2c: specify i2c base address in config file
Signed-off-by: Wolfgang Denk <wd@denx.de>
Large EEPROMs, e.g. 24lc32, need 2 byte to address the internal memory.
These devices require that the high byte of the internal address has to be
written first.
The mxs_i2c driver currently writes the address' low byte first.
The following patch fixes the byte order of the internal address that should
be written to the I2C device.
Signed-off-by: Torsten Fleischer <to-fleischer@t-online.de>
CC: Marek Vasut <marex@denx.de>
CC: Stefano Babic <sbabic@denx.de>
CC: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
Other then being very weird, this code was also wrong.
For example, say I set speed to 100K. I'll read back the speed
as 85937. But the speed is really 85937.5, so we I reset
the speed to 85937, I'll get 73660.7. After a couple of transactions
my speed is now exactly 68750 so it will remain there.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
The following platforms had their config files changed
flea3, imx31_phycore, mx35pdk, mx53ard, mx53evk, mx53smd
and mx53loco.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Stefano Babic <sbabic@denx.de>
When support sh7734 of sh-ether, ECSIPR_BRCRXIP and other were removed.
Therefore SH7757 and SH7724 can not build. This revise this probelem.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Tested-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Add ldb_clk for use in parenting the pixel clock.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
The registers accessed inside clk_ipu_enable/disable are not present on MX6,
so make sure they only run on MX51 and MX53.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
The following erratum :
"ENGcm08316
IPU: Clarification regarding the bypass mode registers setup for
display and camera interfaces"
only applies to mx51, so restrict its usage for this SoC only.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* 'master' of git://git.denx.de/u-boot-arm:
tegra: define fdt_load/fdt_high variables
tegra: enable bootz command
tegra: usb: Fix device enumeration problem of USB1
tegra: trimslice: set up serial flash pinmux
tegra: add pin_mux_spi() board initialization function
tegra: add GMC/GMD funcmux entry for SFLASH
tegra: bootcmd: start USB only when needed
tegra: bootcmd enhancements
tegra: add enterrcm command
tegra: enable CONFIG_ENV_VARS_UBOOT_CONFIG
Add env vars describing U-Boot target board
tegra: usb: fix wrong error check
tegra: add ULPI on USB2 funcmux entry
tegra: fix leftover CONFIG_TEGRA2_MMC & _SPI build switches
tegra: Add Tamonten Evaluation Carrier support
tegra: Use SD write-protect GPIO on Tamonten
tegra: Implement gpio_early_init() on Tamonten
tegra: Allow boards to perform early GPIO setup
tegra: plutux: Add device tree support
tegra: medcom: Add device tree support
tegra: Rework Tamonten support
beagle: add eeprom expansion board info for bct brettl4
Signed-off-by: Wolfgang Denk <wd@denx.de>
A known hardware issue of USB1 port where bit 1 (connect status
change) of PORTSC register will be set after issuing Port Reset
(like "usb reset" in u-boot command line).
This will be treated as an error and stops later device enumeration.
Therefore we clear that bit after Port Reset in order to proceed
later device enumeration.
Signed-off-by: Jim Lin <jilin@nvidia.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This patch adds functions to enable/disable the power of USB
host controller for EXYNOS5.
Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Che-Liang Chiou <clchiou@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Drop mdelay() macros since we already have a common mdelay() func.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Needed for redundant environment for example.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Amit Virdi <amit.virdi@st.com>
Cc: Vipin Kumar <vipin.kumar@st.com>
i2c_probe() is changed to reinit the i2c bus upon read failure.
This is naturally the case upon i2c bus probing.
Also, some printf messages upon read failure are removed. As they
would interfere with the "i2c probe" command.
Additionally, i2c_set_bus_speed() now returns 0, so that the
"i2c speed" command can be used.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Amit Virdi <amit.virdi@st.com>
Cc: Vipin Kumar <vipin.kumar@st.com>
Add support for the M41T82 RTC to the m41t62 driver. The only
difference that needs to be handled by this driver, is to
clear the HT (Halt Update) bit upon reset. This bit is not
used on the M41T62, so its save to clear this bit always.
The M41T82 support will be used by the X600 (SPEAr600)
board support.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds the following changes to designware ethernet driver
found on the ST SPEAr SoC:
- Don't init MAC & PHY upon startup. This causes a delay, waiting for
the auto negotiation to complete. And we don't want this delay to
always happen. Especially not on platforms where ethernet is not
used at all (e.g. booting via flash).
Instead postpone the MAC / PHY configuration to the stage, where
ethernet is first used.
- Add possibility for board specific PHY init code. This is needed
for example on the X600 board, where the Vitesse PHY needs to be
configured for GMII mode.
This board specific PHY init is done via the function
designware_board_phy_init(). And this driver now adds a weak default
which can be overridden by board code.
- Use common functions miiphy_speed() & miiphy_duplex() to read
link status from PHY.
- Print status and progress of auto negotiation.
- Print link status (speed, dupex) upon first usage.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Amit Virdi <amit.virdi@st.com>
Cc: Vipin Kumar <vipin.kumar@st.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@gmail.com>
Few Designware peripheral registers need to be modified based on the
ethernet interface selected by the board. This patch supports interface
information in ethernet driver
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
There are two problems in the current timeout loop implementation:
1. In case initial test failing, there will always be a delay of 1 ms
2. The delay duration is not tunable
The new implementation addresses both these limitations.
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
If the flash size was smaller than 1MB then flash_print_info()
was erroneously reporting 0 MB.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
THis patch introduces a new methodology for flash probing
in which flash_devices[] table, looked-up thru the dev_id, is
used to locate the flash geometry and information.
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Since the smi erase code is very generic and works for any kind
of flash, there is no need to test for ST_M25Pxx_ID flash types
like m25p40 flashes).
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
smi_read_sr fails sometimes because of TFF not getting set within assumed time.
This condition may arise because of, for example, smi memory being in a erase
mode.
This fix is to enable reading the status register until timeout.
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
SMI driver read status fails because the control register could not be
overwritten. Instead, the read status should be tried until timeout.
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This commit does the following:
- Reports error if SNOR flash is not found on the board
- Changes smi_read_sr to return error using which a retry mechanism is
implemented for reading flash status
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Amit Virdi <amit.virdi@st.com>
Signed-off-by: Stefan Roese <sr@denx.de>
