Commit graph

6192 commits

Author SHA1 Message Date
Joonyoung Shim
44237f7a89 Odroid: Add eMMC-reset node on DT
This needs for special handling of nRESET_OUT line(GPK1-2 gpio) for eMMC
memory to perform complete reboot on Odroid X2/U3 boards.

Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-02-13 17:17:10 +09:00
Jaehoon Chung
a276172cf3 arm: exynos: fix the div value for set_mmc_clk
The most exynos used the  "Ratio + 1" as div value.
And value at register is "Ratio".
So if want to set exact value, it needs to subtract one.

Value at register ("Ratio") = div - 1

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2015-02-13 17:15:14 +09:00
Tom Rini
db7a7dee68 Merge branch 'master' of git://git.denx.de/u-boot-x86 2015-02-10 10:42:56 -05:00
Tom Rini
c956662cc3 Merge branch 'master' of git://git.denx.de/u-boot-atmel 2015-02-10 10:42:22 -05:00
Tom Rini
307367eaff Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2015-02-10 10:40:43 -05:00
Graeme Russ
2d6286ab79 arm: mxs: Add 'Wait for JTAG user' if booted in JTAG mode
When booting in JTAG mode, there is no way to use soft break-points, and
no way of knowing when SPL has finished executing (so the user can issue
a 'halt' command to load u-boot.bin for example)

Add a debug output and simple loop to stop execution at the completion of
the SPL initialisation as a pseudo break-point when booting in JTAG mode

Signed-off-by: Graeme Russ <gruss@tss-engineering.com>
2015-02-10 12:48:50 +01:00
Graeme Russ
7a08603707 arm: mxs: Enable booting of mx28 without battery
Section 4.1.2 of Freescale Application Note AN4199 describes the
configuration required to operate the mx28 from a 5V source without a
battery.

This patch changes the behaviour of the dropout control of the DC-DC
converter (refer to section 11.12.9 of the mx28 Application Processor
Reference Manual - Document Number: MCIMX28RM, Rev 2, 08/2013) to the
following:
 - Always use 4P2 Linear Regulator if CONFIG_SYS_MXS_VDD5V_ONLY is defined
 - Switch between 4P2 Linear Regulator and Battery, using whichever has
   the highest voltage if CONFIG_SYS_MXS_VDD5V_ONLY isnot set (this is
   the same as the pre-patch behaviour)

Signed-off-by: Graeme Russ <gruss@tss-engineering.com>
Signed-off-by: Damien Gotfroi <dgotfroi@greenwatch.be>
2015-02-10 12:48:50 +01:00
Graeme Russ
950eaf6230 arm: mxs: Add debug outputs and comments to mxs SPL source files
It is difficult to track down fail to boot issues in the mxs SPL.
Implement the following to make it easier:
 - Add debug outputs to allow tracing of SPL progress in order to track
where failure to boot occurs. DEUBUG and CONFIG_SPL_SERIAL_SUPPORT must
be defined to enable debug output in SPL
 - Add TODO comments where it is not clear if the code is doing what it
is meant to be doing, even tough the board boots properly (these comments
refer to existing code, not to any code added by this patch)

Signed-off-by: Graeme Russ <gruss@tss-engineering.com>
2015-02-10 12:48:49 +01:00
Ye.Li
e8cdeefc22 imx: mx6: Fixed AIPS3 base address issue
Should use AIPS3 configuration address 0x0227C000 to set AIPS3,
not the AIPS3 base address.
Additional, replace AIPS1_BASE_ADDR to AIPS3_ARB_BASE_ADDR to align with
AIPS1 and AIPS2, and resolve the AIPS3_ARB_BASE_ADDR undefine problem.

Signed-off-by: Ye.Li <B37916@freescale.com>
2015-02-10 12:48:49 +01:00
Peng Fan
1730af1bbd imx:mx6 update fuse_bank0_regs
Update fuse_bank0_regs structure according reference mannual.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
2015-02-10 12:48:48 +01:00
Tom Rini
a4fb5df214 Merge branch 'microblaze' of git://git.denx.de/u-boot-microblaze 2015-02-09 11:44:46 -05:00
Tom Rini
10918c03a9 Merge git://git.denx.de/u-boot-arc 2015-02-09 10:25:20 -05:00
Michal Simek
7f33899221 microblaze: spl: Add LISTS to linker script
This is required for driver model.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-02-09 15:13:12 +01:00
Michal Simek
ca7d22662e microblaze: spl: Do not call mem_malloc_init and use early alloc
This patch has some parts connected together:
- Use _gd in bss section which is automatically cleared
  Location at SPL_MALLOC_END wasn't cleared at all
- Use MALLOC_F_LEN(early alloc) instead of FULL MALLOC
  (mem_malloc_init is not called at all)
- Simplify malloc and stack init.
  At the end of SPL addr is malloc area and below is stack

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-02-09 15:13:12 +01:00
Michal Simek
405e651d70 microblaze: Add support for CONFIG_SYS_MALLOC_F_LEN
Create space for dm_init where calloc is called
and malloc_base has to be initialized.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-02-09 15:13:12 +01:00
Michal Simek
0510b14b73 microblaze: Do not use CONFIG_SYS_GENERIC_GLOBAL_DATA
Because it is not compatible with DM where
malloc_base has to be available early and init
has to be done in ASM.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-02-09 15:13:12 +01:00
Michal Simek
7c4dd54255 microblaze: Speedup code copy
Remove one instruction in the loop which speedup
code copying.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-02-09 15:12:46 +01:00
Michal Simek
e945f6dc28 microblaze: Move architecture to use generic board init
Compile code with -fPIC to get GOT. Do not build SPL
with fPIC because it increasing SPL size for nothing.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-02-09 15:11:56 +01:00
Michal Simek
9cef20b109 microblaze: Fix gd_t address which is placed at the end of BRAM
Setup gd from ASM to be availalbe for board_init_r.
Setting it up in spl_board_init is too late when
MALLOC is used.
Space for gd is located behind MALLOC area at the end of BRAM.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-02-09 15:09:58 +01:00
Michal Simek
e4a4743e48 microblaze: Remove unused asm label
It is not used at all that's why remove it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-02-09 15:09:58 +01:00
Michal Simek
2c7c32fa7f microblaze: Use standard interrupt_init() function
Do not use microblaze specific interrupt init function.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-02-09 15:09:58 +01:00
Michal Simek
7c6814f184 microblaze: Remove unneeded data section adding from DTB
DTB is added to rodata section:
  [ 2] .rodata           PROGBITS        84c5b60c 05c60c 00c618 00   A
0   0  4
  [ 3] .dtb.init.rodata  PROGBITS        84c67c30 068c30 003c80 00   A
0   0 16
  [ 4] .rela.dyn         RELA            84c6b8b0 06c8b0 000534 0c   A
0   0  4
  [ 5] .data             PROGBITS        84c6bde4 06cde4 001536 00  WA
0   0 16

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-02-09 15:09:57 +01:00
Michal Simek
070b8e0da2 microblaze: Add debug message about enabling interrupts
Add one more debug message about enabling global interrupts.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-02-09 15:09:57 +01:00
Michal Simek
e217b0d50d microblaze: Fix coding style
No functional changes just to pass checkpatch.pl.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-02-09 15:09:57 +01:00
Michal Simek
4c0922f367 microblaze: Remove DEBUG_INT macro and use debug() instead
Do not use specific macros for debugging.
Also remove compilation warning:
w+../arch/microblaze/cpu/interrupts.c: In function 'interrupt_handler':
w+../arch/microblaze/cpu/interrupts.c:153:2: warning: format '%x'
expects argument of type 'unsigned int', but argument 2 has type 'void
(*)(void *)' [-Wformat]
w+../arch/microblaze/cpu/interrupts.c:153:2: warning: format '%x'
expects argument of type 'unsigned int', but argument 4 has type 'void
*' [-Wformat]

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-02-09 15:09:57 +01:00
Michal Simek
5e2fc801ff microblaze: Fix coding style in exception.c
Just coding style cleanup - no functional changes.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-02-09 15:09:56 +01:00
Michal Simek
1c424d2697 microblaze: Show return address from exception
Show also return address from exception which should
suggest where the problem is.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-02-09 15:09:56 +01:00
Michal Simek
cd8574c0a7 microblaze: Fix stack usage in interrupt handler
Do not save registers below r1 stack pointer because
it is not checked by stack undeflow is not able to detect
it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2015-02-09 15:09:56 +01:00
Michal Simek
0267ba5d86 common: Move dram_init() declaration to common location
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2015-02-09 15:08:48 +01:00
Alexey Brodkin
a67ef280f4 arc: build libgcc in U-Boot
This way we may have very limited set of functions implemented so we
save some space.

Also it allows us to build U-Boot for any ARC core with the same one
toolchain because we don't rely on pre-built libgcc.

For example:
 * we may use little-endian toolchain but build U-Boot for ether
endianess
 * we may use non-multilibbed uClibc toolchain but build U-Boot for
whatever ARC CPU flavour that current GCC supports

Private libgcc built from generic C implementation contributes only 144
bytes to .text section so we don't see significant degradation of size:
--->8---
$ arc-linux-size u-boot.libgcc-prebuilt
   text	   data	    bss	    dec	    hex	filename
 222217	  24912	 214820	 461949	  70c7d	u-boot.libgcc-prebuilt

$ arc-linux-size u-boot.libgcc-private
   text	   data	    bss	    dec	    hex	filename
 222361	  24912	 214820	 462093	  70d0d	u-boot.libgcc-private
--->8---

Also I don't notice visible performance degradation compared to
pre-built libgcc (where at least "*div*" functions are had-written in
assembly) on typical operations of downloading 10Mb uImage over TFTP and
bootm.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2015-02-09 16:41:20 +03:00
Alexey Brodkin
51f4999bc5 arc: move CPU flags selection to the main "config.mk"
As a preparation to ARCv2 port submission we're moving CPU slection
flags to a common location.
Also it will allow us to have more flexible CPU specification, not only
ISA version but CPU family as well checking CONFIG_ARC_CPU_xxx.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2015-02-09 16:41:20 +03:00
Alexey Brodkin
a1dbe57d2d arc: hard-code CONFIG_ARCH_EARLY_INIT_R in asm/config.h
Common arch_early_init_r() is used in "arc/lib/cpu.c" for all ARC boards
so there's no sense in separate per-board definitions.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2015-02-09 16:41:20 +03:00
Alexey Brodkin
6eb651ad29 arc: hard-code CONFIG_SYS_GENERIC_BOARD into asm/config.h
There're no other options for ARC except "generic board" so ther's no
point to define CONFIG_SYS_GENERIC_BOARD per board.

We now have it set fo all ARC boards.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2015-02-09 16:41:20 +03:00
Alexey Brodkin
1f9ad44546 arc: add selection of endianess in Kconfig
This change allows to keep board description clean and minimalistic.
This is especially helpful if one board may house different CPUs with
different features.

It is applicable to both FPGA-based boards or those that have CPUs
mounted on interchnagable daughter-boards.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2015-02-09 16:41:20 +03:00
Alexey Brodkin
205e7a7b77 arc: select cache settings via menuconfig
This change allows to keep board description clean and minimalistic.
This is especially helpful if one board may house different CPUs with
different features.

It is applicable to both FPGA-based boards or those that have CPUs
mounted on interchnagable daughter-boards.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2015-02-09 16:41:20 +03:00
Alexey Brodkin
5ff40f3d42 arc: define and use PTAG AUX regs for MMUv3 only
DC_PTAG and IC_PTAG registers only exist in MMUv3.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2015-02-09 16:41:20 +03:00
Alexey Brodkin
812980bdd6 arc: add more flavours of ARC700 series CPU
Now we may select a particular version of ARC700:
 * ARC750D or
 * ARC770D

It allows more flexible (or more fine tuned) configuration of U-Boot.
Before that change we relied on minimal configuration but now we may
use specific features of each CPU.

Moreover allows us to escape manual selection of options that
exist in both CPUs but may have say different version like MMUv2 in
ARC750D vs MMUv3 in ARC770D.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2015-02-09 16:41:20 +03:00
Igor Guryanov
f958a91fa5 arc: memcmp - fix zero-delay loop utilization
It's prohibited to put branch instruction in the very end of zero-delay
loop. On execution this causes "Illegal instruction" exception.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
2015-02-09 16:41:20 +03:00
Heiko Schocher
f4e1886df5 arm, at91: add reset controller status register
add reset controller status register

Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Bo Shen <voice.shen@atmel.com>
2015-02-07 23:43:22 +01:00
Heiko Schocher
49b461f34a arm, at91, wdt: do not disable WDT in SPL
if CONFIG_AT91SAM9_WATCHDOG is set, do not disable WDT in
SPL

Signed-off-by: Heiko Schocher <hs@denx.de>
2015-02-07 23:43:07 +01:00
Bo Shen
c6941e1203 ARM: atmel: cleanup: remove at91cap9 related code
As the at91cap9adk board is removed by commit: b5508344
(ARM: remove broken "at91cap9adk" board), so the at91cap9
code is not used anymore, and also the document for
at91cap9 can not be found on www.atmel.com, so remove the
at91cap9 related code.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-02-07 23:42:56 +01:00
Bo Shen
0b2a982420 ARM: atmel: sama5d4_xplained: enable spl support
Signed-off-by: Bo Shen <voice.shen@atmel.com>
2015-02-07 23:42:55 +01:00
Bo Shen
5a4c9c2287 ARM: atmel: sama5d4ek: enable SPL support
The sama5d4ek support boot up from NAND flash, SD/MMC card and
also the SPI flash.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
2015-02-07 23:42:53 +01:00
Bo Shen
01c073c013 ARM: atmel: sama5d4: build related file when enable SPL
Signed-off-by: Bo Shen <voice.shen@atmel.com>
2015-02-07 23:42:52 +01:00
Bo Shen
b54dd1b3ad ARM: atmel: sama5d4: can access DDR in interleave mode
The SAMAA5D4 SoC can access DDR in interleave mode.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
2015-02-07 23:42:51 +01:00
Bo Shen
569bbd3ceb ARM: atmel: sama5d4: add interrupt redirect function
Signed-off-by: Bo Shen <voice.shen@atmel.com>
[fix subject]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
2015-02-07 23:42:50 +01:00
Bo Shen
09f5c9745b ARM: atmel: sama5d4: add bus matrix init function
Signed-off-by: Bo Shen <voice.shen@atmel.com>
2015-02-07 23:42:49 +01:00
Bo Shen
5c756bbc9d ARM: atmel: sama5d4: add matrix1 base addr definition
Signed-off-by: Bo Shen <voice.shen@atmel.com>
2015-02-07 23:42:48 +01:00
Bo Shen
0246b7c3b7 ARM: atmel: spl: can not disable osc for sama5d4
The SAMA5D4 SoC on chip rc oscillator can not be disabled.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
2015-02-07 23:42:47 +01:00
Bo Shen
4514b5f46a ARM: atmel: spl: add saic to aic redirect function
Some SoC need to redirect the saic to aic to make the interrupt to
work, here add a weak function to be replaced by real function.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
2015-02-07 23:42:46 +01:00