Commit graph

14490 commits

Author SHA1 Message Date
Andrejs Cainikovs
31d4045d4b net: dm: fec: Support phy-reset-post-delay property
As per Linux kernel DT binding doc:
- phy-reset-post-delay : Post reset delay in milliseconds. If present then
  a delay of phy-reset-post-delay milliseconds will be observed after the
  phy-reset-gpios has been toggled. Can be omitted thus no delay is
  observed. Delay is in range of 1ms to 1000ms. Other delays are invalid.

Signed-off-by: Andrejs Cainikovs <andrejs.cainikovs@netmodule.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
2019-04-08 15:23:28 +02:00
Hannes Schmelzer
afbc31948a net: phy: implement fallback mechanism for negative phy adresses
Negative phy-addresses can occour if the caller function was not able to
determine a valid phy address (from device-tree for example). In this
case we catch this here and search for ANY phy device on the given mdio-
bus.

Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Lukasz Majewski <lukma@denx.de>
2019-04-07 20:31:16 -04:00
Neil Armstrong
82548aaad5 phy: Also allow MESON_GXM for MESON_GXL_USB_PHY
The MESON_GXL_USB_PHY is also used on the Amlogic Meson GXM SoCs.

Fixes: 2960e27e38 ("phy: Add Amlogic Meson USB2 & USB3 Generic PHY drivers")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2019-04-03 10:23:38 -04:00
Jagan Teki
9d1e136734 clk: sunxi: a10: Add CLK_AHB_GMAC
CLK_AHB_GMAC was suppose to be part of previous commit
"clk: sunxi: Implement A10 EMAC clocks" add it so-that
we can get rid of sunxi_set_gate warning on boot message.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-01 21:45:15 +05:30
Tom Rini
48cf0d8c6d sunxi HDMI clock fix
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Merge tag 'video-fixes-for-2019.04-rc4' of git://git.denx.de/u-boot-video

sunxi HDMI clock fix
2019-03-31 07:25:11 -04:00
Tom Rini
4c644692f2 Last-minute fixes for Rockchip for 2019.04:
- reverts the deprecation of the 'download-key' detection
   (with a full solution pending for the next release)
 - applies a temporary fix for the 32bit pinctrl registers on the RK3288
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Merge tag 'rockchip-fixes-for-2019.04' of git://git.denx.de/u-boot-rockchip

Last-minute fixes for Rockchip for 2019.04:
- reverts the deprecation of the 'download-key' detection
  (with a full solution pending for the next release)
- applies a temporary fix for the 32bit pinctrl registers on the RK3288
2019-03-31 07:25:00 -04:00
BOUGH CHEN
5cf12031a4 mmc: correct the HS400 initialization process
After the commit b9a2a0e2e9 ("mmc: Add support for downgrading
HS200/HS400 to HS mode"), it add a parameter in mmc_set_card_speed()
which indicates that the HS200/HS400 to HS downgrade is happening.

During the HS400 initialization, first select to HS200, and config
the related clock rate, then downgrade to HS mode. So here also need
to config the downgrade value to be true for two reasons. First,
make sure in the function mmc_set_card_speed(), after switch to HS
mode, first config the clock rate, then read the EXT_CSD, avoid
receiving data of EXT_CSD in HS mode at 200MHz. Second, after issue
the MMC_CMD_SWITCH command, it need to wait a bit then switch bus
properties.

Test on i.MX8QM MEK board, some Micron eMMC will stuck in transfer
mode in this case, and USDHC will never get data transfer complete
status, cause the uboot hang.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
2019-03-29 10:53:18 -04:00
David Wu
502980914b pinctrl: rockchip: Add 32bit writing function for rk3288 gpio0 pinctrl
There are no higher 16 writing corresponding bits for pmu_gpio0's
iomux/drive/pull at rk3288, need to read the value from register
firstly. Add the flag to distinguish it from normal registers.

Signed-off-by: David Wu <david.wu@rock-chips.com>
2019-03-29 09:24:44 +01:00
Jernej Skrabec
1feed358ed sunxi: video: HDMI: Fix clock setup
Currently, HDMI driver doesn't consider minimum and maximum allowed rate
of pll3 (video PLL). It works most of the time, but not always.

Consider monitor with resolution 1920x1200, which has pixel clock rate
of 154 MHz. Current code would determine that pll3 rate has to be set to
154 MHz. However, minimum supported rate is 192 MHz. In this case video
output just won't work.

The reason why the driver is written in the way it is, is that at the
time HDMI PHY and clock configuration wasn't fully understood. But now
we have needed knowledge, so the issue can be fixed.

With this fix, clock configuration routine uses full range (1-16) for
clock divider instead of limited one (1, 2, 4, 11). It also considers
minimum and maximum allowed rate for pll3.

Fixes: 56009451d8 ("sunxi: video: Add A64/H3/H5 HDMI driver")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-03-28 23:45:41 +01:00
Tom Rini
d32519ac8a Merge branch 'master' of git://git.denx.de/u-boot-sh
- Various fixes for bugs found by u-boot test.py
2019-03-26 23:19:11 -04:00
Patrick Delaunay
14453fbfad Convert CONFIG_SF_DEFAULT_* to Kconfig
This converts the following to Kconfig:
  CONFIG_SF_DEFAULT_BUS
  CONFIG_SF_DEFAULT_CS
  CONFIG_SF_DEFAULT_MODE
  CONFIG_SF_DEFAULT_SPEED

I use moveconfig script and then manual check on generated u-boot.cfg
to solve the remaining issue.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-03-25 17:36:53 -04:00
Marek Vasut
c453fe3a05 mmc: tmio: Clamp SD_SECCNT to 16bit values on 16bit IP
On 16bit variants of the TMIO SD IP, the SECCNT register can only be
programmed to 16bit values, while on the 32bit and 64bit variants it
can be programmed to 32bit values. The SECCNT register indicates the
maximum number of blocks in a continuous transfer. Hence, limit the
maximum continuous transfer block count to 65535 blocks on 16bit
variants of the TMIO IP and to BIT(32)-1 blocks on 32bit and 64bit
variants.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-03-25 20:26:53 +01:00
Marek Vasut
f4eaa56a52 mmc: sh_mmcif: Set default MMCIF clock rate
Set MMCIF clock rate to 97.5 MHz, which is the default according
to Gen2 datasheet.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
2019-03-25 20:26:53 +01:00
Marek Vasut
3cb2849c76 clk: renesas: Add support for setting MMCIF clock divider on Gen2
Add code for configuring the MMC0CKCR/MMC1CKCR on Gen2 platforms.
This allows the MMCIF driver to set higher clock rate if desired.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-25 20:26:53 +01:00
Marek Vasut
4b135d5464 clk: renesas: Fix swapped div and mul in debug output on Gen2
The $div and $mul values were swapped in the debug output,
fix this.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-25 20:26:53 +01:00
Marek Vasut
45b01b462f clk: renesas: Fix SDH clock divider decoding on Gen2
The gen2_clk_get_sdh_div() function is supposed to look up the
$val value read out of the SDCKCR register in the supplied table
and return the matching divider value. The current implementation
was matching the value from SDCKCR on the divider value in the
table, which is wrong. Fix this and rework the function a bit
to make it more readable.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2019-03-25 20:26:53 +01:00
Marek Vasut
7d5ccb1ae7 mmc: Align MMC_TRACE with tiny printf
The tiny printf implementation only supports %x format specifier,
it does not support %X . Since it makes little difference whether
the debug output prints hex numbers in capitals or not, change it
to %x and make the MMC_TRACE output work with tiny printf too.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
2019-03-25 11:44:12 -04:00
Tom Rini
3d7891d3f3 Merge branch 'master' of git://git.denx.de/u-boot-i2c
- i2c: i2c_cdns: Fix below warnings with checker tool
2019-03-21 13:04:42 -04:00
Siva Durga Prasad Paladugu
9d59d6fff6 i2c: i2c_cdns: Fix below warnings with checker tool
This patch fixes below warnings found with checker tool.
The variable len in i2c_msg struct is of unsigned type
and it is received as recv_count which is unsigned type
but it is checked with < 0 which is always false, hence
removed it.
The local variable curr_recv_count is declared as signed
type and compared aginst unsigned recv_count which is
incorrect. This is fixed by declaring it as unsigned type.

drivers/i2c/i2c-cdns.c: In function ‘cdns_i2c_read_data’:
drivers/i2c/i2c-cdns.c:317:18: warning: comparison of
unsigned expression < 0 is always false [-Wtype-limits]
  if ((recv_count < 0))
                  ^
drivers/i2c/i2c-cdns.c:340:24: warning: comparison of
integer expressions of different signedness:
‘u32’ {aka ‘unsigned int’} and ‘int’ [-Wsign-compare]
  updatetx = recv_count > curr_recv_count;
                        ^
drivers/i2c/i2c-cdns.c:361:39: warning: comparison of
integer expressions of different signedness:
‘u32’ {aka ‘unsigned int’} and ‘int’ [-Wsign-compare]
    while (readl(&regs->transfer_size) !=

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-03-21 08:21:43 +01:00
Tom Rini
a00d15757d Merge git://git.denx.de/u-boot-marvell
- Enable network interface on clearfog_gt_8k (Baruch)
- Fix dreamplug boot by adding an spi0 alias to the DT (Chris)
- Fix / enhance Marvell ddr3 setup / parameters (Chris)
- Change CONFIG_SYS_MALLOC_F_LEN to 0x2000 on db-88f6820-amc (Chris)
- Enable SPL_FLASH_BAR on db-88f6820-amc (Chris)
- Use correct pcie controller name in Armada-38x dts files (Chris)
- Disable d-cache on Kirkwood platforms as currently needed (Chris)
- Add a more descriptive comment to pci_mvebu.c (Stefan)
- Update Marvell maintainers entry (Stefan)
2019-03-19 19:58:48 -04:00
Tom Rini
7eddda4537 Merge branch 'master' of git://git.denx.de/u-boot-usb
- Fastboot fixes
2019-03-19 07:13:03 -04:00
Chris Packham
247c80d6b8 mv_ddr: ddr3: only use active chip-selects when tuning ODT
Inactive chip-selects will give invalid values for read_sample so don't
consider them when trying to determine the overall min/max read sample.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>

[https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/18]
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-03-19 09:22:05 +01:00
Chris Packham
08dcbc9823 mv_ddr: ddr3: fix tRAS timimg parameter
Based on the JEDEC standard JESD79-3F. The tRAS timings should include
the highest speed bins at a given frequency. This is similar to commit
683c67b ("mv_ddr: ddr3: fix tfaw timimg parameter") where the wrong
comparison was used in the initial implementation.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>

[https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/15]
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-03-19 09:22:05 +01:00
Stefan Roese
0df62e8da8 pci: pci_mvebu: Add comment about missing of_n_addr_cells() call
This patch adds a comment to explain the use of the hardcoded value for
the number of address cells in mvebu_get_tgt_attr(). This should help to
rework this function, once CONFIG_OF_LIVE is enabled for MVEBU in
general.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-03-19 09:22:05 +01:00
Neil Armstrong
f402d268e8 fastboot: common: fix default fastboot_boot on 64-bit
When booting on a 64-bit system, the boot_addr_start buffer is not
large enough to contain a 64-bit number, thus leading to a crash
even if fastboot_buf_addr is valid, only the high part of the address
will be printed to boot_addr_start :

fastboot with fastboot_buf_addr = 0x0000000006000000:
  downloading of 92239872 bytes finished
  Booting kernel at 0x00000000...

  "Synchronous Abort" handler, esr 0x96000004
  elr: 00000000010561f4 lr : 0000000001056fac (reloc)
  <snip>
  x28: 000000007df2d38f x29: 000000007df2d1b0

  Resetting CPU ...

With this fix, boot_addr_start can have the full 64-bit address passed
to bootm.

Fixes: f73a7df984 ("net: fastboot: Merge AOSP UDP fastboot")
Cc: Simon Glass <sjg@chromium.org>
Cc: Alex Kiernan <alex.kiernan@gmail.com>
Cc: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-03-16 13:29:43 +01:00
Jean-Jacques Hiblot
e81d9de531 usb: udc-uclass: Fixed problem when no alias is defined in DT
commit 801f1fa442 "dm: usb: udc: Use SEQ_ALIAS to index the USB gadget
ports" changed the way the udevice if found. It uses the alias to find
a udevice for a given USB port number. In the commit log it was stated
that if no alias is provided, the bind order will be used instead. However
it doesn't work. Fixing this by adding a call to uclass_get_device() if
uclass_get_device_by_seq() fails.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Tested-by: Vignesh R <vigneshr@ti.com>
2019-03-16 13:29:43 +01:00
Tom Rini
8303467e80 Merge git://git.denx.de/u-boot-fsl-qoriq
- DPAA2 fixes and DDR errata workaround for LS1021A
2019-03-15 11:58:17 -04:00
Pramod Kumar
ba7eadd8e1 drivers: net: ls1088ardb: Fix EC1 and EC2 RCW offset
Fix EC1 and EC2 read from correct offset 26, instead of 25

Signed-off-by: Pramod Kumar <pramod.kumar_1@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-03-15 11:52:01 +05:30
Meenakshi Aggarwal
43ad41e6ae mc : Reduce MC memory size to 128M
ls2088, ls1088 : minimum MC Memory size is 128 MB
lx2 : minimum MC memory size is 256 MB

Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-03-15 11:52:00 +05:30
Ioana Ciocoi Radulescu
2e9f1bf588 driver: net: fsl-mc: Fix DPC MAC address fixup
If node /board_info/ports does not exist in the DPC file,
function mc_fixup_dpc() will skip not only MAC address fixup,
but also the cache flush at the end. This may cause the other
fixup changes (e.g. ICID related ones) to be ignored by MC.

Fixes: 1161dbcc0a ("drivers: net: fsl-mc: Include MAC addr fixup to DPL")

Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-03-15 11:52:00 +05:30
Pankaj Bansal
82fadccccf drivers: net: ldpaa_eth: check if the dpmac is enabled
some dpmacs in armv8a based freescale layerscape SOCs can be
configured via both serdes(sgmii, xfi, xlaui etc) bits and via
EC*_PMUX(rgmii) bits in RCW.
e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from
serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits
Now if a dpmac is enabled by serdes bits then it takes precedence
over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol
that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII,
then the dpmac is SGMII and not RGMII.

Therefore, in fsl_rgmii_init function of SOC, we will check if the
dpmac is enabled or not? if it is (fsl_serdes_init has already enabled
the dpmac), then don't enable it.

Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-03-15 11:52:00 +05:30
Tom Rini
9659eb46af Merge branch 'master' of git://git.denx.de/u-boot-samsung 2019-03-14 11:37:11 -04:00
Tom Rini
a0d12cd239 Small fixes in several i.MX boards
----------------------------------
 
 - imx8: add pinctrl driveri (mx8m), fix documentation and
   fix reported CPU frequency. Fabio is co-maintainer
 - pico-imx6ul: switch to DM
 - local fixes for ventana, mx6ul_14x14_evk, engicam,
   imx6(q)_logic, liteboard
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Merge tag 'u-boot-imx-20190313' of git://git.denx.de/u-boot-imx

Small fixes in several i.MX boards
----------------------------------

- imx8: add pinctrl driveri (mx8m), fix documentation and
  fix reported CPU frequency. Fabio is co-maintainer
- pico-imx6ul: switch to DM
- local fixes for ventana, mx6ul_14x14_evk, engicam,
  imx6(q)_logic, liteboard
2019-03-13 16:07:41 -04:00
Hannes Schmelzer
b882005a18 drivers/net/fec: phy_init: remove redundant logic
The phy_connect_dev(...) function from phy.c does all the handling
(inclusive catching fixed-link).

So we drop here the single steps and call just phy_connect_dev(...).

Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-03-13 09:14:35 +01:00
Adam Ford
d46d27d3b6 MTD: mxs_nand_spl: Redo the way nand_init initializes
Currently the spl system calls nand_init which does nothing.
It isn't until an attempt to load from NAND that it gets initialized.
Subsequent attempts to load just skip the initialization  because
NAND is already initialized.

This moves the contents of mxs_nand_init to nand_init.  In the event
of an error, it clears the number of nand chips found.  Any
attempts to use nand will check if there are nand chips available
instead of actually doing the initialization at that time. If there
are none, it will return an error to the higher level calls.

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-03-13 09:14:35 +01:00
Adam Ford
e434b414fb imx: serial_mxc: use CONFIG_IS_ENABLED instead of ifdef
Kconfig allows boards to configured with DM_SERIAL and still
have SPL_DM_SERIAL disabled.  This patch changes the ifdef's
to CONFIG_IS_ENABLED to allow the modes to differ between
SPL and U-Boot.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-03-13 09:14:35 +01:00
Peng Fan
78814467a0 pinctrl: add imx8m driver
Add i.mx8m pinctrl driver.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-03-13 09:14:35 +01:00
Tom Rini
116a3a1ae0 Pull request for UEFI system for v2019.04-rc4
Fix an error with the serial communication on boards with a very small
 UART buffer which leads to a stalled system.
 
 Provide an X86 reset driver for the UEFI runtime.
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Merge tag 'efi-2019-04-rc4-2' of https://github.com/xypron2/u-boot

Pull request for UEFI system for v2019.04-rc4

Fix an error with the serial communication on boards with a very small
UART buffer which leads to a stalled system.

Provide an X86 reset driver for the UEFI runtime.
2019-03-12 10:56:02 -04:00
Tom Rini
2e8092d94f Merge branch 'master' of git://git.denx.de/u-boot-sunxi
- axp818 fix
- fix warnings for ethernet clock code
2019-03-11 15:48:57 -04:00
Krzysztof Kozlowski
000ee4b739 power: regulator: s2mps11: Add enable delay
According to datasheet, the output on LDO regulators will start
appearing after 10-15 us.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2019-03-11 15:53:19 +09:00
Krzysztof Kozlowski
e66d1cb3c2 regulator: Add support for ramp delay
Changing voltage and enabling regulator might require delays so the
regulator stabilizes at expected level.

Add support for "regulator-ramp-delay" binding which can introduce
required time to both enabling the regulator and to changing the
voltage.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2019-03-11 15:53:19 +09:00
Krzysztof Kozlowski
311eaf7430 power: regulator: s2mps11: Fix step for LDO27 and LDO35
LDO27 and LDO35 have 25 mV step, not 50 mV.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2019-03-11 15:53:19 +09:00
Krzysztof Kozlowski
6e74c6af32 adc: exynos-adc: Fix wrong bit operation used to stop the ADC
When stopping the ADC_V2_CON1_STC_EN should be cleared.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2019-03-11 15:53:19 +09:00
Alexander Graf
3eeb09b4c0 x86: Add efi runtime reset
Our selftest will soon test the actual runtime reset function rather than
the boot time one. For this, we need to ensure that the runtime version
actually succeeds on x86 to keep our travis tests work.

So this patch implements an x86 runtime reset function. It is missing
shutdown functionality today, but OSs usually implement that via ACPI
and this function does more than the stub from before, so it's at least
an improvement.

Eventually we will want to have full DM functionality in runtime services.
But this fixes a travis failure and doesn't clutter the code too heavily, so
we should pull it in without the amazing new RTS DM framework.

Signed-off-by: Alexander Graf <agraf@suse.de>
2019-03-11 00:44:42 +01:00
Marek Vasut
88c3bb49e1 ddr: socfpga: Clean up ddr_setup()
Replace the current rather convoluted code using ad-hoc polling
mechanism with a more straightforward code. Use wait_for_bit_le32()
to poll the DDRCALSTAT register instead of local reimplementation.
It makes no sense to pull for 5 seconds before giving up and trying
to restart the EMIF, so instead wait 500 mSec for the calibration to
complete and if this fails, restart the EMIF and try again. Perform
this 32 times instead of 3 times as the original code did.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2019-03-09 23:25:19 +01:00
Marek Vasut
8297dd1d93 ddr: socfpga: Clean up EMIF reset
The EMIF reset code can well use wait_for_bit_le32() instead of all that
convoluted polling code. Reduce the timeout from 100 seconds to 1 second,
since if the EMIF fails to reset itself in 1 second, it's unlikely longer
wait would help. Make sure to clear the EMIF reset request even if the
SEQ2CORE_INT_RESP_BIT isn't asserted.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2019-03-09 23:25:19 +01:00
Marek Vasut
ffd1e1a336 ddr: socfpga: Fix EMIF clear timeout
The current EMIF clear timeout handling code was applying bitwise
operations to signed data types and as it was, was extremely hard
to read. Replace it with simple wait_for_bit(). Expand the error
handling to make it more readable too.

This patch also changes the timeout for emif_clear() from 14 hours
to 1 second.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2019-03-09 23:25:19 +01:00
Marek Vasut
dc3249b91b ddr: socfpga: Fix newline in debug print on A10
The debug print is missing a newline, add it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2019-03-09 17:59:13 +01:00
Marek Vasut
71fc4825f7 ddr: socfpga: Fix IO in Arria10 DDR driver
The Altera Arria10 DDR driver was using constants in a few places
instead of reading registers associated with those constants, fix
this.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2019-03-09 17:59:13 +01:00
Jagan Teki
aefc0b7a60 clk: sunxi: h3: Implement EPHY CLK and RESET
EPHY CLK and RESET is available in Allwinner H3 EMAC
via mdio-mux node of internal PHY. Add the respective
clock and reset reg and bits.

Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-03-09 13:16:35 +05:30