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mv_ddr: ddr3: fix tRAS timimg parameter

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Based on the JEDEC standard JESD79-3F. The tRAS timings should include
the highest speed bins at a given frequency. This is similar to commit
683c67b ("mv_ddr: ddr3: fix tfaw timimg parameter") where the wrong
comparison was used in the initial implementation.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>

[https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/15]
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Chris Packham 2019-03-01 10:11:13 +13:00 committed by Stefan Roese
parent 5860532264
commit 08dcbc9823
1 changed files with 4 additions and 4 deletions
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8
drivers/ddr/marvell/a38x/ddr3_training_db.c
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@ -420,13 +420,13 @@ unsigned int mv_ddr_speed_bin_timing_get(enum mv_ddr_speed_bin index, enum mv_dd
result = speed_bin_table_t_rcd_t_rp[index];
break;
case SPEED_BIN_TRAS:
if (index < SPEED_BIN_DDR_1066G)
if (index <= SPEED_BIN_DDR_1066G)
result = 37500;
else if (index < SPEED_BIN_DDR_1333J)
else if (index <= SPEED_BIN_DDR_1333J)
result = 36000;
else if (index < SPEED_BIN_DDR_1600K)
else if (index <= SPEED_BIN_DDR_1600K)
result = 35000;
else if (index < SPEED_BIN_DDR_1866M)
else if (index <= SPEED_BIN_DDR_1866M)
result = 34000;
else
result = 33000;