mirror of
https://github.com/AsahiLinux/u-boot
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sunxi: video: Add A64/H3/H5 HDMI driver
This commit adds support for HDMI output. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit is contained in:
Jernej Skrabec
Maxime Ripard
parent
a05a45493d
commit
56009451d8
7 changed files with 795 additions and 0 deletions
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@ -18,6 +18,8 @@
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#define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */
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#define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */
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#define SUNXI_DE2_BASE 0x01000000
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#ifdef CONFIG_MACH_SUN8I_A83T
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#define SUNXI_CPUCFG_BASE 0x01700000
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#endif
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@ -46,7 +48,9 @@
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#define SUNXI_USB1_BASE 0x01c14000
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#endif
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#define SUNXI_SS_BASE 0x01c15000
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#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I)
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#define SUNXI_HDMI_BASE 0x01c16000
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#endif
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#define SUNXI_SPI2_BASE 0x01c17000
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#define SUNXI_SATA_BASE 0x01c18000
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#ifdef CONFIG_SUNXI_GEN_SUN4I
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@ -164,6 +168,10 @@ defined(CONFIG_MACH_SUN50I)
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#define SUNXI_MP_BASE 0x01e80000
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#define SUNXI_AVG_BASE 0x01ea0000
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#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I)
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#define SUNXI_HDMI_BASE 0x01ee0000
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#endif
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#define SUNXI_RTC_BASE 0x01f00000
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#define SUNXI_PRCM_BASE 0x01f01400
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124
arch/arm/include/asm/arch-sunxi/display2.h
Normal file
124
arch/arm/include/asm/arch-sunxi/display2.h
Normal file
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@ -0,0 +1,124 @@
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/*
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* Sunxi platform display controller register and constant defines
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*
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* (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
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*
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* Based on out of tree Linux DRM driver defines:
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* Copyright (C) 2016 Jean-Francois Moine <moinejf@free.fr>
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* Copyright (c) 2016 Allwinnertech Co., Ltd.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _SUNXI_DISPLAY2_H
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#define _SUNXI_DISPLAY2_H
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/* internal clock settings */
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struct de_clk {
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u32 gate_cfg;
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u32 bus_cfg;
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u32 rst_cfg;
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u32 div_cfg;
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u32 sel_cfg;
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};
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/* global control */
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struct de_glb {
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u32 ctl;
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u32 status;
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u32 dbuff;
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u32 size;
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};
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/* alpha blending */
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struct de_bld {
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u32 fcolor_ctl;
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struct {
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u32 fcolor;
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u32 insize;
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u32 offset;
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u32 dum;
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} attr[4];
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u32 dum0[15];
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u32 route;
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u32 premultiply;
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u32 bkcolor;
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u32 output_size;
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u32 bld_mode[4];
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u32 dum1[4];
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u32 ck_ctl;
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u32 ck_cfg;
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u32 dum2[2];
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u32 ck_max[4];
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u32 dum3[4];
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u32 ck_min[4];
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u32 dum4[3];
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u32 out_ctl;
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};
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/* VI channel */
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struct de_vi {
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struct {
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u32 attr;
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u32 size;
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u32 coord;
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u32 pitch[3];
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u32 top_laddr[3];
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u32 bot_laddr[3];
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} cfg[4];
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u32 fcolor[4];
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u32 top_haddr[3];
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u32 bot_haddr[3];
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u32 ovl_size[2];
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u32 hori[2];
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u32 vert[2];
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};
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struct de_ui {
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struct {
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u32 attr;
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u32 size;
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u32 coord;
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u32 pitch;
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u32 top_laddr;
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u32 bot_laddr;
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u32 fcolor;
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u32 dum;
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} cfg[4];
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u32 top_haddr;
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u32 bot_haddr;
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u32 ovl_size;
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};
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/*
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* DE register constants.
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*/
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#define SUNXI_DE2_MUX0_BASE (SUNXI_DE2_BASE + 0x100000)
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#define SUNXI_DE2_MUX1_BASE (SUNXI_DE2_BASE + 0x200000)
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#define SUNXI_DE2_MUX_GLB_REGS 0x00000
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#define SUNXI_DE2_MUX_BLD_REGS 0x01000
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#define SUNXI_DE2_MUX_CHAN_REGS 0x02000
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#define SUNXI_DE2_MUX_CHAN_SZ 0x1000
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#define SUNXI_DE2_MUX_VSU_REGS 0x20000
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#define SUNXI_DE2_MUX_GSU1_REGS 0x30000
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#define SUNXI_DE2_MUX_GSU2_REGS 0x40000
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#define SUNXI_DE2_MUX_GSU3_REGS 0x50000
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#define SUNXI_DE2_MUX_FCE_REGS 0xa0000
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#define SUNXI_DE2_MUX_BWS_REGS 0xa2000
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#define SUNXI_DE2_MUX_LTI_REGS 0xa4000
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#define SUNXI_DE2_MUX_PEAK_REGS 0xa6000
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#define SUNXI_DE2_MUX_ASE_REGS 0xa8000
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#define SUNXI_DE2_MUX_FCC_REGS 0xaa000
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#define SUNXI_DE2_MUX_DCSC_REGS 0xb0000
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#define SUNXI_DE2_FORMAT_XRGB_8888 4
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#define SUNXI_DE2_FORMAT_RGB_565 10
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#define SUNXI_DE2_MUX_GLB_CTL_EN (1 << 0)
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#define SUNXI_DE2_UI_CFG_ATTR_EN (1 << 0)
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#define SUNXI_DE2_UI_CFG_ATTR_FMT(f) ((f & 0xf) << 8)
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#define SUNXI_DE2_WH(w, h) (((h - 1) << 16) | (w - 1))
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#endif /* _SUNXI_DISPLAY2_H */
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@ -708,6 +708,16 @@ config SUNXI_DE2
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bool
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default n
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config VIDEO_DE2
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bool "Display Engine 2 video driver"
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depends on SUNXI_DE2
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select DM_VIDEO
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select DISPLAY
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default y
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---help---
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Say y here if you want to build DE2 video driver which is present on
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newer SoCs. Currently only HDMI output is supported.
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choice
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prompt "LCD panel support"
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@ -6,3 +6,4 @@
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#
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obj-$(CONFIG_VIDEO_SUNXI) += sunxi_display.o lcdc.o ../videomodes.o
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obj-$(CONFIG_VIDEO_DE2) += sunxi_de2.o sunxi_dw_hdmi.o lcdc.o ../dw_hdmi.o
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258
drivers/video/sunxi/sunxi_de2.c
Normal file
258
drivers/video/sunxi/sunxi_de2.c
Normal file
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@ -0,0 +1,258 @@
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/*
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* Allwinner DE2 display driver
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*
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* (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <display.h>
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#include <dm.h>
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#include <edid.h>
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#include <video.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/display2.h>
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#include <dm/device-internal.h>
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#include <dm/uclass-internal.h>
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DECLARE_GLOBAL_DATA_PTR;
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enum {
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/* Maximum LCD size we support */
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LCD_MAX_WIDTH = 3840,
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LCD_MAX_HEIGHT = 2160,
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LCD_MAX_LOG2_BPP = VIDEO_BPP32,
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};
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static void sunxi_de2_composer_init(void)
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{
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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#ifdef CONFIG_MACH_SUN50I
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u32 reg_value;
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/* set SRAM for video use (A64 only) */
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reg_value = readl(SUNXI_SRAMC_BASE + 0x04);
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reg_value &= ~(0x01 << 24);
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writel(reg_value, SUNXI_SRAMC_BASE + 0x04);
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#endif
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clock_set_pll10(432000000);
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/* Set DE parent to pll10 */
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clrsetbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_PLL_MASK,
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CCM_DE2_CTRL_PLL10);
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/* Set ahb gating to pass */
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setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE);
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setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE);
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/* Clock on */
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setbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_GATE);
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}
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static void sunxi_de2_mode_set(int mux, const struct display_timing *mode,
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int bpp, ulong address)
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{
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ulong de_mux_base = (mux == 0) ?
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SUNXI_DE2_MUX0_BASE : SUNXI_DE2_MUX1_BASE;
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struct de_clk * const de_clk_regs =
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(struct de_clk *)(SUNXI_DE2_BASE);
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struct de_glb * const de_glb_regs =
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(struct de_glb *)(de_mux_base +
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SUNXI_DE2_MUX_GLB_REGS);
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struct de_bld * const de_bld_regs =
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(struct de_bld *)(de_mux_base +
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SUNXI_DE2_MUX_BLD_REGS);
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struct de_ui * const de_ui_regs =
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(struct de_ui *)(de_mux_base +
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SUNXI_DE2_MUX_CHAN_REGS +
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SUNXI_DE2_MUX_CHAN_SZ * 1);
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u32 size = SUNXI_DE2_WH(mode->hactive.typ, mode->vactive.typ);
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int channel;
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u32 format;
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/* enable clock */
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#ifdef CONFIG_MACH_SUN8I_H3
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setbits_le32(&de_clk_regs->rst_cfg, (mux == 0) ? 1 : 4);
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#else
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setbits_le32(&de_clk_regs->rst_cfg, BIT(mux));
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#endif
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setbits_le32(&de_clk_regs->gate_cfg, BIT(mux));
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setbits_le32(&de_clk_regs->bus_cfg, BIT(mux));
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clrbits_le32(&de_clk_regs->sel_cfg, 1);
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writel(SUNXI_DE2_MUX_GLB_CTL_EN, &de_glb_regs->ctl);
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writel(0, &de_glb_regs->status);
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writel(1, &de_glb_regs->dbuff);
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writel(size, &de_glb_regs->size);
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for (channel = 0; channel < 4; channel++) {
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void *ch = (void *)(de_mux_base + SUNXI_DE2_MUX_CHAN_REGS +
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SUNXI_DE2_MUX_CHAN_SZ * channel);
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memset(ch, 0, (channel == 0) ?
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sizeof(struct de_vi) : sizeof(struct de_ui));
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}
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memset(de_bld_regs, 0, sizeof(struct de_bld));
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writel(0x00000101, &de_bld_regs->fcolor_ctl);
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writel(1, &de_bld_regs->route);
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writel(0, &de_bld_regs->premultiply);
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writel(0xff000000, &de_bld_regs->bkcolor);
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writel(0x03010301, &de_bld_regs->bld_mode[0]);
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writel(size, &de_bld_regs->output_size);
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writel(mode->flags & DISPLAY_FLAGS_INTERLACED ? 2 : 0,
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&de_bld_regs->out_ctl);
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writel(0, &de_bld_regs->ck_ctl);
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writel(0xff000000, &de_bld_regs->attr[0].fcolor);
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writel(size, &de_bld_regs->attr[0].insize);
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/* Disable all other units */
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writel(0, de_mux_base + SUNXI_DE2_MUX_VSU_REGS);
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writel(0, de_mux_base + SUNXI_DE2_MUX_GSU1_REGS);
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writel(0, de_mux_base + SUNXI_DE2_MUX_GSU2_REGS);
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writel(0, de_mux_base + SUNXI_DE2_MUX_GSU3_REGS);
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writel(0, de_mux_base + SUNXI_DE2_MUX_FCE_REGS);
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writel(0, de_mux_base + SUNXI_DE2_MUX_BWS_REGS);
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writel(0, de_mux_base + SUNXI_DE2_MUX_LTI_REGS);
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writel(0, de_mux_base + SUNXI_DE2_MUX_PEAK_REGS);
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writel(0, de_mux_base + SUNXI_DE2_MUX_ASE_REGS);
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writel(0, de_mux_base + SUNXI_DE2_MUX_FCC_REGS);
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writel(0, de_mux_base + SUNXI_DE2_MUX_DCSC_REGS);
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switch (bpp) {
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case 16:
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format = SUNXI_DE2_UI_CFG_ATTR_FMT(SUNXI_DE2_FORMAT_RGB_565);
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break;
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case 32:
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default:
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format = SUNXI_DE2_UI_CFG_ATTR_FMT(SUNXI_DE2_FORMAT_XRGB_8888);
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break;
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}
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writel(SUNXI_DE2_UI_CFG_ATTR_EN | format, &de_ui_regs->cfg[0].attr);
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writel(size, &de_ui_regs->cfg[0].size);
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writel(0, &de_ui_regs->cfg[0].coord);
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writel((bpp / 8) * mode->hactive.typ, &de_ui_regs->cfg[0].pitch);
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writel(address, &de_ui_regs->cfg[0].top_laddr);
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writel(size, &de_ui_regs->ovl_size);
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/* apply settings */
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writel(1, &de_glb_regs->dbuff);
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}
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static int sunxi_de2_init(struct udevice *dev, ulong fbbase,
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enum video_log2_bpp l2bpp,
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struct udevice *disp, int mux)
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{
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struct video_priv *uc_priv = dev_get_uclass_priv(dev);
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struct display_timing timing;
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struct display_plat *disp_uc_plat;
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int ret;
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disp_uc_plat = dev_get_uclass_platdata(disp);
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debug("Using device '%s', disp_uc_priv=%p\n", disp->name, disp_uc_plat);
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if (display_in_use(disp)) {
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debug(" - device in use\n");
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return -EBUSY;
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}
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disp_uc_plat->source_id = mux;
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ret = device_probe(disp);
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if (ret) {
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debug("%s: device '%s' display won't probe (ret=%d)\n",
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__func__, dev->name, ret);
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return ret;
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}
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ret = display_read_timing(disp, &timing);
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if (ret) {
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debug("%s: Failed to read timings\n", __func__);
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return ret;
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}
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sunxi_de2_composer_init();
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sunxi_de2_mode_set(mux, &timing, 1 << l2bpp, fbbase);
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ret = display_enable(disp, 1 << l2bpp, &timing);
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if (ret) {
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debug("%s: Failed to enable display\n", __func__);
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return ret;
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}
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uc_priv->xsize = timing.hactive.typ;
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uc_priv->ysize = timing.vactive.typ;
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uc_priv->bpix = l2bpp;
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debug("fb=%lx, size=%d %d\n", fbbase, uc_priv->xsize, uc_priv->ysize);
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return 0;
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}
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static int sunxi_de2_probe(struct udevice *dev)
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{
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struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
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struct udevice *disp;
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int ret;
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int mux;
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/* Before relocation we don't need to do anything */
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if (!(gd->flags & GD_FLG_RELOC))
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return 0;
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ret = uclass_find_device_by_name(UCLASS_DISPLAY,
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"sunxi_dw_hdmi", &disp);
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if (ret) {
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debug("%s: hdmi display not found (ret=%d)\n", __func__, ret);
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return ret;
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}
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if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5))
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mux = 0;
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else
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mux = 1;
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ret = sunxi_de2_init(dev, plat->base, VIDEO_BPP32, disp, mux);
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if (ret)
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return ret;
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video_set_flush_dcache(dev, 1);
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return 0;
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}
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static int sunxi_de2_bind(struct udevice *dev)
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{
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struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
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plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
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(1 << LCD_MAX_LOG2_BPP) / 8;
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return 0;
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}
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|
||||
static const struct video_ops sunxi_de2_ops = {
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(sunxi_de2) = {
|
||||
.name = "sunxi_de2",
|
||||
.id = UCLASS_VIDEO,
|
||||
.ops = &sunxi_de2_ops,
|
||||
.bind = sunxi_de2_bind,
|
||||
.probe = sunxi_de2_probe,
|
||||
.flags = DM_FLAG_PRE_RELOC,
|
||||
};
|
||||
|
||||
U_BOOT_DEVICE(sunxi_de2) = {
|
||||
.name = "sunxi_de2"
|
||||
};
|
||||
389
drivers/video/sunxi/sunxi_dw_hdmi.c
Normal file
389
drivers/video/sunxi/sunxi_dw_hdmi.c
Normal file
|
|
@ -0,0 +1,389 @@
|
|||
/*
|
||||
* Allwinner DW HDMI bridge
|
||||
*
|
||||
* (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <display.h>
|
||||
#include <dm.h>
|
||||
#include <dw_hdmi.h>
|
||||
#include <edid.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/lcdc.h>
|
||||
|
||||
struct sunxi_dw_hdmi_priv {
|
||||
struct dw_hdmi hdmi;
|
||||
int mux;
|
||||
};
|
||||
|
||||
struct sunxi_hdmi_phy {
|
||||
u32 pol;
|
||||
u32 res1[3];
|
||||
u32 read_en;
|
||||
u32 unscramble;
|
||||
u32 res2[2];
|
||||
u32 ctrl;
|
||||
u32 unk1;
|
||||
u32 unk2;
|
||||
u32 pll;
|
||||
u32 clk;
|
||||
u32 unk3;
|
||||
u32 status;
|
||||
};
|
||||
|
||||
#define HDMI_PHY_OFFS 0x10000
|
||||
|
||||
static int sunxi_dw_hdmi_get_divider(uint clock)
|
||||
{
|
||||
/*
|
||||
* Due to missing documentaion of HDMI PHY, we know correct
|
||||
* settings only for following four PHY dividers. Select one
|
||||
* based on clock speed.
|
||||
*/
|
||||
if (clock <= 27000000)
|
||||
return 11;
|
||||
else if (clock <= 74250000)
|
||||
return 4;
|
||||
else if (clock <= 148500000)
|
||||
return 2;
|
||||
else
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void sunxi_dw_hdmi_phy_init(void)
|
||||
{
|
||||
struct sunxi_hdmi_phy * const phy =
|
||||
(struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
|
||||
unsigned long tmo;
|
||||
u32 tmp;
|
||||
|
||||
/*
|
||||
* HDMI PHY settings are taken as-is from Allwinner BSP code.
|
||||
* There is no documentation.
|
||||
*/
|
||||
writel(0, &phy->ctrl);
|
||||
setbits_le32(&phy->ctrl, BIT(0));
|
||||
udelay(5);
|
||||
setbits_le32(&phy->ctrl, BIT(16));
|
||||
setbits_le32(&phy->ctrl, BIT(1));
|
||||
udelay(10);
|
||||
setbits_le32(&phy->ctrl, BIT(2));
|
||||
udelay(5);
|
||||
setbits_le32(&phy->ctrl, BIT(3));
|
||||
udelay(40);
|
||||
setbits_le32(&phy->ctrl, BIT(19));
|
||||
udelay(100);
|
||||
setbits_le32(&phy->ctrl, BIT(18));
|
||||
setbits_le32(&phy->ctrl, 7 << 4);
|
||||
|
||||
/* Note that Allwinner code doesn't fail in case of timeout */
|
||||
tmo = timer_get_us() + 2000;
|
||||
while ((readl(&phy->status) & 0x80) == 0) {
|
||||
if (timer_get_us() > tmo) {
|
||||
printf("Warning: HDMI PHY init timeout!\n");
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
setbits_le32(&phy->ctrl, 0xf << 8);
|
||||
setbits_le32(&phy->ctrl, BIT(7));
|
||||
|
||||
writel(0x39dc5040, &phy->pll);
|
||||
writel(0x80084343, &phy->clk);
|
||||
udelay(10000);
|
||||
writel(1, &phy->unk3);
|
||||
setbits_le32(&phy->pll, BIT(25));
|
||||
udelay(100000);
|
||||
tmp = (readl(&phy->status) & 0x1f800) >> 11;
|
||||
setbits_le32(&phy->pll, BIT(31) | BIT(30));
|
||||
setbits_le32(&phy->pll, tmp);
|
||||
writel(0x01FF0F7F, &phy->ctrl);
|
||||
writel(0x80639000, &phy->unk1);
|
||||
writel(0x0F81C405, &phy->unk2);
|
||||
|
||||
/* enable read access to HDMI controller */
|
||||
writel(0x54524545, &phy->read_en);
|
||||
/* descramble register offsets */
|
||||
writel(0x42494E47, &phy->unscramble);
|
||||
}
|
||||
|
||||
static int sunxi_dw_hdmi_get_plug_in_status(void)
|
||||
{
|
||||
struct sunxi_hdmi_phy * const phy =
|
||||
(struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
|
||||
|
||||
return !!(readl(&phy->status) & (1 << 19));
|
||||
}
|
||||
|
||||
static int sunxi_dw_hdmi_wait_for_hpd(void)
|
||||
{
|
||||
ulong start;
|
||||
|
||||
start = get_timer(0);
|
||||
do {
|
||||
if (sunxi_dw_hdmi_get_plug_in_status())
|
||||
return 0;
|
||||
udelay(100);
|
||||
} while (get_timer(start) < 300);
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
static void sunxi_dw_hdmi_phy_set(uint clock)
|
||||
{
|
||||
struct sunxi_hdmi_phy * const phy =
|
||||
(struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
|
||||
int div = sunxi_dw_hdmi_get_divider(clock);
|
||||
u32 tmp;
|
||||
|
||||
/*
|
||||
* Unfortunately, we don't know much about those magic
|
||||
* numbers. They are taken from Allwinner BSP driver.
|
||||
*/
|
||||
switch (div) {
|
||||
case 1:
|
||||
writel(0x30dc5fc0, &phy->pll);
|
||||
writel(0x800863C0, &phy->clk);
|
||||
mdelay(10);
|
||||
writel(0x00000001, &phy->unk3);
|
||||
setbits_le32(&phy->pll, BIT(25));
|
||||
mdelay(200);
|
||||
tmp = (readl(&phy->status) & 0x1f800) >> 11;
|
||||
setbits_le32(&phy->pll, BIT(31) | BIT(30));
|
||||
if (tmp < 0x3d)
|
||||
setbits_le32(&phy->pll, tmp + 2);
|
||||
else
|
||||
setbits_le32(&phy->pll, 0x3f);
|
||||
mdelay(100);
|
||||
writel(0x01FFFF7F, &phy->ctrl);
|
||||
writel(0x8063b000, &phy->unk1);
|
||||
writel(0x0F8246B5, &phy->unk2);
|
||||
break;
|
||||
case 2:
|
||||
writel(0x39dc5040, &phy->pll);
|
||||
writel(0x80084381, &phy->clk);
|
||||
mdelay(10);
|
||||
writel(0x00000001, &phy->unk3);
|
||||
setbits_le32(&phy->pll, BIT(25));
|
||||
mdelay(100);
|
||||
tmp = (readl(&phy->status) & 0x1f800) >> 11;
|
||||
setbits_le32(&phy->pll, BIT(31) | BIT(30));
|
||||
setbits_le32(&phy->pll, tmp);
|
||||
writel(0x01FFFF7F, &phy->ctrl);
|
||||
writel(0x8063a800, &phy->unk1);
|
||||
writel(0x0F81C485, &phy->unk2);
|
||||
break;
|
||||
case 4:
|
||||
writel(0x39dc5040, &phy->pll);
|
||||
writel(0x80084343, &phy->clk);
|
||||
mdelay(10);
|
||||
writel(0x00000001, &phy->unk3);
|
||||
setbits_le32(&phy->pll, BIT(25));
|
||||
mdelay(100);
|
||||
tmp = (readl(&phy->status) & 0x1f800) >> 11;
|
||||
setbits_le32(&phy->pll, BIT(31) | BIT(30));
|
||||
setbits_le32(&phy->pll, tmp);
|
||||
writel(0x01FFFF7F, &phy->ctrl);
|
||||
writel(0x8063b000, &phy->unk1);
|
||||
writel(0x0F81C405, &phy->unk2);
|
||||
break;
|
||||
case 11:
|
||||
writel(0x39dc5040, &phy->pll);
|
||||
writel(0x8008430a, &phy->clk);
|
||||
mdelay(10);
|
||||
writel(0x00000001, &phy->unk3);
|
||||
setbits_le32(&phy->pll, BIT(25));
|
||||
mdelay(100);
|
||||
tmp = (readl(&phy->status) & 0x1f800) >> 11;
|
||||
setbits_le32(&phy->pll, BIT(31) | BIT(30));
|
||||
setbits_le32(&phy->pll, tmp);
|
||||
writel(0x01FFFF7F, &phy->ctrl);
|
||||
writel(0x8063b000, &phy->unk1);
|
||||
writel(0x0F81C405, &phy->unk2);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static void sunxi_dw_hdmi_pll_set(uint clk_khz)
|
||||
{
|
||||
int value, n, m, div = 0, diff;
|
||||
int best_n = 0, best_m = 0, best_diff = 0x0FFFFFFF;
|
||||
|
||||
div = sunxi_dw_hdmi_get_divider(clk_khz * 1000);
|
||||
|
||||
/*
|
||||
* Find the lowest divider resulting in a matching clock. If there
|
||||
* is no match, pick the closest lower clock, as monitors tend to
|
||||
* not sync to higher frequencies.
|
||||
*/
|
||||
for (m = 1; m <= 16; m++) {
|
||||
n = (m * div * clk_khz) / 24000;
|
||||
|
||||
if ((n >= 1) && (n <= 128)) {
|
||||
value = (24000 * n) / m / div;
|
||||
diff = clk_khz - value;
|
||||
if (diff < best_diff) {
|
||||
best_diff = diff;
|
||||
best_m = m;
|
||||
best_n = n;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
clock_set_pll3_factors(best_m, best_n);
|
||||
debug("dotclock: %dkHz = %dkHz: (24MHz * %d) / %d / %d\n",
|
||||
clk_khz, (clock_get_pll3() / 1000) / div,
|
||||
best_n, best_m, div);
|
||||
}
|
||||
|
||||
static void sunxi_dw_hdmi_lcdc_init(int mux, const struct display_timing *edid,
|
||||
int bpp)
|
||||
{
|
||||
struct sunxi_ccm_reg * const ccm =
|
||||
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
|
||||
int div = sunxi_dw_hdmi_get_divider(edid->pixelclock.typ);
|
||||
struct sunxi_lcdc_reg *lcdc;
|
||||
|
||||
if (mux == 0) {
|
||||
lcdc = (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
|
||||
|
||||
/* Reset off */
|
||||
setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);
|
||||
|
||||
/* Clock on */
|
||||
setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);
|
||||
writel(CCM_LCD0_CTRL_GATE | CCM_LCD0_CTRL_M(div),
|
||||
&ccm->lcd0_clk_cfg);
|
||||
} else {
|
||||
lcdc = (struct sunxi_lcdc_reg *)SUNXI_LCD1_BASE;
|
||||
|
||||
/* Reset off */
|
||||
setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD1);
|
||||
|
||||
/* Clock on */
|
||||
setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD1);
|
||||
writel(CCM_LCD1_CTRL_GATE | CCM_LCD1_CTRL_M(div),
|
||||
&ccm->lcd1_clk_cfg);
|
||||
}
|
||||
|
||||
lcdc_init(lcdc);
|
||||
lcdc_tcon1_mode_set(lcdc, edid, false, false);
|
||||
lcdc_enable(lcdc, bpp);
|
||||
}
|
||||
|
||||
static int sunxi_dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock)
|
||||
{
|
||||
sunxi_dw_hdmi_pll_set(mpixelclock/1000);
|
||||
sunxi_dw_hdmi_phy_set(mpixelclock);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sunxi_dw_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size)
|
||||
{
|
||||
struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
|
||||
|
||||
return dw_hdmi_read_edid(&priv->hdmi, buf, buf_size);
|
||||
}
|
||||
|
||||
static int sunxi_dw_hdmi_enable(struct udevice *dev, int panel_bpp,
|
||||
const struct display_timing *edid)
|
||||
{
|
||||
struct sunxi_hdmi_phy * const phy =
|
||||
(struct sunxi_hdmi_phy *)(SUNXI_HDMI_BASE + HDMI_PHY_OFFS);
|
||||
struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
|
||||
int ret;
|
||||
|
||||
ret = dw_hdmi_enable(&priv->hdmi, edid);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
sunxi_dw_hdmi_lcdc_init(priv->mux, edid, panel_bpp);
|
||||
|
||||
/*
|
||||
* Condition in original code is a bit weird. This is attempt
|
||||
* to make it more reasonable and it works. It could be that
|
||||
* bits and conditions are related and should be separated.
|
||||
*/
|
||||
if (!((edid->flags & DISPLAY_FLAGS_HSYNC_HIGH) &&
|
||||
(edid->flags & DISPLAY_FLAGS_VSYNC_HIGH))) {
|
||||
setbits_le32(&phy->pol, 0x300);
|
||||
}
|
||||
|
||||
setbits_le32(&phy->ctrl, 0xf << 12);
|
||||
|
||||
/*
|
||||
* This is last hdmi access before boot, so scramble addresses
|
||||
* again or othwerwise BSP driver won't work. Dummy read is
|
||||
* needed or otherwise last write doesn't get written correctly.
|
||||
*/
|
||||
(void)readb(SUNXI_HDMI_BASE);
|
||||
writel(0, &phy->unscramble);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sunxi_dw_hdmi_probe(struct udevice *dev)
|
||||
{
|
||||
struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
|
||||
struct sunxi_dw_hdmi_priv *priv = dev_get_priv(dev);
|
||||
struct sunxi_ccm_reg * const ccm =
|
||||
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
|
||||
int ret;
|
||||
|
||||
/* Set pll3 to 297 MHz */
|
||||
clock_set_pll3(297000000);
|
||||
|
||||
/* Set hdmi parent to pll3 */
|
||||
clrsetbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_PLL_MASK,
|
||||
CCM_HDMI_CTRL_PLL3);
|
||||
|
||||
/* Set ahb gating to pass */
|
||||
setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);
|
||||
setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI2);
|
||||
setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);
|
||||
setbits_le32(&ccm->hdmi_slow_clk_cfg, CCM_HDMI_SLOW_CTRL_DDC_GATE);
|
||||
|
||||
/* Clock on */
|
||||
setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);
|
||||
|
||||
sunxi_dw_hdmi_phy_init();
|
||||
|
||||
ret = sunxi_dw_hdmi_wait_for_hpd();
|
||||
if (ret < 0) {
|
||||
debug("hdmi can not get hpd signal\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
priv->hdmi.ioaddr = SUNXI_HDMI_BASE;
|
||||
priv->hdmi.i2c_clk_high = 0xd8;
|
||||
priv->hdmi.i2c_clk_low = 0xfe;
|
||||
priv->hdmi.reg_io_width = 1;
|
||||
priv->hdmi.phy_set = sunxi_dw_hdmi_phy_cfg;
|
||||
priv->mux = uc_plat->source_id;
|
||||
|
||||
dw_hdmi_init(&priv->hdmi);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dm_display_ops sunxi_dw_hdmi_ops = {
|
||||
.read_edid = sunxi_dw_hdmi_read_edid,
|
||||
.enable = sunxi_dw_hdmi_enable,
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(sunxi_dw_hdmi) = {
|
||||
.name = "sunxi_dw_hdmi",
|
||||
.id = UCLASS_DISPLAY,
|
||||
.ops = &sunxi_dw_hdmi_ops,
|
||||
.probe = sunxi_dw_hdmi_probe,
|
||||
.priv_auto_alloc_size = sizeof(struct sunxi_dw_hdmi_priv),
|
||||
};
|
||||
|
||||
U_BOOT_DEVICE(sunxi_dw_hdmi) = {
|
||||
.name = "sunxi_dw_hdmi"
|
||||
};
|
||||
|
|
@ -475,6 +475,11 @@ extern int soft_i2c_gpio_scl;
|
|||
#define CONSOLE_STDOUT_SETTINGS \
|
||||
"stdout=serial,vga\0" \
|
||||
"stderr=serial,vga\0"
|
||||
#elif CONFIG_DM_VIDEO
|
||||
#define CONFIG_SYS_WHITE_ON_BLACK
|
||||
#define CONSOLE_STDOUT_SETTINGS \
|
||||
"stdout=serial,vidconsole\0" \
|
||||
"stderr=serial,vidconsole\0"
|
||||
#else
|
||||
#define CONSOLE_STDOUT_SETTINGS \
|
||||
"stdout=serial\0" \
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue