Commit graph

14490 commits

Author SHA1 Message Date
Julien Béraud
97b262758b gpio: altera_pio: fix get_value
gpio_get_value should return 0 or 1, not the value of bit & (1 << pin)

Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Julien Beraud <julien.beraud@orolia.com>
2019-02-25 16:07:36 +01:00
Tom Rini
888f9aa5ca Merge branch 'master' of git://git.denx.de/u-boot-tegra 2019-02-20 12:28:57 -05:00
Tom Rini
0c41e59a37 Merge git://git.denx.de/u-boot-x86
- Add support for sound.

Albeit the big changeset, changes are pretty limited to x86 only and a
few new sound drivers used by x86 so I think it would be good to have
this in the next release.
2019-02-20 12:28:40 -05:00
Tom Rini
176b32cd4f Merge git://git.denx.de/u-boot-fsl-qoriq
- Support of NXP's LX2160RDB and LX2160QDS platform
- Enable SATA DM model for NXP's ARM SoCs
2019-02-20 12:26:05 -05:00
Peter Robinson
06b070e323 Kconfig: tegra: Migrate TEGRA_KEYBOARD
Migrate TEGRA_KEYBOARD from headers to Kconfig, only the seaboard uses it but we
drop CONFIG_KEYBOARD as the driver doesn't use the legacy drv_keyboard_init.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2019-02-20 09:01:45 -07:00
Peter Robinson
747fed56d3 Kconfig: tegra: Migrate USB_EHCI_TEGRA
Migrate USB_EHCI_TEGRA from headers to Kconfig

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Peter.Chubb@data61.csiro.au
Cc: Lucas Stach <dev@lynxeye.de>
Cc: Stefan Agner <stefan.agner@toradex.com>
Cc: Alban Bedel <alban.bedel@avionic-design.de>
Cc: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2019-02-20 09:01:44 -07:00
Peter Robinson
02253d4d12 Kconfig: tegra: Migrate SYS_I2C_TEGRA
Migrate SYS_I2C_TEGRA from headers to Kconfig

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Stephen Warren <swarren@nvidia.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Peter.Chubb@data61.csiro.au
Cc: Lucas Stach <dev@lynxeye.de>
Cc: Stefan Agner <stefan.agner@toradex.com>
Cc: Alban Bedel <alban.bedel@avionic-design.de>
Cc: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2019-02-20 09:01:44 -07:00
Simon Glass
e2c901c99e x86: Add sound support for samus
Enable sound on samus using the broadwell I2S and an RT5677 audio codec.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2019-02-20 15:27:11 +08:00
Simon Glass
7b96c6c89a x86: sound: Add sound support for samus (broadwell)
Add a sound driver for samus which ties together the audio codec and
I2S controller.

For now broadwell_sound is commented out in the makefile since we cannot
compile it without sound support enabled. The next commit fixes this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20 15:27:11 +08:00
Simon Glass
cf885929a6 sound: Add a driver for RealTek RT5677
This audio codec is used on samus. Add a driver for it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20 15:27:11 +08:00
Simon Glass
cbdfe59918 x86: sound: Add support for broadwell I2S
I2S is used to send digital audio data to an audio codec. Add support for
this on broadwell.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20 15:27:11 +08:00
Simon Glass
6a27e540de sound: Add a driver for the i8254 beep
Add a sound driver which can output simple beeps using this legacy timer.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20 15:27:10 +08:00
Simon Glass
6744c0d652 sound: x86: link: Add sound support
Add sound support for link, using the HDA codec implementation.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20 15:27:09 +08:00
Simon Glass
ecc7973d1c sandbox: sound: Silence sound for testing
When testing the sound system we don't need the hear the beeps. The
testing works by checking the data that would be emitted. Add a
device-tree property to silence the sound, and enable it for testing.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20 15:27:09 +08:00
Simon Glass
2ca471379b sound: Add support for Intel HDA
The Intel High-definition Audio is a newer-generation audio system which
provides for transfer of a large number of audio stream, each containing
up to 16 channels.

Add support for HDA as a library which can be used by other drivers.
U-Boot currently uses only two channels (stereo).

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20 15:27:09 +08:00
Simon Glass
2850266965 sound: Add uclass operations for beeping
Some audio codecs such as Intel HDA do not need to use digital data to
play sounds, but instead have a way to emit beeps. Add this interface as
an option. If the beep interface is not supported, then the sound uclass
falls back to the I2S interface.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20 15:27:08 +08:00
Simon Glass
e65f9ef9f2 sound: Mark sound_setup() as optional
This method in the sound API is optional since some drivers can do this
when probing or as part of SoC init. Mark it as such.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20 15:27:08 +08:00
Simon Glass
1260f8c0ef pch: Add ioctl support
At present the PCH has 4 operations and these are reasonably widely used
in the drivers. But sometimes we want to add rarely used operations, and
each of these currently adds to the size of the PCH operations table.

Add an ioctl() method which can be easily expanded without any more impact
on the operations table.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20 15:27:08 +08:00
Simon Glass
b45c833c71 sandbox: pch: Add a test for the PCH uclass
This uclass currently has no tests. Add a sandbox driver and some simple
tests to provide basic coverage.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: Use "sandbox,pch" for the compatible string, for consistency]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20 15:26:36 +08:00
Simon Glass
c882163b09 x86: sandbox: pch: Add a CONFIG option for PCH
At present this uclass is selected only on x86. In order to add a test for
it, it must also support sandbox. Create a new CONFIG_PCH option and
enable it on x86 and sandbox.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20 15:25:30 +08:00
Simon Glass
11503be448 pci: Don't export pci_hose_config_device()
This function is not used outside this file so make it static.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20 15:21:44 +08:00
Simon Glass
2b5d029db8 i2c: designware: Add error checking on init
At present this driver does not check whether it is able to actually
communicate with the I2C controller. It prints a timeout message but still
considers the probe to be successful.

To fix this, add some checking that the init succeeds.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-02-20 15:21:44 +08:00
Simon Glass
529f57d926 dm: syscon: Don't require a regmap for PCI devices
At present it is not possible to use the syscon devices for PCI devices
since a regmap is required. Since PCI uses a 3-cell address the conversion
of the 'reg' property to an address always fails. In any case, the regmap
is not useful with PCI since devices are accessed through the PCI bus
which regmap does not support.

Add a special case for PCI syscon devices, so that they don't set up a
regmap.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-20 15:21:44 +08:00
Heinrich Schuchardt
90037d4c73 dm: scsi: report correct device number
Before the patch scsi would report the same device number for all SCSI
devices, e.g.

  Device 0: (1:0) Vendor: ATA Prod.: Crucial_CT128M55 Rev: MU01
            Type: Hard Disk
            Capacity: 122104.3 MB = 119.2 GB (250069680 x 512)
  Device 0: (1:0) Vendor: ATA Prod.:  Rev:
            Type: Hard Disk
            Capacity: not available

With the patch the same device number is reported as is used in
scsi_read():

  Device 0: (1:0) Vendor: ATA Prod.: Crucial_CT128M55 Rev: MU01
            Type: Hard Disk
            Capacity: 122104.3 MB = 119.2 GB (250069680 x 512)
  Device 1: (1:0) Vendor: ATA Prod.:  Rev:
            Type: Hard Disk
            Capacity: not available

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2019-02-19 08:55:43 -05:00
Priyanka Jain
50dcbd1ff8 drivers/ddr/fsl: Update fsl_ddr_board_options as weak function
fsl_ddr_board_options is generally defined in board
board's ddr.c, but some boards like lx2160ardb board
does not need this function.
Defining fsl_ddr_board_options as weak function to
resolve compilation errors for such boards.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
[PK: Fix checkpatch warnings]
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-02-19 10:26:43 +05:30
Tom Rini
b78a9e2212 Merge branch 'master' of git://git.denx.de/u-boot-socfpga
- Misc Gen5 fixes
- stratix10 bugfix
- dwmmc bugfix
2019-02-18 22:12:59 -05:00
Ang, Chee Hong
5097ba6177 ARM: socfpga: stratix10: Return valid error code from FPGA driver
This patch prevent the Stratix 10 FPGA driver incorrectly return the
transaction ID as the mailbox error code. It should always return the
actual mailbox error code from SDM firmware.

Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
2019-02-18 13:00:54 +01:00
Ley Foon Tan
7997599e2d mmc: dwmmc: Poll for iDMAC TX/RX interrupt
Poll for iDMAC TX/RX interrupt before disable DMA.
This to prevent disable DMA before data is transfer
completed.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2019-02-18 13:00:54 +01:00
Simon Goldschmidt
6fb1eb1b76 arm: socfpga: gen5 enable designware_socfpga
Enable the socfpga specific designware ethernet driver by default for
socfpga by implying it when enabling CONFIG_ETH_DESIGNWARE for a
MACH_SOCFPGA config.

This is required to remove the hacky reset and phy mode handling in
arch/arm/mach-socfpga.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-02-18 13:00:53 +01:00
Simon Goldschmidt
4f1267cea1 net: designware: socfpga: adapt to Gen5
This driver was written for Arria10, but it applies to Gen5, too.

The main difference is that Gen5 has 2 MACs (Arria10 has 3) and the
syscon bits are encoded in the same register, thus an offset is needed.

This offset is already read from the devicetree, but for Arria10 it is
always 0, which is probably why it has been ignored. By using this
offset when writing the phy mode into the syscon regiter, we can use
this driver to set the phy mode for both of the MACs on Gen5.

Since the PHY mode bits in sysmgr are the same even for Stratix10,
let's drop the detection of the sub-mach by checking compatible
version and just use the same code for all FPGAs.

To work correctly, this driver depends on SYSCON and REGMAP, so select
those via Kconfig when it is enabeld.

Tested on socfpga_socrates (where the 2nd MAC is connected, so a shift
offset is required).

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-02-18 13:00:53 +01:00
Tom Rini
500ad54e35 - sunxi display DDC probe fallback
- support 24bpp BMP files on 16bpp displays
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Merge tag 'video-for-2019.04-rc2' of git://git.denx.de/u-boot-video

- sunxi display DDC probe fallback
- support 24bpp BMP files on 16bpp displays
2019-02-16 18:10:53 -05:00
Tom Rini
7a2ab3778c Merge branch 'master' of git://git.denx.de/u-boot-sh
- Various MMC fixes
2019-02-16 17:05:51 -05:00
Marek Vasut
261445dfaf mmc: tmio: sdhi: Configure DT2FF register for HS400 mode
The DT2FF register must be configured differently for HS400 mode
and for HS200/SDR104 mode. Configure the DT2FF register according
to the recommended datasheet settings for each mode.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-02-16 18:12:17 +01:00
Marek Vasut
4c80f111c0 mmc: tmio: Configure HOST_MODE WMODE according to bus width
Set the HOST_MODE register WMODE bit according to the SDHI bus width,
that is 0 for 64bit bus and 1 for 16/32bit bus.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-02-16 18:12:17 +01:00
Marek Vasut
fceea99268 mmc: Downgrade SD/MMC from UHS/HS200/HS400 modes before boot
Older kernel versions or systems which do not connect eMMC reset line
properly may not be able to handle situations where either the eMMC
is left in HS200/HS400 mode or SD card in UHS modes by the bootloader
and may misbehave. Downgrade the eMMC to HS/HS52 mode and/or SD card
to non-UHS mode before booting the kernel to allow such older kernels
to work with modern U-Boot.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
2019-02-16 18:12:17 +01:00
Tom Rini
b89074f650 u-boot-imx-2019-02-16
---------------------
 
 - vhybrid: add calibration
 - gw_ventana: fixes
 - Improve documentation for Secure Boot (HABv4)
 - Fix Marvell Switch
 - MX6 Sabre, switch to DM
 - Fixes for NAND
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Merge tag 'u-boot-imx-2019-02-16' of git://git.denx.de/u-boot-imx

u-boot-imx-2019-02-16
---------------------

- vhybrid: add calibration
- gw_ventana: fixes
- Improve documentation for Secure Boot (HABv4)
- Fix Marvell Switch
- MX6 Sabre, switch to DM
- Fixes for NAND
2019-02-16 08:31:05 -05:00
Max Krummenacher
a24532083c imx: serial_mxc: disable ri and dcd irq in dte mode
If the UART is used in DTE mode the RI and DCD bits in UCR3 become
irq enable bits. Both are set to enabled after reset and both likely
are pending.

Disable the bits to prevent an interrupt storm when Linux enables
the UART interrupts.

Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2019-02-15 22:01:15 +01:00
Abel Vesa
d76706c89a mmc: fsl_esdhc: Fix DM_REGULATOR ifdefs for SPL builds
Since the fsl_esdhc will also be used by SPL, make the
preprocessor switches more generic to allow any kind of build.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-02-15 22:01:15 +01:00
Abel Vesa
921208ebca usb: ehci-mx6: Make regulator DM_REGULATOR dependent
Do the regulator related work only if the build has the DM_REGULATOR.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-02-15 22:01:15 +01:00
Stefan Roese
e25710305d video: bmp: Add support for 24bpp BMP files on 16bpp displays
This patch adds support to load 24bpp BMP files on 16bpp displays. This
will be used by the theadorable board. The "old" bmp command did support
this operartion mode and to not break compatibility with the move to
DM_VIDEO, we need to add this support to the "new" bmp code.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>
2019-02-15 16:51:12 +01:00
Priit Laes
0220f8c223 sunxi: display: Implement fallback to ddc probe when hpd fails
There are HDMI displays where hpd pin is not connected, thus
we cannot get it to work unless we specifically set the resolution.

Rework the display probing, so hotplug detect failure causes
fallback to probing ddc for EDID data.

Signed-off-by: Priit Laes <priit.laes@paf.com>
2019-02-15 16:30:44 +01:00
Priit Laes
361604d658 sunxi: display: Move DDC PLL setup to HDMI init
Move PLL initialization code to single place so
we won't call it every time we query for EDID data.

Signed-off-by: Priit Laes <priit.laes@paf.com>
2019-02-15 16:28:58 +01:00
Tim Harvey
69280961d7 net: mv88e61xx: fix autonegotiation on ports
phy_reset should be called before autoneg is setup

The only boards using MV88E61XX_SWITCH are:
 - alliedtelesis/SBx81LIFKW
 - alliedtelesis/SBx81LIFXCAT
 - gateworks/gw_ventana

Cc: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
2019-02-15 13:01:28 +01:00
Adam Ford
04568bd0b6 MTD: nand: mxs_nand: Allow driver to auto setup ECC in SPL
The initialization of the NAND in SPL hard-coded ecc.bytes,
ecc.size, and ecc.strength which may work for some NAND parts,
but it not appropriate for others.  With the pending patch
"mxs_nand: Fix BCH read timeout error on boards requiring ECC"
the driver can auto configure the ECC when these entries are
blank.  This patch has been tested in NAND flash with oob 64
and oob 128.

Signed-off-by: Adam Ford <aford173@gmail.com>
Tested-by: Jörg Krause <joerg.krause@embedded.rocks>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Tested-by: Tim Harvey <tharvey@gateworks.com>
2019-02-15 12:42:13 +01:00
Adam Ford
8f1a5ac797 net: dm: fec: Fix regulator enable when using DM_REGULATOR
When DM_REGULATOR is enabled, the driver attempts to call
regulator_autoset() which expects the regulators to be on at boot
and/or always on and fails if they are not true.
For a more generic approach, this patch just calls
regulator_set_enable() which shouldn't have such restrictions.

Fixes: ad8c43cbca ("net: dm: fec: Support the phy-supply
binding")

Signed-off-by: Adam Ford <aford173@gmail.com>
Tested-by: Martin Fuzzey <martin.fuzzey@flowbird.group>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2019-02-15 12:41:12 +01:00
Adam Ford
5645df9e00 MTD: NAND: mxs_nand_init_dma: Make mxs_nand_init_dma static
mxs_nand_init_dma is only referenced from mxs_nand.c.  It's not
referenced in any headers or outside code, so this patch
defines it as static.

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-02-15 12:36:44 +01:00
Adam Ford
5ae585ba3a MTD: mxs_nand: Fix BCH read timeout error on boards requiring ECC
The LogicPD board uses a Micron Flash with ECC.  To boot this from
SPL, the ECC needs to be correctly configured or the BCH engine
times out.

Signed-off-by: Adam Ford <aford173@gmail.com>
Acked-by: Stefan Agner <stefan.agner@toradex.com>
Tested-by: Jörg Krause <joerg.krause@embedded.rocks>
Acked-by: Tim Harvey <tharvey@gateworks.com>
Tested-by: Tim Harvey <tharvey@gateworks.com>
2019-02-15 12:36:08 +01:00
Michal Simek
027b1134b2 xilinx: common: Remove !DM_i2C code for reading mac from eeprom
All platforms are converted to DM_I2C that's why there is no reason to
keep this code here.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-02-14 14:31:10 +01:00
Michal Simek
f88185bcc3 i2c: Remove ancient zynq_i2c driver
This driver is replaced by drivers/i2c/i2c-cdns.c DM based driver.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Heiko Schocher <hs@denx.de>
2019-02-14 14:31:10 +01:00
Michal Simek
f3976cc61f spi: zynqmp_gqspi: Enable versal compatible string
Trivial patch.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-02-14 14:31:09 +01:00
Bernhard Messerklinger
ca7db866fe x86: tsc: Add support for native calibration of TSC freq
Add native tsc calibration function. Calibrate the tsc timer the same
way as linux does in arch/x86/kernel/tsc.c.

Fixes booting for Apollo Lake processors.

Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-12 14:37:16 +08:00
Tom Rini
f94fa0e94f Merge branch 'master' of git://git.denx.de/u-boot-i2c
- DM I2C improvements
2019-02-11 11:15:34 -05:00
Baruch Siach
6664a0e5f3 pcie: designware: mvebu: fix reset release polarity
The dm_gpio_set_value() routine sets signal logical level, with
GPIO_ACTIVE_LOW/HIGH value taken into account. Reset active value is 1
(asserted), while reset inactive value is 0 (de-asserted). Fix the reset
toggle code to set the correct reset logic value.

Reported-by: Sven Auhagen <sven.auhagen@voleatech.de>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2019-02-11 09:39:12 +01:00
Michal Simek
c4bd12a7da i2c: mux: Generate longer i2c mux name
For !DM case busses are listed as
ZynqMP> i2c bus
Bus 0:	zynq_0
Bus 1:	zynq_0->PCA9544A@0x75:0
Bus 2:	zynq_0->PCA9544A@0x75:1
Bus 3:	zynq_0->PCA9544A@0x75:2
Bus 4:	zynq_1
Bus 5:	zynq_1->PCA9548@0x74:0
Bus 6:	zynq_1->PCA9548@0x74:1
Bus 7:	zynq_1->PCA9548@0x74:2
Bus 8:	zynq_1->PCA9548@0x74:3
Bus 9:	zynq_1->PCA9548@0x74:4
Bus 10:	zynq_1->PCA9548@0x75:0
Bus 11:	zynq_1->PCA9548@0x75:1
Bus 12:	zynq_1->PCA9548@0x75:2
Bus 13:	zynq_1->PCA9548@0x75:3
Bus 14:	zynq_1->PCA9548@0x75:4
Bus 15:	zynq_1->PCA9548@0x75:5
Bus 16:	zynq_1->PCA9548@0x75:6
Bus 17:	zynq_1->PCA9548@0x75:7

where is exactly describing i2c bus topology.
By moving to DM case i2c mux buses are using names from DT and because
i2c-muxes describing sub busses with the same names like i2c@0, etc it
is hard to identify which bus is where.
Linux is adding topology information to i2c-mux busses to identify them
better.
This patch is doing the same and composing bus name with topology
information.

When patch is applied with topology information on zcu102-revA.
ZynqMP> i2c bus
Bus 0:	i2c@ff020000
   20: gpio@20, offset len 1, flags 0
   21: gpio@21, offset len 1, flags 0
   75: i2c-mux@75, offset len 1, flags 0
Bus 2:	i2c@ff020000->i2c-mux@75->i2c@0
Bus 3:	i2c@ff020000->i2c-mux@75->i2c@1
Bus 4:	i2c@ff020000->i2c-mux@75->i2c@2
Bus 1:	i2c@ff030000  (active 1)
   74: i2c-mux@74, offset len 1, flags 0
   75: i2c-mux@75, offset len 1, flags 0
Bus 5:	i2c@ff030000->i2c-mux@74->i2c@0  (active 5)
   54: eeprom@54, offset len 1, flags 0
Bus 6:	i2c@ff030000->i2c-mux@74->i2c@1
Bus 7:	i2c@ff030000->i2c-mux@74->i2c@2
Bus 8:	i2c@ff030000->i2c-mux@74->i2c@3
Bus 9:	i2c@ff030000->i2c-mux@74->i2c@4
Bus 10:	i2c@ff030000->i2c-mux@75->i2c@0
Bus 11:	i2c@ff030000->i2c-mux@75->i2c@1
Bus 12:	i2c@ff030000->i2c-mux@75->i2c@2
Bus 13:	i2c@ff030000->i2c-mux@75->i2c@3
Bus 14:	i2c@ff030000->i2c-mux@75->i2c@4
Bus 15:	i2c@ff030000->i2c-mux@75->i2c@5
Bus 16:	i2c@ff030000->i2c-mux@75->i2c@6
Bus 17:	i2c@ff030000->i2c-mux@75->i2c@7

Behavior before the patch is applied.
ZynqMP> i2c bus
Bus 0:	i2c@ff020000
   20: gpio@20, offset len 1, flags 0
   21: gpio@21, offset len 1, flags 0
   75: i2c-mux@75, offset len 1, flags 0
Bus 2:	i2c@0
Bus 3:	i2c@1
Bus 4:	i2c@2
Bus 1:	i2c@ff030000  (active 1)
   74: i2c-mux@74, offset len 1, flags 0
   75: i2c-mux@75, offset len 1, flags 0
Bus 5:	i2c@0  (active 5)
   54: eeprom@54, offset len 1, flags 0
Bus 6:	i2c@1
Bus 7:	i2c@2
Bus 8:	i2c@3
Bus 9:	i2c@4
Bus 10:	i2c@0
Bus 11:	i2c@1
Bus 12:	i2c@2
Bus 13:	i2c@3
Bus 14:	i2c@4
Bus 15:	i2c@5
Bus 16:	i2c@6
Bus 17:	i2c@7

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-02-11 09:38:23 +01:00
Michal Simek
61607225d1 i2c: Fill req_seq in i2c_post_bind()
For i2c controllers which are missing alias in DT there is no req_seq
setup. This function is setting up proper ID based on highest found
alias ID.

On zcu102 this is the behavior when patch is applied.
ZynqMP> i2c bus
Bus 0:	i2c@ff020000
   20: gpio@20, offset len 1, flags 0
   21: gpio@21, offset len 1, flags 0
   75: i2c-mux@75, offset len 1, flags 0
Bus 2:	i2c@0
Bus 3:	i2c@1
Bus 4:	i2c@2
Bus 1:	i2c@ff030000  (active 1)
   74: i2c-mux@74, offset len 1, flags 0
   75: i2c-mux@75, offset len 1, flags 0
Bus 5:	i2c@0  (active 5)
   54: eeprom@54, offset len 1, flags 0
Bus 6:	i2c@1
Bus 7:	i2c@2
Bus 8:	i2c@3
Bus 9:	i2c@4
Bus 10:	i2c@0
Bus 11:	i2c@1
Bus 12:	i2c@2
Bus 13:	i2c@3
Bus 14:	i2c@4
Bus 15:	i2c@5
Bus 16:	i2c@6
Bus 17:	i2c@7

Before this patch applied (controllers have -1 ID)
ZynqMP> i2c bus
Bus 0:	i2c@ff020000
   20: gpio@20, offset len 1, flags 0
   21: gpio@21, offset len 1, flags 0
   75: i2c-mux@75, offset len 1, flags 0
Bus -1:	i2c@0
Bus -1:	i2c@1
Bus -1:	i2c@2
Bus 1:	i2c@ff030000  (active 1)
   74: i2c-mux@74, offset len 1, flags 0
   75: i2c-mux@75, offset len 1, flags 0
Bus -1:	i2c@0  (active 0)
   54: eeprom@54, offset len 1, flags 0
Bus -1:	i2c@1
Bus -1:	i2c@2
Bus -1:	i2c@3
Bus -1:	i2c@4
Bus -1:	i2c@0
Bus -1:	i2c@1
Bus -1:	i2c@2
Bus -1:	i2c@3
Bus -1:	i2c@4
Bus -1:	i2c@5
Bus -1:	i2c@6
Bus -1:	i2c@7

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-02-11 09:38:23 +01:00
Michal Simek
6bfacc8aad i2c: dm: Record maximum id of devices before probing devices
There is a need to find out the first free i2c ID which can be used for
i2s buses (including i2c buses connected to i2c mux). Do it early in
init and share this variable with other i2c classes for uniq bus
identification.

add from hs:
fix build problem in i2c-uclass.c for omap devices

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2019-02-11 09:37:27 +01:00
Tom Rini
dbe70c7d4e Merge branch 'master' of git://git.denx.de/u-boot-sh
- SD/MMC fixes and ext4 memory leak fix
2019-02-10 08:11:53 -05:00
Tom Rini
151b8339cc Samsung sound patches (applied for Samsung maintainer)
Common sound support
 buildman environment support
 of-platdata documentation improvements
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Merge tag 'dm-pull-10feb19' of git://git.denx.de/u-boot-dm

Samsung sound patches (applied for Samsung maintainer)
Common sound support
buildman environment support
of-platdata documentation improvements
2019-02-10 08:11:32 -05:00
Simon Glass
afcd645794 sound: Allow audio codecs to be used by other SoCs
At present there is still some samsung-specific code in the audio codecs.
Remove it so that these can be used by other SoCs.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-02-09 12:50:22 -07:00
Simon Glass
4a68a60e53 sound: samsung: Fix 'regiter' typo
Fix a typo that appears many times in this file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-02-09 12:50:22 -07:00
Simon Glass
e5d611671d misc: Allow child devices
Allow misc devices to have children, so that we can use this uclass for
cases where a child device (e.g. I2S) needs to access a misc driver for
transferring data.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-02-09 12:50:22 -07:00
Lokesh Vutla
d3de38554a mmc: omap_hsmmc: Use regulator_set_enable_if_allowed for enabling regulator
Use regulator_set_enable_if_allowed() api instead of regulator_set_enable()
while enabling io regulators. This way the driver doesn't see an error
when disabling an always-on regulator and when enabling is not supported.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-02-09 12:50:22 -07:00
Lokesh Vutla
cc4a224af2 power: regulator: Introduce regulator_set_enable_if_allowed api
regulator_set_enable() api throws an error in the following three cases:
- when requested to disable an always-on regulator
- when set_enable() ops not provided by regulator driver
- when enabling is actually failed.(Error returned by the regulator driver)

Sometimes consumer drivers doesn't want to track the first two scenarios
and just need to worry about the case where enabling is actually failed.
But it is also a good practice to have an error value returned in the
first two cases.

So introduce an api regulator_set_enable_if_allowed() which ignores the
first two error cases and returns an error as given by regulator driver.
Consumer drivers can use this api need not worry about the first two
error conditions.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-02-09 12:50:22 -07:00
Lokesh Vutla
f93fab3126 Revert "power: regulator: Return success on attempt to disable an always-on regulator"
This reverts commit e17e0ceb83.

It is advised to return an error when trying to disable an always-on
regulator and let the consumer driver handle the error if needed.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2019-02-09 12:50:22 -07:00
Simon Glass
e898799ce4 samsung: mmc: Drop old MMC init code
Now that these boards use driver model we can drop the old code. At
present s5p_mmc_init() is still used by goni and smdkv310 so cannot be
removed unless we remove those boards.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2019-02-09 12:50:22 -07:00
Simon Glass
9a7210f6a4 sound: Add a driver for max98088
This chip is used by spring. Add a driver for it and update the
samsung_sound driver to pick it up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2019-02-09 12:50:22 -07:00
Marcel Ziswiler
f388564965 dm: device: fail uclass_find_first_device() if list_empty
While uclass_find_device() fails with -ENODEV in case of list_empty
strangely uclass_find_first_device() returns 0.

Fix uclass_find_first_device() to also fail with -ENODEV instead.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-02-09 07:51:00 -05:00
Philippe Reynes
dcae39e55f watchdog: bcm6345: allow to use this driver on arm bcm63158
This IP is also used on some arm SoC, so we allow to
use it on arm bcm63158 too.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-02-09 07:50:59 -05:00
Faiz Abbas
351a4aa050 mmc: omap_hsmmc: Workaround errata regarding SDR104/HS200 tuning failures (i929)
Errata i929 in certain OMAP5/DRA7XX/AM57XX silicon revisions
(SPRZ426D - November 2014 - Revised February 2018 [1]) mentions
unexpected tuning pattern errors. A small failure band may be present
in the tuning range which may be missed by the current algorithm.
Furthermore, the failure bands vary with temperature leading to
different optimum tuning values for different temperatures.

As suggested in the related Application Report (SPRACA9B - October 2017
- Revised July 2018 [2]), tuning should be done in two stages.
In stage 1, assign the optimum ratio in the maximum pass window for the
current temperature. In stage 2, if the chosen value is close to the
small failure band, move away from it in the appropriate direction.

References:
[1] http://www.ti.com/lit/pdf/sprz426
[2] http://www.ti.com/lit/pdf/SPRACA9

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2019-02-09 07:50:58 -05:00
Patrick Delaunay
bbd108a082 clk: stm32mp1: correctly handle Clock Spreading Generator
To activate the csg option, the driver need to set the bit2
of PLLNCR register = SSCG_CTRL: Spread Spectrum Clock Generator
of PLLn enable.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-02-09 07:50:57 -05:00
Patrick Delaunay
8d6310aa0b clk: stm32mp1: add debug information
Add support of clk dump command and
display information during probe (under CONFIG_DISPLAY_CPUINFO).

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-02-09 07:50:57 -05:00
Patrick Delaunay
f3a23c2609 clk: stm32mp1: recalculate counter when switching freq
Because stgen is initialized with HSI clock, we need to
recalculate the counter when changing frequency.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-02-09 07:50:56 -05:00
Patrick Delaunay
63201281e5 clk: stm32mp1: correct access to RCC_OCENSETR/RCC_OCENCLRR
Remove unnecessary setbits on set/clear registers.
Avoid to deactivate HSI with HSE.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-02-09 07:50:56 -05:00
Patrick Delaunay
d661f61847 clk: stm32mp1: add IPCC clock
Add support for enable/disable of IPCC clock using AHB3 registers

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-02-09 07:50:56 -05:00
Patrick Delaunay
86617dd140 clk: stm32mp1: no more get ck_usbo_48m in device tree
Remove support of ck_usbo_48m clock node in device tree,
but force 48MHz frequency to prepare alignment
with kernel device tree.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2019-02-09 07:50:55 -05:00
Vabhav Sharma
ba8ba69b66 drivers: serial: dm: Enable DM_FLAG_PRE_RELOC in SBSA pl011 uart driver
The DM_FLAG_PRE_RELOC shall be enabled in SBSA PL011 uart driver
as this driver is used in NXP based SoCs

It is necessary to have Serial console running before relocation

The !CONFIG_IS_ENABLED(OF_CONTROL) [*] check is set as "workaround"
for DM problem : 4687919684

This flag is set if board does not support device-tree and using
platform data, In DM Model either of device tree or platform data
can be used to fetch device configuration

It is possible to use SBSA UART with CONFIG_DM_SERIAL but witout
corresponding device tree description (OF_CONTROL)

Other board/SoCs have this flag set unconditionally

Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
2019-02-09 07:50:55 -05:00
Philippe Reynes
47b68d00a3 watchdog: bcm6345: allow to use this driver on arm bcm6858
This IP is also used on some arm SoC, so we allow to
use it on arm bcm6858 too.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2019-02-09 07:50:50 -05:00
Philippe Reynes
771ee9b6ed watchdog: bcm6345: switch to raw I/O functions
This driver is used on several big endian mips board.
So we could use raw I/O function instead of forcing
big endian access.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2019-02-09 07:50:50 -05:00
Marek Vasut
6892550c4a mmc: Do not poll using CMD13 when changing timing
When using CMD6 to switch eMMC card timing from HS200/HS400 to HS/legacy,
do not poll for the completion status using CMD13, but rather wait 50mS.

Once the card receives the CMD6 and starts executing it, the bus is in
undefined state until both the card finishes executing the command and
until the controller switches the bus to matching timing configuration.
During this time, it is not possible to transport any commands or data
across the bus, which includes the CMD13.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
2019-02-09 11:08:40 +01:00
Marek Vasut
cbbe69483e mmc: tmio: renesas: Add 1uS delay after DMA completion on older IPs
The internal DMAC asserts DMA transfer end bit too early on older
version of the TMIO IPs which use bit 17 for DTRAEND. Add 1uS
delay after the completion of DMA transfer and before invalidating
the cache to let the DMAC fully complete the transfer. Otherwise,
it could happen that the last few bytes of a transferred data are
not available.

A test case to trigger this behavior is the following command, ran
on the U-Boot command line, with Sandisk 16 GiB UHS-I card inserted
into SDHI slot 0 and with first partition being of type FAT:
=> while true ; do mmc rescan ; fstype mmc 0:1 ; done

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-02-09 11:08:40 +01:00
Marek Vasut
992bcf4f27 mmc: tmio: Make DMA transfer end bit configurable
Different versions of the SDHI core use either bit 17 or bit 20 for the
DTRAEND indication, which can differ even between SoC revisions. Make
the DTRAEND bit position part of the driver private data, so that the
probe function can set this accordingly. Set this to 20 on Socionext
SoCs and either 17 or 20 on Renesas SoCs, depending on the SoC.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-02-09 11:08:40 +01:00
Michal Simek
83e4c7e9ff dm: core: Introduce dev_read_alias_highest_id()
It is wrapper for calling of_alias_get_highest_id() when live tree is
enabled and fdtdec_get_alias_highest_id() if not.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-02-08 06:25:32 +01:00
Michal Simek
5ebc7c7e27 dm: core: Add of_alias_get_highest_id()
The same functionality was added to Linux for i2c bus registration with this
commit message:

"
of: base: add function to get highest id of an alias stem

I2C supports adding adapters using either a dynamic or fixed id. The
latter is provided by aliases in the DT case. To prevent id collisions
of those two types, install this function which gives us the highest
fixed id, so we can then let the dynamically created ones come after
this highest number.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
"

Add it also to U-Boot for DM I2C support.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2019-02-08 06:24:57 +01:00
Tom Rini
50e24381c0 Merge branch 'master' of git://git.denx.de/u-boot-spi
- SPI-NOR support
2019-02-07 14:48:56 -05:00
Vignesh R
6d82517836 configs: Don't use SPI_FLASH_BAR as default
Now that new SPI NOR layer uses stateless 4 byte opcodes by default,
don't enable SPI_FLASH_BAR. For SPI controllers that cannot support
4-byte addressing, (stm32_qspi.c, fsl_qspi.c, mtk_qspi.c, ich.c,
renesas_rpc_spi.c) add an imply clause to enable SPI_FLASH_BAR so as to
not break functionality.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07 15:33:22 +05:30
Vignesh R
778572d7cb mtd: spi: Add lightweight SPI flash stack for SPL
Add a tiny SPI flash stack that just supports reading data/images from
SPI flash. This is useful for boards that have SPL size constraints and
would need to use SPI flash framework just to read images/data from
flash. There is approximately 1.5 to 2KB savings with this.

Based on prior work of reducing spi flash id table by
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07 15:33:21 +05:30
Vignesh R
5b66fdb29d mtd: spi: Remove unused files
spi_flash and spi_flash_ids are no longer needed after SPI NOR
migration. Remove them.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07 15:33:21 +05:30
Vignesh R
c4e8862308 mtd: spi: Switch to new SPI NOR framework
Switch spi_flash_* interfaces to call into new SPI NOR framework via MTD
layer. Fix up sf_dataflash to work in legacy way. And update sandbox to
use new interfaces/definitions

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07 15:33:21 +05:30
Vignesh R
2ee6705be0 mtd: spi: sf_probe: Add "jedec, spi-nor" compatible string
Linux uses "jedec,spi-nor" as compatible string for JEDEC compatible
SPI Flash device nodes. Therefore make U-Boot also to look for the same
compatible string so that we can use Linux DTS files as is.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07 15:33:21 +05:30
Vignesh R
8c927809ea mtd: spi: spi-nor-core: Add back U-Boot specific features
For legacy reasons, we will have to keep around U-Boot specific
SPI_FLASH_BAR and SPI_TX_BYTE. Add them back to the new framework

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07 15:33:21 +05:30
Vignesh R
0c6f187cdb mtd: spi: spi-nor-core: Add SFDP support
Sync Serial Flash Discoverable Parameters (SFDP) parsing support from
Linux. This allows auto detection and configuration of Flash parameters.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07 15:33:21 +05:30
Vignesh R
61059bc55a mtd: spi: spi-nor-core: Add 4 Byte addressing support
Sync changes from Linux SPI NOR framework to add 4 byte addressing
support. This is required in order to support flashes like MT35x
that no longer support legacy Bank Address Register(BAR) way of accessing
>16MB region.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07 15:33:21 +05:30
Vignesh R
492e65b29b mtd: spi: spi-nor-core: Add SPI MEM support
Many SPI controllers have special MMIO interfaces which provide
accelerated read/write access but require knowledge of flash parameters
to make use of it. Recent spi-mem layer provides a way to support such
controllers.
Therefore, add spi-mem support to spi-nor-core as a way to support SPI
controllers with MMIO interface. SPI MEM layer takes care of translating
spi_mem_ops to spi_xfer()s in case of legacy SPI controllers.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07 15:33:21 +05:30
Vignesh R
7aeedac015 mtd: spi: Port SPI NOR framework from Linux
Current U-Boot SPI NOR support (sf layer) is quite outdated as it does not
support 4 byte addressing opcodes, SFDP table parsing and different types of
quad mode enable sequences. Many newer flashes no longer support BANK
registers used by sf layer to a access >16MB of flash address space.
So, sync SPI NOR framework from Linux v4.19 that supports all the
above features. Start with basic sync up that brings in basic framework
subsequent commits will bring in more features.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07 15:33:21 +05:30
Vignesh R
6430eea639 spi: Add non DM version of SPI_MEM
Add non DM version of SPI_MEM to support easy migration to new SPI NOR
framework. This can be removed once DM_SPI conversion is complete.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07 15:33:21 +05:30
Vignesh R
76094485e4 spi: spi-mem: Claim SPI bus before spi mem access
It is necessary to call spi_claim_bus() before starting any SPI
transactions and this restriction would also apply when calling spi-mem
operations. Therefore claim and release bus before requesting transfer
via exec_op.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07 15:33:21 +05:30
Vignesh R
12563f768e spi: spi-mem: Extend spi_mem_adjust_op_size() to honor max xfer size
Extend spi_mem_adjust_op_size() to take spi->max_write_size and
spi->max_read_size into account.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07 15:33:21 +05:30
Vignesh R
6d373e523f spi: spi-mem: Allow use of spi_mem_exec_op for all SPI modes
SPI controllers support all types of SPI modes including dual/quad bus
widths. Therefore remove constraint wrt SPI mode from spi-mem layer.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stefan Roese <sr@denx.de>
Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
2019-02-07 15:33:21 +05:30
Tom Rini
bdac5e18a8 Merge git://git.denx.de/u-boot-marvell
- Move Armada XP / 38x PCIe driver to DM_PCI from me
- Move Armada XP / 38x LCD driver to DM_VIDEO from me
- Add uDPU board (Armada-3720) from Vladimir

[trini: Fix warning in pci-uclass.c by removing ret from
	pci_uclass_child_post_bind as it no longer calls functions with
        a return code to catch.]
Signed-off-by: Tom Rini <trini@konsulko.com>II
2019-02-05 12:29:59 -05:00
Stefan Roese
6d9a98c583 video: Armada XP: Move driver to DM_VIDEO
This patch moves the Armada XP video / LCD driver to DM_VIDEO. With this
move, the legacy interface board_video_init() is removed from the
theadorable board code (only user of this video driver). The support
via DT will be added in a separate patch.

This patch also enables DM_VIDEO for the theadorable board, as this is
needed to not break git bisect'ability.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>
2019-02-05 14:23:21 +01:00
Stefan Roese
94f453ea38 pci: pci_mvebu: Add DM_PCI support and move CONFIG_PCI_MVEBU to defconfig
This patch adds DM_PCI support to the MVEBU PCIe driver. This is
necessary, since all PCI drivers have to be moved to DM (driver model)
until the v2019.07 release.

To not break git bisect'ablility, this patch also moves CONFIG_PCI_MVEBU
from config headers to the defconfig files.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Chris Packham <chris.packham@alliedtelesis.co.nz>
Cc: Phil Sutter <phil@nwl.cc>
Cc: Marek Behún <marek.behun@nic.cz>
Cc: VlaoMao <vlaomao@gmail.com>
2019-02-05 14:22:38 +01:00
Stefan Roese
b52142004f pci: Add pci_get_devfn() to extract devfn from the fdt_pci_addr
This function will be used by the Marvell Armada XP/38x PCIe driver,
which is moved to DM right now. So let's extract the functionality
from pci_uclass_child_post_bind() to make it available.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-05 14:22:24 +01:00
Tom Rini
e5fd39c886 u-boot-rockchip changes for 2019.04-rc1:
* support for Chromebook Bob
   * full pinctrl driver using DTS properties
   * documentation improvements
   * I2S support for some Rockchip SoCs
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Merge tag 'for-master-20190201' of git://git.denx.de/u-boot-rockchip

u-boot-rockchip changes for 2019.04-rc1:
  * support for Chromebook Bob
  * full pinctrl driver using DTS properties
  * documentation improvements
  * I2S support for some Rockchip SoCs
2019-02-02 10:11:20 -05:00
Tom Rini
544d5e98f3 - MIPS: mscc: jr2: small fixes
- MIPS: mscc: luton: add ethernet and switch driver
 - MIPS: mt76xx: fix timer frequency
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Merge tag 'mips-pull-2019-02-01' of git://git.denx.de/u-boot-mips

- MIPS: mscc: jr2: small fixes
- MIPS: mscc: luton: add ethernet and switch driver
- MIPS: mt76xx: fix timer frequency
2019-02-02 10:11:12 -05:00
Adam Ford
3c29a56736 regulator: pbias: Handle extended drain IO when changing omap36 PBIAS
The OMAP36 and DM37 TRM state to disable extneded drain IO before
changing the PBIAS.  This patch does this before pmic writes if
the CONFIG_MMC_OMAP36XX_PINS flag is set and the cpu family is
omap36xx

Signed-off-by: Adam Ford <aford173@gmail.com>
2019-02-01 14:13:45 -05:00
Philipp Tomsich
5a127325f0 pinctrl: Kconfig: fix missing include of rockchip/Kconfig
After the merge of the new, generic pinctrl-code, the include for
rockchip/Kconfig was missing.  Add it here, so we can select the
pinctrl-driver for SPL.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:14 +01:00
Philipp Tomsich
efc4677171 pinctrl: Kconfig: sort includes alphabetically
To make adding new subdirectories easier, let's enforce alphabetical
ordering of the includes of Kconfig files in the respective
subdirectories.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:14 +01:00
Simon Glass
aa48c94ca8 rockchip: Implement spl_gpio in the GPIO driver
Allow rockchip boards to use GPIOs before driver model is ready. This is
really only useful for setting GPIOs to enable the early debug console, if
needed on some platforms.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:13 +01:00
Simon Glass
5328af1774 rockchip: clk: Add mention of four new clocks
These clocks are needed to get MMC running. We don't actually support
setting them yet.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:13 +01:00
Simon Glass
6831616063 clk: Improve debug message in clk_set_default_rates()
It is helpful to print the clock number as well as the index, so that this
can be looked up in the binding file. Update the debug() statement to do
this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:12 +01:00
David Wu
96f73e0d24 pinctrl: rockchip: Clean the unused rockchip pinctrl drivers
If we used the pinctrl-rockchip driver, these code is not needed,
so remove them.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:11 +01:00
David Wu
e7ae4cf27a pinctrl: rockchip: Add common rockchip pinctrl driver
Use this driver to fit all Rockchip SOCs and to support
the desired pinctrl configuration via DTS.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:11 +01:00
Simon Glass
bcea0e1e81 rockchip: Add a sound driver
Add a sound driver for rk3288 supporting chromebook_jerry. This uses the
I2S driver, and existing audio codec and the clock/pinmux support.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:10 +01:00
Simon Glass
2665f09115 rockchip: Add an I2S driver
Add a driver for I2S which allows audio data to be sent from the SoC to
the audio codec. The sample rate and other settings are hard-coded for now
as there is no suitable device-tree binding available.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:10 +01:00
Simon Glass
3dbfe5ae61 rockchip: rk3288: Add i2s pinctrl and clock support
Add support for setting pinctrl and clock for I2S on rk3288. This allows
the sound driver to operate. These settings were created by rkmux.py

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2019-02-01 16:59:10 +01:00
Jean-Jacques Hiblot
1c1464c2b1 usb: ether: call _usb_eth_halt() if initialization fails
If the host does not respond in time, the initialization fails. However
the usb ether driver will still be registered. This will make
usb_gadget_probe_driver() fail the next time the initialization is
attempted because it cannot find an available UDC.

Fixing this by calling _usb_eth_halt() when the init fails.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
2019-02-01 09:09:40 -05:00
Horatiu Vultur
c5620aeea4 net: Add MSCC Luton networkd driver.
Add network driver for Microsemi Ethernet switch, it is
present on Luton SoCs.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-02-01 14:13:36 +01:00
Horatiu Vultur
0b8f34dc8c net: mscc: Remove unused variables
Remove unused variables in the struct ocelot_private and make
miim variable static.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-02-01 14:13:36 +01:00
Horatiu Vultur
45f2748c50 net: mscc: Move mac_table_add function into different file.
Move the function mac_table_add into a different file,
so it can be reused.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-02-01 14:13:36 +01:00
Horatiu Vultur
36d04f52ff net: mscc: Move ocelot_send and ocelot_recv in a different file.
This functions can be reused by other MSCC SoCs therefore,
make them more generic and move them in separate files.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-02-01 14:13:36 +01:00
Horatiu Vultur
2fff4a9b59 net: mscc: Move miim commands into separate file.
Move miim functions that can be shared in a different file inside
mscc_eswitch.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-02-01 14:13:36 +01:00
Horatiu Vultur
4c66157f42 net: mscc: Move ocelot_switch to mscc_eswitch folder
Move file ocelot_switch to mscc_eswitch to prepare to add
new net drivers for other MSCC SoCs.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
2019-02-01 14:13:36 +01:00
Tom Rini
db4a29993d - ihs and imx driver fixes
- relax EDID validation checks for 0 hsync/vsync
   pulse width (support some quirky displays)
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Merge tag 'video-updates-for-2019.04-rc1' of git://git.denx.de/u-boot-video

- ihs and imx driver fixes
- relax EDID validation checks for 0 hsync/vsync
  pulse width (support some quirky displays)
2019-01-31 16:07:37 -05:00
Neil Armstrong
3bed422094 video: Add Meson Video Processing Unit Driver
This adds video output support for Amlogic GXBB/GXL/GXM chips.
The supported ports are CVBS and HDMI (based on DW_HDMI).

When using HDMI, only DMT modes are supported.

There is support for simple-framebuffer (CONFIG_VIDEO_DT_SIMPLEFB)

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jorge Ramire-Ortiz <jramirez@baylibre.com>
Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com>
[narmstrong: fixed defines alignment in meson_canvas.c]
Reviewed-by: Anatolij Gustschin <agust@denx.de>
2019-01-31 09:35:01 +01:00
Jorge Ramirez-Ortiz
56dd8d87e5 video: dw_hdmi: add support for color conversion
Some IPs like the meson VPU can only feed a particular pixel format to
dw_hdmi. As of now, the driver is hardcoded to use RGB888 as input.

This commit enables different pixel format inputs, with the appropriate
CSC configuration.

Signed-off-by: Jorge Ramire-Ortiz <jramirez@baylibre.com>
Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
2019-01-31 09:35:01 +01:00
Jorge Ramirez-Ortiz
fd99841808 video: dw_hdmi: support SoC specific read/write ops
Some IPs like the meson VPU have a specific way to write to dw_hdmi
registers. Make it configurable.

Signed-off-by: Jorge Ramirez-Ortiz <jramirez@baylibre.com>
[added commit description]
Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
2019-01-31 09:35:01 +01:00
Maxime Jourdan
335d287327 power: domain: meson-gx-pwrc-vpu: add missing depends
MESON_GX_VPU_POWER_DOMAIN should depend on POWER_DOMAIN.

Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
2019-01-31 09:35:01 +01:00
Simon Goldschmidt
1f92c074cb dfu: mmc: call fs functions instead of run_command
This unbreaks dfu mmc_file_op which is currently broken since using the
load cmd on a buffer from heap is not allowed - added with
commit aa3c609e2b ("fs: prevent overwriting reserved memory")

Fixes: commit aa3c609e2b ("fs: prevent overwriting reserved memory")
Reported-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Lukasz Majewski <lukma@denx.de>
2019-01-30 21:22:53 -05:00
Tom Rini
552452f80c Merge branch 'master' of git://git.denx.de/u-boot-sunxi
- Enable DM_MMC support
2019-01-30 12:24:32 -05:00
Andre Przywara
13b0867dc3 sunxi: clk: enable clk and reset for CCU devices
Some Allwinner clock devices have parent clocks and reset gates itself,
which need to be activated for them to work.

Add some code to just assert all resets and enable all clocks given.
This should enable the A80 MMC config clock, which requires both to be
activated. The full CCU devices typically don't require resets, and have
just fixed clocks as their parents. Since we treat both as optional and
enabling fixed clocks is a NOP, this works for all cases, without the need
to differentiate between those clock types.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2019-01-30 18:21:35 +05:30
Tom Rini
748ad078ee For 2019.04
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Merge tag 'u-boot-imx-20190129' of git://git.denx.de/u-boot-imx

For 2019.04
2019-01-30 07:22:12 -05:00
Andre Przywara
4233698dd3 mmc: sunxi: Honour non-removable property in DT
If a board DT describes a cd-gpios property, but also marks the storage
as non-removable, we must ignore the GPIO (as Linux does).

Teach the DM_MMC part of the Allwinner MMC driver about the
non-removable DT property, to fix DM_MMC access on the SoPine and
Pine64-LTS board.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2019-01-29 23:49:41 +05:30
Andre Przywara
c57572eb5a mmc: sunxi: Add DM clk and reset support
Now that we have the gate clocks and the reset gates in our new
Allwinner clock driver, let's make use of them in the MMC driver, when
DM_MMC is defined.
We treat the reset device as optional now, as the older SoCs don't
implement it.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-01-29 23:44:03 +05:30
Jagan Teki
3c8c7da6fc mmc: sunxi: Add DM_MMC support for A80
A80 gates clock already be part of CLK framework, so just
add mod_clk offset with A80 compatible string.

Cc: Rask Ingemann Lambertsen <rask@formelder.dk>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2019-01-29 23:41:57 +05:30
Jagan Teki
9e23338268 mmc: sunxi: Add DM_MMC support for H6
Unlike other Allwinner SoC's, H6 uses a different MMC mod clock offset.
Connect that with the respective compatible string.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2019-01-29 23:35:18 +05:30
Jagan Teki
a1925a64d5 mmc: sunxi: Add remaining compatible strings
Add MMC compatible strings for A83T, A64, H5.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2019-01-29 23:34:58 +05:30
Andre Przywara
e0c7ce7e52 sunxi: clk: A80: add MMC clock support
The A80 handles resets and clock gates for the MMC devices differently,
outside of the CCU IP block. Consequently we have a separate clock
device with a separate binding for that.

Implement that with the respective clock gates and resets to allow the
A80 taking part in the DM_MMC game.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[jagan: fix a80 mmc clock config compatible]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-01-29 23:33:08 +05:30
Andre Przywara
bb3e5aa289 sunxi: clk: add MMC gates/resets
Add the MMC clock gates and reset bits for all the Allwinner SoCs.
This allows them to be used by the MMC driver.

We don't advertise the mod clock yet, as this is still handled by the
MMC driver.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[jagan: add V3S, A80 gates/resets]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-01-29 23:30:11 +05:30
Jerome Brunet
c4c726c26b pinctrl: meson: add pinconf support
Adding pinconf support is necessary to enable boot from SPI
without breaking the eMMC. When booting from SPI, the ROM code
leave pull downs on the eMMC pad.

We need to set pinconf provided in DT to solve this

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
[narmstrong: added missing comma in pinctrl-meson-axg-pmx.c]
2019-01-29 11:19:15 +01:00
Mario Six
6df07d854b ihs_video_out: Fix error handling
The ihs_video_out driver's error handling is incorrect in two places
(one is a missing negation, and in one place a error should be ignored).

Fix these two instances.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
2019-01-28 21:29:25 +01:00
Priit Laes
0307d95d52 videomodes: Relax EDID validation checks for hsync/vsync pulse width
Current EDID detailed timing parser errors out when either
horizontal or vertical pulse sync width is 0, thus not
allowing a display with EDID listed below work properly.

EDID below works ok within Linux although it warns about
these two fields being 0. Therefore relax the checks a bit
so we can actually use this the screen out of the box.

Of-course, this display itself is somewhat quirky display with
following anti-features:
- HPD pin is not usable
- although resolution is 640x480, only top 240 pixels are visible

$ xxd -p display.edid
00ffffffffffff0005a1e00301000000150f0103800f05780a0f6ea05748
9a2610474f200000010101010101010101010101010101012a08804520e0
0b1020004000953600000018000000fd0034441a2403000a202020202020
0000001000310a20202020202020202020200000001000002a4030701300
782d1100001e006b

$ edid-decode display.edid
EDID version: 1.3
Manufacturer: AMA Model 3e0 Serial Number 1
Digital display
Maximum image size: 15 cm x 5 cm
Gamma: 2.20
RGB color display
First detailed timing is preferred timing
Display x,y Chromaticity:
  Red:   0.6250, 0.3398
  Green: 0.2841, 0.6044
  Blue:  0.1494, 0.0644
  White: 0.2802, 0.3105
Established timings supported:
  640x480@60Hz 4:3 HorFreq: 31469 Hz Clock: 25.175 MHz
Standard timings supported:
Detailed mode: Clock 20.900 MHz, 149 mm x 54 mm
                640  672  672  709 hborder 0
                480  484  484  491 vborder 0
               -hsync -vsync
               VertFreq: 60 Hz, HorFreq: 29478 Hz
Monitor ranges (GTF): 52-68Hz V, 26-36kHz H, max dotclock 30MHz
Dummy block
Dummy block
Checksum: 0x6b (valid)

Signed-off-by: Priit Laes <priit.laes@paf.com>
Signed-off-by: Priit Laes <plaes@plaes.org>
2019-01-28 21:20:05 +01:00
Patrick Bruenn
791c88da31 mmc: fsl_esdhc: add compatible for fsl, imx53-esdhc
Add compatible "fsl,imx53-esdhc" to keep mmc working on i.MX53 platforms
with CONFIG_DM_MMC=y

Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
2019-01-28 20:55:46 +01:00
Adam Ford
96d0be07e7 MTD: nand: mxs_nand_spl: Fix empty function pointer for BBT
The initialization function calls a nand_chip.scan_bbt(mtd) but
scan_bbt is never initialized resulting in an undefined function
pointer.  This will direct the function pointer to nand_default_bbt
defined in the same file.

Signed-off-by: Adam Ford <aford173@gmail.com>
Acked-by: Stefan Agner <stefan.agner@toradex.com>
2019-01-28 20:55:46 +01:00
Ye Li
65a106e36f spi: mxc_spi: Fix build warning on ARM64 platforms
When building mxc_spi driver on ARM64 platforms, get below build warnings.
Fix it in this patch.

In file included from include/common.h:48:0,
 from drivers/spi/mxc_spi.c:9:
 drivers/spi/mxc_spi.c: In function ‘spi_xchg_single’:
drivers/spi/mxc_spi.c:232:21: warning: cast from pointer to integer of
different size [-Wpointer-to-int-cast]
 _func_, bitlen, (u32)dout, (u32)din);
 ^
 include/log.h:135:26: note: in definition of macro ‘debug_cond’
printf(pr_fmt(fmt), ##args); \
 ^~~~
 drivers/spi/mxc_spi.c:231:2: note: in expansion of macro ‘debug’
debug("%s: bitlen %d dout 0x%x din 0x%x\n",
 ^~~~~
 drivers/spi/mxc_spi.c:232:32: warning: cast from pointer to integer of
different size [-Wpointer-to-int-cast]
 _func_, bitlen, (u32)dout, (u32)din);
 ^
 include/log.h:135:26: note: in definition of macro ‘debug_cond’
printf(pr_fmt(fmt), ##args); \
 ^~~~
 drivers/spi/mxc_spi.c:231:2: note: in expansion of macro ‘debug’
debug("%s: bitlen %d dout 0x%x din 0x%x\n",
 ^~~~~

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-01-28 20:35:47 +01:00
Ye Li
11a1c27eb4 pinctrl: imx: Fix select input issue
The pinctrl supports to set any bit in input register on iMX6 if
the MSB of input value is 0xff. But the driver uses signed int for
input value, so when executing the codes below, it won't meet.
Because this is arithmetic right shift.

    if (input_val >> 24 == 0xff)

Fix the issue by changing the input_val, config_val and mux_mode to u32.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2019-01-28 20:35:47 +01:00
Peng Fan
1610368234 gpio: introduce CONFIG_SPL_DM_PCA953X
Introduce CONFIG_SPL_DM_PCA953X for SPL usage.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-28 20:35:47 +01:00
Peng Fan
04b249656e imx8: scu: use dedicated MU for SPL
SPL runs in EL3 mode, except MU0_A, others are not powered on,
and could not be used. However normal U-Boot use MU1_A, so we
could not reuse the one in dts. And we could not replace the one
in dts with MU0_A, because MU0_A is reserved in secure world.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2019-01-28 20:35:47 +01:00
Martyn Welch
774ec60b74 Enable FEC driver to retrieve PHY address from device tree
Currently if we have more than one phy on the MDIO bus, we do not have a
good mechanism for determining which should be used at runtime. Enable the
FEC driver to determine the address for the PHY from the device tree.

Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2019-01-28 12:47:15 +01:00
Tom Rini
0da9025508 Merge branch '2019-01-25-master-imports'
- snapdragon 820c improvements
- poplar updates
- DFU + SPL cleanups
- Improve the mediatek mmc driver
- Other minor cleanups / improvements
2019-01-26 22:47:55 -05:00
Michal Simek
e38cef9f6e misc: i2c_eeprom: Add atmel,24c08 to the list
Linux kernel binding is using atmel,24c08 compatible string. On the
other hand there is atmel,24c08a which is not listed in the kernel.
Add compatible string without "a" suffix to be compatible with Linux
kernel binding.

These eeproms are available on several ZynqMP development boards.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2019-01-26 08:13:57 -05:00