Commit graph

259 commits

Author SHA1 Message Date
Patrick Delaunay
f42045b2e7 stm32mp15: replace CONFIG_TFABOOT when it is possible
In some part of STM32MP15 support the CONFIG_TFABOOT can be replaced
by other config: CONFIG_ARMV7_PSCI and CONFIG_ARM_SMCCC.

This patch also simplifies the code in cpu.c, stm32mp1_ram.c and
clk_stml32mp1.c as execution of U-Boot in sysram (boot without SPL and
without TFA) is not supported: the associated initialization code is
present only in SPL.

This cleanup patch is a preliminary step to support SPL load of OP-TEE
in secure world, with SPL in secure world and U-Boot in no-secure world.

Reported-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-10 17:07:31 +01:00
Bin Meng
d36c94279d ram: sifive: Fix -Wint-to-pointer-cast warnings
The following warning is seen in sifive_ddr.c in a 32-bit build:

  warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]

Change to use dev_read_addr_index_ptr().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-10-20 10:59:09 +08:00
Wolfgang Denk
0cf207ec01 WS cleanup: remove SPACE(s) followed by TAB
Signed-off-by: Wolfgang Denk <wd@denx.de>
2021-09-30 09:08:16 -04:00
Wolfgang Denk
0a50b3c97b WS cleanup: remove trailing white space
Signed-off-by: Wolfgang Denk <wd@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-09-30 08:08:56 -04:00
Wolfgang Denk
66356b4c06 WS cleanup: remove trailing empty lines
Signed-off-by: Wolfgang Denk <wd@denx.de>
2021-09-30 08:08:56 -04:00
Simon Glass
f0ab8f9fbe clk: Rename clk_get_by_driver_info()
This is actually a misnomer now, since the phandle info may contain
a driver_info index or a udevice index. Rename it to use the word
'phandle', which seems more accurate. Add a comment while we are here.

Also add a test for this function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-25 09:46:15 -06:00
Simon Glass
dcfc42b12f treewide: Try to avoid the preprocessor with OF_REAL
Convert some of these occurences to C code, where it is easy to do. This
should help encourage this approach to be used in new code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-25 09:46:15 -06:00
Simon Glass
9539738509 treewide: Use OF_REAL instead of !OF_PLATDATA
Now that we have a 'positive' Kconfig option, use this instead of the
negative one, which is harder to understand.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-25 09:46:15 -06:00
Michal Simek
b4c2c151b1 Kconfig: Remove all default n/no options
default n/no doesn't need to be specified. It is default option anyway.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
[trini: Rework FSP_USE_UPD portion]
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-31 17:47:49 -04:00
Simon Glass
0b1284eb52 global: Convert simple_strtoul() with decimal to dectoul()
It is a pain to have to specify the value 10 in each call. Add a new
dectoul() function and update the code to use it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-02 13:32:14 -04:00
Patrick Delaunay
b953ec2bca dm: define LOG_CATEGORY for all uclass
Define LOG_CATEGORY for all uclass to allow filtering with
log command.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-07-06 10:38:03 -06:00
Joseph Chen
2d46775287 rockchip: rk3568: Add sdram driver
Add the driver for rk3568 u-boot to get sdram capacity.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-06-18 14:36:24 +08:00
Green Wan
dab18c7aa6 drivers: ram: sifive: rename fu540_ddr and add fu740 support
Rename fu540_ddr.c to sifive_ddr.c and add fu740 support

Signed-off-by: Green Wan <green.wan@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-05-31 16:35:54 +08:00
Lokesh Vutla
2ce6dedf0b ram: k3-ddrss: Enable vtt regulator if present
Attempt to get and enable a vtt regulator if one is provided from the
dts. If we do not find one, continue as not all platforms have this.

Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:30:52 +05:30
Dave Gerlach
9f9b5c1c16 ram: k3-ddrss: Introduce support for AM642 SoCs
Introduce support for the AM64 DDRSS controller which uses the 16bit
variation of the controller. This controller shares much functionality
with the existing J721e support, so this patch introduces only the new
code needed for am64 specific support from "_16bit_" files with headers
under "16bit/" include path/.

Also add a CONFIG_K3_AM64_DDRSS option to the choice required for use
with CONFIG_K3_DDRSS to allow selecting AM64 support.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:30:52 +05:30
Dave Gerlach
a8c13c777e ram: k3-ddrss: Introduce common driver with J7 SoC support
Introduce a new version of the ddr driver which has the ability to
support different variations of the controller. Also introduce support
for the 32bit variation of the controller which is what was already
supported by the previous version used for J721e and J7200.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:30:52 +05:30
Dave Gerlach
db2438131d ram: k3-ddrss: Introduce top-level CONFIG_K3_DDRSS
Create a new CONFIG_K3_DDRSS option to select the common parts of the
k3-ddrss driver. Also introduce a choice that depends on the top level
option to select CONFIG_K3_J721E_DDRSS for j721e support, and update
corresponding Kconfig as required.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:30:52 +05:30
Dave Gerlach
67124b9a74 ram: k3-j721e: Rename to k3-ddrss
Rename the k3-j721e folder under drivers/ram to k3-ddrss in preparation
of introducing additional support for other platforms to the same
driver.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:30:52 +05:30
Dave Gerlach
036f0c0b66 ram: k3-j721e: lpddr4_ctl_regs: Fix checkpatch issue for types
Use Linux style u32 instead of uint32_t.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:30:52 +05:30
Dave Gerlach
cc40e4d947 ram: k3-j721e: lpddr4_pi_macros: Fix indentation issues
Fix the indentation for certain macros to be consistent with the other
macros in the file, as the existing indentation does not make sense in
many places.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:30:52 +05:30
Dave Gerlach
cde1fcee3e ram: k3-j721e: lpddr4_phy_core_macros: Fix indentation issues
Fix the indentation for certain macros to be consistent with the other
macros in the file, as the existing indentation does not make sense in
many places.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:30:52 +05:30
Dave Gerlach
0ef6349326 ram: k3-j721e: lpddr4_ddr_controller_macros: Fix indentation issues
Fix the indentation for certain macros to be consistent with the other
macros in the file, as the existing indentation does not make sense in
many places.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:30:52 +05:30
Dave Gerlach
6a0677d0a0 ram: k3-j721e: lpddr4_data_slice_3_macros: Fix indentation issues
Fix the indentation for certain macros to be consistent with the other
macros in the file, as the existing indentation does not make sense in
many places.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:30:52 +05:30
Dave Gerlach
f1ce7dd92d ram: k3-j721e: lpddr4_data_slice_2_macros: Fix indentation issues
Fix the indentation for certain macros to be consistent with the other
macros in the file, as the existing indentation does not make sense in
many places.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:30:52 +05:30
Dave Gerlach
c1cf7a3d3a ram: k3-j721e: lpddr4_data_slice_1_macros: Fix indentation issues
Fix the indentation for certain macros to be consistent with the other
macros in the file, as the existing indentation does not make sense in
many places.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:30:52 +05:30
Dave Gerlach
5bf74a4884 ram: k3-j721e: lpddr4_data_slice_0_macros: Fix indentation issues
Fix the indentation for certain macros to be consistent with the other
macros in the file, as the existing indentation does not make sense in
many places.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:30:52 +05:30
Dave Gerlach
6da67b081f ram: k3-j721e: lpddr4_address_slice_0_macros: Fix indentation issues
Fix the indentation for certain macros to be consistent with the other
macros in the file, as the existing indentation does not make sense in
many places.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-05-12 16:30:52 +05:30
Stefan Roese
b0f4ba0242 mips: octeon: Misc changes required because of the newly added headers
With the newly added headers and their restructuring (which macro is
defined where), some changes in the already existing Octeon files are
necessary. This patch makes the necessary changes.

Signed-off-by: Stefan Roese <sr@denx.de>
2021-04-23 21:03:24 +02:00
Tom Rini
3f2e3c7845 Add rt-thread art-pi board support based on STM32H750 SoC
Add Engicam i.Core STM32MP1 SoM
 Add FIP header support for STM32programmer
 Update uart number when no serial device found for STM32MP1
 Remove board_check_usb_power function when ADC flag is not set
 Update SPL size limitation for STM32MP1
 Set soc_type, soc_pkg, soc_rev env variables for STM32MP1
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Merge tag 'u-boot-stm32-20210409' of https://source.denx.de/u-boot/custodians/u-boot-stm

Add rt-thread art-pi board support based on STM32H750 SoC
Add Engicam i.Core STM32MP1 SoM
Add FIP header support for STM32programmer
Update uart number when no serial device found for STM32MP1
Remove board_check_usb_power function when ADC flag is not set
Update SPL size limitation for STM32MP1
Set soc_type, soc_pkg, soc_rev env variables for STM32MP1
2021-04-09 13:10:59 -04:00
dillon min
1f0305e0d0 ram: stm32: fix strsep failed on read only memory
strsep will change data from original memory address,
in case the memory is in non-sdram/sram place, will
run into a bug(hang at SDRAM: )

just add a temporary array to store bank_name[] to fix this
bug.

Signed-off-by: dillon min <dillon.minfei@gmail.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-04-09 11:53:00 +02:00
Bin Meng
ae2d9506a3 riscv: sifive: Rename fu540 board to unleashed
In preparation to add SiFive Unmatched board support, let's rename
the existing fu540 board to unleashed.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-04-08 15:37:29 +08:00
Simon Glass
401d1c4f5d common: Drop asm/global_data.h from common header
Move this out of the common header and include it only where needed.  In
a number of cases this requires adding "struct udevice;" to avoid adding
another large header or in other cases replacing / adding missing header
files that had been pulled in, very indirectly.   Finally, we have a few
cases where we did not need to include <asm/global_data.h> at all, so
remove that include.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-02-02 15:33:42 -05:00
Dylan Hung
fde9314346 ram: aspeed: Add AST2600 DRAM control support
AST2600 supports DDR4 SDRAM with maximum speed DDR4-1600.
The DDR4 DRAM types including 128MbX16 (2Gb), 256MbX16 (4Gb),
512MbX16 (8Gb), 1GbX16 (16Gb), and 1GbX8 TwinDie (16Gb) are supported.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2021-01-18 15:19:15 -05:00
Heinrich Schuchardt
f5abd8a616 ram: k3-j721e: rename BIT_MASK()
The macro BIT_MASK is already defined in include/linux/bitops.h. To avoid
name collisions rename BIT_MASK() in drivers/ram/k3-j721e/lpddr4_private.h
to LPDDR4_BIT_MASK().

Remove superfluous parantheses.
Remove superfluous comparison to 0.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-01-16 19:17:11 -05:00
Patrick Delaunay
66b3b9db69 ram: stm32mp1: migrate trace to dev or log macro
Define LOG_CATEGORY, use dev_ macro when it is possible
and migrate other trace to log_ macro.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2021-01-13 09:52:58 +01:00
Patrick Delaunay
997f7dab9d ram: stm32: migrate trace to log macro
Define LOG_CATEGORY, change debug to dev_dbg and remove "%s:" __func__
header as it is managed by dev macro (dev->name is displayed)

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2021-01-13 09:52:58 +01:00
Simon Glass
8a8d24bdf1 dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13 16:51:09 -07:00
Simon Glass
d1998a9fde dm: treewide: Rename ofdata_to_platdata() to of_to_plat()
This name is far too long. Rename it to remove the 'data' bits. This makes
it consistent with the platdata->plat rename.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13 16:51:09 -07:00
Simon Glass
c69cda25c9 dm: treewide: Rename dev_get_platdata() to dev_get_plat()
Rename this to be consistent with the change from 'platdata'.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13 16:51:09 -07:00
Simon Glass
caa4daa2ae dm: treewide: Rename 'platdata' variables to just 'plat'
We use 'priv' for private data but often use 'platdata' for platform data.
We can't really use 'pdata' since that is ambiguous (it could mean private
or platform data).

Rename some of the latter variables to end with 'plat' for consistency.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13 16:51:08 -07:00
Simon Glass
41575d8e4c dm: treewide: Rename auto_alloc_size members to be shorter
This construct is quite long-winded. In earlier days it made some sense
since auto-allocation was a strange concept. But with driver model now
used pretty universally, we can shorten this to 'auto'. This reduces
verbosity and makes it easier to read.

Coincidentally it also ensures that every declaration is on one line,
thus making dtoc's job easier.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-12-13 08:00:25 -07:00
Tom Rini
2c31d7e746 Merge tag 'u-boot-rockchip-20201031' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- New PX30 board: Engicam PX30.Core;
- Fix USB HID support for rock960;
- Remove host endianness dependency for rockchip mkimage;
- dts update for rk3288-tinker;
- Enable console MUX for some ROCKPi boards;
- Add config-based ddr selection for px30;
2020-10-30 23:13:13 -04:00
Heiko Stuebner
2db36c64bd ram: rockchip: px30: add a config-based ddr selection
The SRAM on the PX30 is not big enough to hold multiple DDR configs
so it needs to be selected during build.

So far simply the DDR3 config was always selected and getting DDR4
or LPDDR2/3 initialized would require a code modification.

So add Kconfig options similar to RK3399 to allow selecting the DDR4
and LPDDR2/3 options instead, while DDR3 stays the default as before.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2020-10-30 18:11:29 +08:00
Heinrich Schuchardt
c670aeee3d common: rename getc() to getchar()
The sandbox is built with the SDL2 library with invokes the X11 library
which in turn calls getc(). But getc() in glibc is defined as

    int getc(FILE *)

This does not match our definition.

    int getc(void)

The sandbox crashes when called with parameter -l.

Rename our library symbol getc() to getchar().

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-10-22 09:54:53 -04:00
Sean Anderson
8d4c596644 ram: imxrt: Include device_compat.h
Necessary for dev_xxx.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-10-15 18:36:56 -04:00
Dylan Hung
0474050d46 ram: add ddr4 dual x8 configuration
the aspeed ddr sdram controller needs to know if the memory chip mounted on
the board is dual x8 die or not. Or it may get the wrong size of the
memory space.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-10-08 10:58:45 -04:00
Dylan Hung
5d457f8057 ram: move aspeed ram driver into drivers/ directory
to improve the maintainability.  It is more easier to modify and add
configurations of the driver in the centralized ram driver directory.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2020-10-08 10:58:33 -04:00
Aaron Williams
15afe725f3 ram: octeon: Add MIPS Octeon3 DDR4 support (part 3/3)
This Octeon 3 DDR driver is ported from the 2013 Cavium / Marvell U-Boot
repository. It currently supports DDR4 on Octeon 3. It can be later
extended to support also DDR3 and Octeon 2 platforms.

Part 3 includes the DIMM SPD handling code and the Kconfig / Makefile
integration.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07 20:25:57 +02:00
Aaron Williams
61674a17bc ram: octeon: Add MIPS Octeon3 DDR4 support (part 2/3)
This Octeon 3 DDR driver is ported from the 2013 Cavium / Marvell U-Boot
repository. It currently supports DDR4 on Octeon 3. It can be later
extended to support also DDR3 and Octeon 2 platforms.

Part 2 includes the very complex Octeon 3 DDR4 configuration

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07 20:25:57 +02:00
Aaron Williams
e13bb86588 ram: octeon: Add MIPS Octeon3 DDR4 support (part 1/3)
This Octeon 3 DDR driver is ported from the 2013 Cavium / Marvell U-Boot
repository. It currently supports DDR4 on Octeon 3. It can be later
extended to support also DDR3 and Octeon 2 platforms.

Part 1 adds the base U-Boot RAM driver, which will be instantiated by
the DT based probing.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2020-10-07 20:25:57 +02:00