Commit graph

83 commits

Author SHA1 Message Date
Simon Glass
f45e747d6d x86: Add support for newer CAR schemes
Newer Intel SoCs have different ways of setting up cache-as-ram (CAR).
Add support for these along with suitable configuration options.

To make the code cleaner, adjust a few definitions in processor.h so that
they can be used from assembler.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:18 +08:00
Simon Glass
d496162c85 x86: spi: Add helper functions for Intel Fast SPI
Most x86 CPUs use a mechanism where the SPI flash is mapped into the very
top of 32-bit address space, so that it can be executed in place and read
simply by copying from memory. For an 8MB ROM the mapping starts at
0xff800000.

However some recent Intel CPUs do not use a simple 1:1 memory map. Instead
the map starts at a different address and not all of the SPI flash is
accessible through the map. This 'Fast SPI' feature requires that U-Boot
check the location of the map. It is also possible (optionally) to read
from the SPI flash using a driver.

Add support for booting from Fast SPI. The memory-mapped version is used
by both TPL and SPL on Apollo Lake.

In respect of a SPI flash driver, the actual SPI driver is ich.c - this
just adds a few helper functions and definitions.

This is used by Apollo Lake.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-15 11:44:08 +08:00
Simon Glass
67c4e9f815 common: Move board_get_usable_ram_top() out of common.h
Move this function into init.h which seems to be designed for this sort
of thing. Also update the header to declare struct global_data so that it
can be included without global_data.h being needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2019-12-02 18:25:04 -05:00
Simon Glass
a27520904f x86: Add new common CPU functions for turbo/burst mode
Add a few more CPU functions that are common on Intel CPUs. Also add
attribution for the code source.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: add missing MSR_IA32_MISC_ENABLE write back in cpu_set_eist();
        fix 2 typos in cpu_get_burst_mode_state() comments]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:57:47 +08:00
Simon Glass
2f0c2f03e7 x86: Add common functions for TDP and perf control
These functions are the same on modern Intel CPUs, so use common code to
set them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: return false instead of 0 in cpu_ivybridge_config_tdp_levels();
        fix 'muiltiplier' and 'desgn' typos]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:57:47 +08:00
Simon Glass
246ac08b03 x86: Add a common function to set CPU thermal target
This code appears in a few places, so move it to a common file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:57:46 +08:00
Simon Glass
e2493a7f5a x86: Use a common definition of MSR_IA32_PERF_CTL
Remove the duplicate definition as it is not needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:57:46 +08:00
Simon Glass
c3863eadbc x86: fsp: Save usable RAM and hob_list in the handoff area
The useable RAM is calculated when the RAM is inited. Save this value so
that it can be easily used in U-Boot proper.

Also save a pointer to the hob list so that it is accessible (before
relocation only) in U-Boot proper. This avoids having to scan it in SPL,
for everything U-Boot proper might need later.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: guard handoff_arch_save() with IS_ENABLED(CONFIG_USE_HOB)]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:57:36 +08:00
Simon Glass
d3abc5d1ee x86: Move common Intel CPU info code into a function
Add cpu_intel_get_info() to find out the CPU info on modern Intel CPUs.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: add parameter and return value descriptions]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2019-10-08 13:57:35 +08:00
Simon Glass
9fa31fc51d x86: Support TPL in Intel common code
Update the Makefie rules to ensure that the correct files are built when
TPL is being used.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08 13:02:16 +08:00
Simon Glass
17903c06e8 x86: Add common Intel code for SPL
Add an implementation of arch_cpu_init_f() so that the x86 SPL code builds
and identifies the CPU.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08 13:02:14 +08:00
Simon Glass
d68574a72d x86: Allow 16-bit init to be in TPL
At present we support having 16-bit init be in SPL or U-Boot proper, but
not TPL. Add support for this so that TPL can boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08 13:02:13 +08:00
Simon Glass
11b7cc37f1 x86: Update a stale comment about ifdtool
We use binman to build the x86 image now. Update a comment which still
refers to ifdtool.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-05-08 13:02:10 +08:00
Ivan Gorinov
8199a145c4 x86: Use microcode update from device tree for all processors
Built without a ROM image with FSP (u-boot.rom), the U-Boot loader applies
the microcode update data block encoded in Device Tree to the bootstrap
processor but not passed to the other CPUs when multiprocessing is enabled.

If the bootstrap processor successfully performs a microcode update
from Device Tree, use the same data block for the other processors.

Signed-off-by: Ivan Gorinov <ivan.gorinov@intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fixed build errors on edison and qemu-x86]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2018-07-02 09:23:28 +08:00
Bin Meng
3ebd892fda x86: Rename efi-x86 target to efi-x86_app
To avoid confusion, let's rename the efi-x86 target to efi-x86_app.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-17 21:16:04 +08:00
Bin Meng
a8542ad81f x86: ivybridge: Drop CONFIG_USBDEBUG
This is not used anywhere. Clean this up.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-13 09:50:57 +08:00
Tom Rini
83d290c56f SPDX: Convert all of our single license tags to Linux Kernel style
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-07 09:34:12 -04:00
Masahiro Yamada
b08c8c4870 libfdt: move headers to <linux/libfdt.h> and <linux/libfdt_env.h>
Thomas reported U-Boot failed to build host tools if libfdt-devel
package is installed because tools include libfdt headers from
/usr/include/ instead of using internal ones.

This commit moves the header code:
  include/libfdt.h         -> include/linux/libfdt.h
  include/libfdt_env.h     -> include/linux/libfdt_env.h

and replaces include directives:
  #include <libfdt.h>      -> #include <linux/libfdt.h>
  #include <libfdt_env.h>  -> #include <linux/libfdt_env.h>

Reported-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-03-05 10:16:28 -05:00
Simon Glass
e160f7d430 dm: core: Replace of_offset with accessor
At present devices use a simple integer offset to record the device tree
node associated with the device. In preparation for supporting a live
device tree, which uses a node pointer instead, refactor existing code to
access this field through an inline function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-02-08 06:12:14 -07:00
Simon Glass
2eff989585 x86: Use X86_32BIT_INIT instead of X86_RESET_VECTOR
Use this new option to control the location of 32-bit init. This will allow
us to place this in SPL if needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-02-06 11:38:46 +08:00
Simon Glass
e6294e0579 x86: ivybridge: Allow microcode to be collated
Generally the microcode is combined into a single block only (and removed
from the device tree) when there are multiple blocks. But this is not a
requirement.

Adjust the ivybridge code to avoid assuming this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-08-30 09:26:05 +08:00
Simon Glass
fda4fa8195 x86: Add debugging when a microcode update fails
Add a debug() at this point to help figure out what is wrong.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher<hs@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-08-30 09:26:05 +08:00
Simon Glass
a219639d42 dm: Rename disk uclass to ahci
This started as 'ahci' and was renamed to 'disk' during code review. But it
seems that this is too generic. Now that we have a 'blk' uclass, we can use
that as the generic piece, and revert to ahci for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-05-17 09:54:43 -06:00
Simon Glass
65dd1507e3 x86: Add common SDRAM-init code
The code to call the memory reference code is common to several Intel CPUs.
Add common code for performing this init. Intel calls this 'Pre-EFI-Init'
(PEI), where EFI stands for Extensible Firmware Interface.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:27 +08:00
Simon Glass
7e4a6ae62c x86: Move common PCH code into a common place
The SATA indexed register write functions are common to several Intel PCHs.
Move this into a common location.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:27 +08:00
Simon Glass
e77b62e290 x86: Update microcode for secondary CPUs
Each CPU needs to have its microcode loaded. Add support for this so that
all CPUs will have the same version.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:25 +08:00
Simon Glass
6bcb675b2f x86: Record the CPU details when starting each core
As each core starts up, record its microcode version and CPU ID so these can
be presented with the 'cpu detail' command.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:25 +08:00
Simon Glass
8b900a4175 x86: Move Intel Management Engine code to a common place
Some of the Intel ME code is common to several Intel CPUs. Move it into a
common location. Add a header file for report_platform.c also.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[squashed in http://patchwork.ozlabs.org/patch/598372/]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:24 +08:00
Simon Glass
2a605d4d88 x86: Rename PORT_RESET to IO_PORT_RESET
This same name is used in USB. Add a prefix to distinguish it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:24 +08:00
Simon Glass
50dd3da004 x86: Move common CPU code to its own place
Some of the Intel CPU code is common to several Intel CPUs. Move it into a
common location along with required declarations.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:24 +08:00
Simon Glass
8c30b57130 x86: Move common LPC code to its own place
Some of the LPC code is common to several Intel LPC devices. Move it into a
common location.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:24 +08:00
Simon Glass
9e66506d33 x86: Move microcode code to a common location
This code is used on several Intel CPUs. Move it into a common location.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:24 +08:00
Simon Glass
1223d737a3 x86: Move cache-as-RAM code into a common location
This cache-as-RAM (CAR) code is common to several Intel chips. Create a new
intel_common directory and move it in there.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:24 +08:00