Add a second dram bank of usable memory beyond the blob of space for
peripheral near 4GB. Any memory that exists beyond the 4GB mark is added
to the second bank.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Newer DRAM initialization blobs from vendor can encode sdram info in a
new version 3 format. The new format makes use of more bits in sys_reg3
compared to the version 2 format.
Add basic support for detecting the version 3 format and decoding the
high bits used for ddrtype.
This fixes decode of sdram size on my RK3568 boards that have LPDDR4X.
Details on the new format was deciphered from vendor u-boot commit [1].
[1] c69667e0e2
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
CONFIG_RAM_PX30_DDR4 got renamed to CONFIG_RAM_ROCKCHIP_DDR4 in commit
26f92be07e ("ram: rockchip: Add common ddr type configs"). Since both
patchsets were merged unbeknownst to the other, the conflict wasn't
detected while testing each patchset individually and could only be
observed after a merge to master branch.
Fixes: c925be73a0 ("rockchip: add support for PX30 Ringneck SoM on Haikou Devkit")
Cc: Quentin Schulz <foss+uboot@0leil.net>
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
The RK3288 TRM states that, for 8-bit DDR modes:
The CLKDIV register should always be programmed with a value
higher than zero (0); that is, a clock divider should always be
used for 8-bit DDR mode.
In Linux, the driver applies this logic for all SoCs using the driver
and does not distinguish RK3288, so presumably this requirement is the
same for all other Rockchip SoCs using this IP.
Add the necessary code to double the clock frequency when 8-bit DDR is
selected. The dw_mmc core already handles setting CLKDIV correctly
given the input clock and desired bus clock.
Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Provide human-readable manufacturer and product names for the
FriendlyELEC NanoPi R4S.
Enable CONFIG_SYSINFO and CONFIG_SYSINFO_SMBIOS by default.
Signed-off-by: Christian Kohlschütter <christian@kohlschutter.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
- btrfs bugfix, silence a bunch of gcc-12.2 linker warnings finally,
relax one of the trace test time requirements (so CI doesn't fail due
to test being slightly slow, but still correct), and correct env on
MMC and checking for where GPT can be
This function allows updating bootloader from u-boot
on production devices without need in host PC.
Be aware! It works only with re-crypt BCT.
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Signed-off-by: Ramin Khonsari <raminterex@yahoo.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
This function allows updating bootloader from u-boot
on production devices without need in host PC.
Be aware! It works only with re-crypted BCT.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Ramin Khonsari <raminterex@yahoo.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
Add support for encryption, decryption and signinig with
non-zero key saving backward compatibility.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
Configure PMIC voltages for early stages using updated
early i2c write.
Tested-by: Thierry Reding <treding@nvidia.com> # Beaver T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom <twarren@nvidia.com>
This implementation allows pwr i2c writing on early SPL
stages when DM is not yet setup.
Such writing is needed to configure main voltages of PMIC
on early SPL for bootloader to boot properly.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
Late init function allows passing values like identifiers and
perform device specific configurations of pre-boot stage.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
All Nvidia boards use the same manufacturer, vendor ID and product ID
for the gadgets. Make them the defaults to remove some boilerplate from
the defconfigs.
Inspired by commit e02687bda9 ("sunxi: provide default USB gadget
setup") which did the same for Allwinner boards.
Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124
Signed-off-by: Maxim Schwalm <maxim.schwalm@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
Original t20 slink could work with commands only
fully divisible by 8. This patch removes such
restriction, so commands of any bitlength now
can be passed and processed.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
Default parent clock for the PWM on Tegra is a 32kHz clock and
is unable to support the requested PWM period.
Fix PWM support on Tegra20, Tegra30, Tegra114, Tegra124 and Tegra210 by
updating the parent clock for the PWM to be the PLL_P.
This commit is equivalent to Linux kernel commit:
https://lore.kernel.org/all/20221010100046.6477-1-jonathanh@nvidia.com/
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # ASUS TF201 T30
Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
On T30 unlike T20 dsi panels are wider used on devices
and PLLD is used as DISP1 parent more often, so lets
enable it as well for this cases.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF700T T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X T30
Tested-by: Thierry Reding <treding@nvidia.com> # Beaver T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
Get periph clock id and its parent from device tree.
This works by looking up the peripheral's 'clocks' node and
reading out the second and fourth cells, which are the
peripheral and PLL clock numbers.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
This function allows to convert a device tree clock ID to PLL ID.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
According to mainline clock tables and TRM HOST1X
parent is PLLC, while DISP1 usually uses PLLP as
parent clock.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Tested-by: Thierry Reding <treding@nvidia.com> # Beaver T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
This mappings were missing for some reason.
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom <twarren@nvidia.com>
Apply the GPT U-Boot environment GUID type look up only on eMMC user
HW partition, do not apply the look up on eMMC boot HW partitions as
mmc_offset_try_partition() assumes either SD partitions or eMMC user
HW partition.
This fixes environment operation on systems where CONFIG_SYS_MMC_ENV_PART
is non-zero and CONFIG_SYS_REDUNDAND_ENVIRONMENT is set.
Fixes: 80105d8fd5 ("env: mmc: select GPT env partition by type guid")
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
We expect the profile and bootstage to agree on timing, but when
running on slow machines there can be a larger descrepency. Increase the
tolerance to fix this.
Fixes: 9cea4797ae ("trace: Add a test")
Signed-off-by: Simon Glass <sjg@chromium.org>
To match how we link EFI executables elsewhere, and to silence a linker
warning, pass -z execstack here as well.
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
When moving to gcc-12.2 we started trying to quiet some of the new
linker warnings, that are not relevant to us. However, a
misunderstanding of the mechanics at play meant that I intentionally
omitted passing -z noexecstack to the linker, when we do need to. Add
this flag and in turn remove warnings from the linker.
Fixes: 1e1c51f8ac ("Makefile: link with --no-warn-rwx-segments")
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[BUG]
There is a bug report that btrfs driver caused hang during file read:
This breaks btrfs on the HiFive Unmatched.
=> pci enum
PCIE-0: Link up (Gen1-x8, Bus0)
=> nvme scan
=> load nvme 0:2 0x8c000000 /boot/dtb/sifive/hifive-unmatched-a00.dtb
[hangs]
[CAUSE]
The reporter provided some debug output:
read_extent_data: cur=615817216, orig_len=16384, cur_len=16384
read_extent_data: btrfs_map_block: cur_len=479944704; ret=0
read_extent_data: ret=0
read_extent_data: cur=615833600, orig_len=4096, cur_len=4096
read_extent_data: btrfs_map_block: cur_len=479928320; ret=0
Note the second and the last line, the @cur_len is 450+MiB, which is
almost a chunk size.
And inside __btrfs_map_block(), we limits the returned value to stripe
length, but that's depending on the chunk type:
if (map->type & (BTRFS_BLOCK_GROUP_RAID0 | BTRFS_BLOCK_GROUP_RAID1 |
BTRFS_BLOCK_GROUP_RAID1C3 | BTRFS_BLOCK_GROUP_RAID1C4 |
BTRFS_BLOCK_GROUP_RAID5 | BTRFS_BLOCK_GROUP_RAID6 |
BTRFS_BLOCK_GROUP_RAID10 |
BTRFS_BLOCK_GROUP_DUP)) {
/* we limit the length of each bio to what fits in a stripe */
*length = min_t(u64, ce->size - offset,
map->stripe_len - stripe_offset);
} else {
*length = ce->size - offset;
}
This means, if the chunk is SINGLE profile, then we don't limit the
returned length at all, and even for other profiles, we can still return
a length much larger than the requested one.
[FIX]
Properly clamp the returned length, preventing it from returning a much
larger range than expected.
Reported-by: Andreas Schwab <schwab@linux-m68k.org>
Signed-off-by: Qu Wenruo <wqu@suse.com>
This file was missed during the conversion process. Add the symbol to
defconfig.
Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add devicetree for chameleonv3 with the 270-2I2-D11E variant of the
Mercury+ AA1 module
Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This file is included by the different chameleonv3 variants. Change the
name to .dtsi.
Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Set the bitstream name per Chameleon variant. This allows the same
boot filesystem with all bitstream variants to be used on different
boards.
Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Move the environment to an easily editable text file in the boot
partition
Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
As the "reset-gpios" property is optional, don't return the
error and just skip the gpio reset sequence.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Documentation
* Add a document for the RISC-V architecture
* Move gateworks and bcm7xxx documentation to HTML
UEFI
* measure the loaded device-tree
* make CapsuleMax configurable and provide sensible default
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEEbcT5xx8ppvoGt20zxIHbvCwFGsQFAmPym08ACgkQxIHbvCwF
GsTFNhAAgq5cghkgUFDgz49ZJ6Rc7quo30UM4zUjZqp2ZU0kWYcEX3afcjPaSvpb
+nEDJgQIR1EfxGz7CUI8HrkhMeyGa57696ABIqSAI7Ml8KY7T8XuWDY1p+ybGQmP
PhleKQ+XzEddKAmMLeiXNUUHWu+X8kSsEtARFOehlTiVfiNQzu3bS4lfWnVNrrgC
/68EQEQ6SHazyRtrgp2oSv6VOSQCgfeCOhrkdYTeu9eBDYC0MzBtVv31clW7WoTz
ftykJUI1mcR6g4PgXnqvh9BiQlmI1SiU5fI1UwNwD8/021IwuKpwQ5fjYkWn9qff
oP2N1Ymf10fXgg74T5mihlSnlimV9Zh5wFgHPJSWCCXC9Fj8LQj5/N2oW6o8eKqm
EytrfpCMztIzzYUIsG6pHXEwjNQPJQl5Ow8Vda6r8wx7kqLqKRdZPxPaGhC7BTdX
cAJBRtZjtL8z66JtmT+BqCXJDkqfl4cCOjNeybzuJIajMH3DlF4Ou73jyZbRJz29
iW63F+u55LDhBJhOxEOofYB82NLRwIQx7Mih9YrMfMfWCmQNciAfevsrrBzcLjOC
ThwBnq2QFh80odb+097lw14YwW+L2yjPwUIqjR3RqAoylRxQYq2kWp1iL3YHP/uk
pj4GCR7wftfSRZI8EhhC6c7Sh4UrEhBrwUgvD+3TklwD5yk4xhw=
=0BHD
-----END PGP SIGNATURE-----
Merge tag 'efi-2023-04-rc3' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request for efi-2023-04-rc3
Documentation
* Add a document for the RISC-V architecture
* Move gateworks and bcm7xxx documentation to HTML
UEFI
* measure the loaded device-tree
* make CapsuleMax configurable and provide sensible default
Adds CONFIG_EFI_CAPSULE_MAX to configure the max index value used in
EFI capsule reports. Prior to this change is the hard coded value was
65535 which would exceed available storage for variables. Now the
default value is 15 which should work fine with most systems.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Measures the DTB passed to the EFI application upon new boolean config
switch CONFIG_EFI_TCG2_PROTOCOL_MEASURE_DTB. For platforms where the
content of the DTB passed to the OS can change across reboots, there is
not point measuring it hence the config switch to allow platform to not
embed this feature.
Co-developed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
QueryVariableInfo with EFI_VARIABLE_HARDWARE_ERROR_RECORD is
accepted, remove wrong attribute check.
Fixes: 454a9442fb ("efi_loader: update attribute check for QueryVariableInfo()")
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
This patch adds a brief introduction to the RISC-V architecture and
the typical boot process used on a variety of RISC-V platforms.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Convert the documentation for the Broadcom BCM7445 and BCM7260 boards
to reStructuredText format and add the new filename to
doc/board/broadcom/index.rst.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Fix typo and whitespace in the document.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
