Commit graph

372 commits

Author SHA1 Message Date
Marek Vasut
e026b984e6 ddr: altera: Repair DQ window centering code
The code uses a lot of signed numbers, which ended up in variables
of unsigned type, which resulted in all sorts of underflows. This
in turn caused incorrect calibration on certain boards. Moreover,
repair the readout of the DQ delay, which was being pulled from
wrong register.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
2016-04-20 11:28:45 +02:00
Marek Vasut
85f76628a0 ddr: altera: Staticize global variables
Just staticize global variables in sequencer, since there is no
point in having these symbols available outside of the DDR code.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
2016-04-20 11:28:45 +02:00
Marek Vasut
ea9aa2414e ddr: altera: Make DLEVEL behavior inclusive
Originally, the DLEVEL selects the debug level within the sequencer code,
but only displays the messages on that particular debug level. Tweak the
handling such that for particular debug level, debug messages on that
level and lower are displayed. This allows better regulation of debug
message verbosity.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
2016-04-20 11:28:45 +02:00
Marek Vasut
70ed80af46 ddr: altera: Zero DM IN delay in scc_mgr_zero_group()
This one last set of delay configuration registers was not properly
zeroed out originally, fix it and zero them out.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
2016-04-20 11:28:45 +02:00
Marek Vasut
f3f777cdf0 ddr: altera: Remove unnecessary ODT mode config
There is no point in resetting the ODT setting if the write test
failed, since the code will always retry the calibration and thus
reconfigure the ODT anyway OR the code will fail calibration and
halt.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
2016-04-20 11:28:44 +02:00
Marek Vasut
f5f8c411de ddr: altera: Remove unnecessary update of the SCC
Every invocation of the scc_mgr_set_dqs_en_delay_all_ranks() is
followed by SCC manager update. Moreover, only this function
triggers the SCC manager update internally. Thus, remove the
internal invocation to avoid triggering the update twice.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
2016-04-20 11:28:44 +02:00
Marek Vasut
164eb23f49 ddr: altera: Fix DRAM end value in protection rule
The hi address bitfield in the protection rule must be set to
the last address in the region which the rule represents. The
behavior is now in-line with code generated by Quartus 15.1 .

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
2016-04-20 11:28:44 +02:00
Marek Vasut
8e9e62c946 ddr: altera: Fix scc_mgr_set() argument order
The code should be setting registers to zero, not one register to value.
Swap the order of arguments to correct the behavior. The behavior is now
in-line with code generated by Quartus 15.1 .

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
2016-04-20 11:28:44 +02:00
Marek Vasut
bba7711092 ddr: altera: Tweak DQS tracking enable handling
In the most unlikely case the DQS tracking was to be disabled,
make sure we do not errornously re-enable it. Note that DQS
tracking is enabled on all systems observed thus far.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
2016-04-20 11:28:44 +02:00
Marek Vasut
abaf83619c ddr: altera: Replace ad-hoc constant with macro
The bit 22 is in fact DQS tracking enable bit (dqstrken) and there
is a macro for this bit already, so use it.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
2016-04-20 11:28:43 +02:00
Alexander Merkle
dd8d8da3d7 Fix typo choosen in comments and printf logs
Minor change: chosen is written with one "o".
No code change here, only comment & printf.

Signed-off-by: Alexander Merkle <alexander.merkle@lauterbach.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-27 09:12:23 -04:00
Dirk Eibach
44876bf9e8 arm: mvebu: Fix ddr3_init() cpu config
Armada 38x has a maximum of two cores. Probably copy/paste
bug from Armada XP.

Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Stefan Roese <sr@denx.de>
2016-03-24 09:36:40 +01:00
Shengzhou Liu
dd8e740c78 driver/ddr/fsl: Add workaround for erratum A-009803
During initial DDR training, false parity errors may be detected.
This patch adds workaround to fix the erratum.
Tested on LS2085QDS and LS2080RDB.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-21 12:42:13 -07:00
Shengzhou Liu
eb118807a4 driver/ddr/fsl: Add address parity support for DDR4 UDIMM/discrete
Add support of address parity for DDR4 UDIMM or discrete memory.
It requires to configurate corresponding MR5[2:0] and
TIMING_CFG_7[PAR_LAT]. Parity can be turned on by hwconfig,
e.g. hwconfig=fsl_ddr:parity=on.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-03-21 12:42:13 -07:00
Bin Meng
a187559e3d Use correct spelling of "U-Boot"
Correct spelling of "U-Boot" shall be used in all written text
(documentation, comments in source files etc.).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2016-02-06 12:00:59 +01:00
Purna Chandra Mandal
9ffa7a35ef drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32.
This driver initializes PIC32 DDR2 SDRAM controller and internal DDR2 Phy module.
DDR2 controller operates in half-rate mode (upto 533MHZ frequency).

Signed-off-by: Paul Thacker <paul.thacker@microchip.com>
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-02-01 22:14:01 +01:00
Ed Swarthout
81dfdee0dc drivers/ddr/fsl: fsl_ddr_sdram_size remove unused controllers
Following commit 61bd2f75, exclude unused DDR controller from
calculating RAM size for SPL boot.

Signed-off-by: Ed Swarthout <Ed.Swarthout@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-25 08:24:16 -08:00
Shengzhou Liu
a994b3deb0 driver/ddr/fsl: Add workaround for A009663
Erratum A-009663 workaround requires to set DDR_INTERVAL[BSTOPRE] to 0
before setting DDR_SDRAM_CFG[MEM_EN] and set DDR_INTERVAL[BSTOPRE]
to the desired value after DDR initialization has completed.

When DDR controller is configured to operate in auto-precharge
mode(DDR_INTERVAL[BSTOPRE]=0), this workaround is not needed.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-25 08:24:15 -08:00
Shengzhou Liu
0d3972cfcd fsl/ddr: Add workaround for ERRATUM_A009942
During the receive data training, the DDRC may complete on a
non-optimal setting that could lead to data corruption or
initialization failure.

Workaround: before setting MEM_EN, set DEBUG_29 register with
specific value for different data rates.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-01-25 08:24:14 -08:00
Tom Rini
5b8031ccb4 Add more SPDX-License-Identifier tags
In a number of places we had wordings of the GPL (or LGPL in a few
cases) license text that were split in such a way that it wasn't caught
previously.  Convert all of these to the correct SPDX-License-Identifier
tag.

Signed-off-by: Tom Rini <trini@konsulko.com>
2016-01-19 08:31:21 -05:00
Marek Vasut
1720fad0f1 ddr: altera: Init the rule ID in debug code
Init the rule ID, otherwise the debug code will always dump the
protection settings entry 0.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux@gmail.com>
2016-01-16 07:07:22 +01:00
Phil Sutter
4444d230ac mvebu: axp: Rename MV_DDR_32BIT to CONFIG_DDR_32BIT
This should make it clear that this symbol is meant to be defined by
board headers.

Signed-off-by: Phil Sutter <phil@nwl.cc>
Acked-by: Stefan Roese <sr@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-14 14:08:59 +01:00
Phil Sutter
7e1e59a7b7 axp: Fix debugging support in DDR3 write leveling
If MV_DEBUG_WL is defined, DEBUG_WL_S and DEBUG_WL_D macros are missing.
In addition to that, get rid of debug output printing non-existent
counter variable.

Signed-off-by: Phil Sutter <phil@nwl.cc>
Acked-by: Stefan Roese <sr@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-01-14 14:08:59 +01:00
Stefan Roese
698ffab239 arm: mvebu: Make ECC support configurable on Armada XP
Currently, ECC support is enabled for all Armada XP boards. So the
DDR3 driver tries to configure the controller with ECC support, even
on boards without ECC. This patch makes this ECC optional which now
can be configured on a board-per-board basis.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Phil Sutter <phil@nwl.cc>
2016-01-14 14:08:59 +01:00
Stefan Roese
cdf1d240ba arm: mvebu: ddr: Fix compilation warning
gcc 5.1 generates this new warning (for Armada 38x platforms):

drivers/ddr/marvell/a38x/ddr3_debug.c: In function 'hws_ddr3_tip_read_training_result':
drivers/ddr/marvell/a38x/ddr3_debug.c:177:40: warning: 'sizeof' on array
  function parameter 'result' will return size of 'enum hws_result (*)[1]' [-Wsizeof-array-argument]
  memcpy(result, training_result, sizeof(result));
                                        ^
drivers/ddr/marvell/a38x/ddr3_debug.c:171:31: note: declared here
  u32 dev_num, enum hws_result result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM])
                               ^

Since this functions is not referenced anywhere, lets just remove it.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2016-01-14 14:08:59 +01:00
Yao Yuan
000f4e7686 move erratum a008336 and a008514 to soc specific file
As the errata A008336 and A008514 do not apply to all LS series SoCs
(such as LS1021A, LS1043A) we move them to an soc specific file

Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-15 08:57:32 +08:00
Shengzhou Liu
a46b1852de fsl/ddr: updated ddr errata-A008378 for arm and power SoCs
DDR errata-A008378 applies to LS1021-20-22A-R1.0, T1023-R1.0,
T1024-R1.0, T1040-42-20-22-R1.0/R1.1, it has been fixed on
LS102x Rev2.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-12-13 18:27:28 -08:00
York Sun
6c6e006a20 driver/ddr/fsl: Update timing config for heavy load
In case four chip-selects are all active, the turnaround times need to
increase to avoid overlapping under heavy load.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-12-13 18:27:27 -08:00
York Sun
7cc079989d driver/ddr/fsl: Update workaround for A008511 for vref range
The workaround requires different setting for range 1 vs 2.
Also adjust timeout value for waiting for controller to be idle.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-12-13 18:27:27 -08:00
York Sun
8a51429e00 driver/ddr/fsl: Update MR5 RTT park
For four chip-selects enabled case, RTT is parked on all of them.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-12-13 18:27:27 -08:00
York Sun
0fb7197436 driver/ddr/fsl: Update DDR4 MR6 for Vref range
MR6 bit 6 is set accrodingly for range 1 or 2, per JEDEC spec.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-12-13 18:27:27 -08:00
York Sun
19601dd99c driver/ddr/fsl: Update DDR4 RTT values
DDR4 has different RTT value and code according to JEDEC spec. Update
the macros and options .

Signed-off-by: York Sun <yorksun@freescale.com>
2015-12-13 18:27:27 -08:00
York Sun
da305b9f57 drivers/ddr/fsl: Fix typo in BIST test for DDR4
BIST test code has a typo, resulting the binding registers not
maintained as expected. This typo results BIST runs twice on
the covered memory.

Signed-off-by: York Sun <yorksun@freescale.com>
Reported-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
2015-11-30 09:11:12 -08:00
York Sun
61bd2f75f5 drivers/ddr/fsl: Enable detection of one DDR controller operation for LSCH3
Freescale LSCH3 platforms use two DDR controlers interleaving mode out of
reset. It can be configured to disable one controller. To support this
operation, the driver needs to detect and skip the disabled controller.

Signed-off-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:11 -08:00
Prabhakar Kushwaha
06b5301043 armv8: ls2085a: Add support of LS2085A SoC
Freescale's LS2085A is a another personality of LS2080A SoC with
support of AIOP and DP-DDR.
This Patch adds support of LS2085A Personality.

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: Updated MAINTAINERS files
           Dropped #ifdef in cpu.h
           Add CONFIG_SYS_NS16550=y in defconfig]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:10:47 -08:00
Prabhakar Kushwaha
449372148f armv8: LS2080A: Rename LS2085A to reflect LS2080A
LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP
personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc.
So renaming existing LS2085A code base to reflect LS2080A (Prime personality)

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: Dropped #ifdef in cpu.c for cpu_type_list]
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 08:53:04 -08:00
Dirk Eibach
a21b4f0f99 arm: mvebu: Fix SAR1_CPU_CORE_MASK
SAR1_CPU_CORE_MASK was wrong, probably copy/paste
from another architecture.

Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Reviewed-by: Stefan Roese <sr@denx.de>
2015-11-17 23:41:41 +01:00
Kevin Smith
544acb07ec arm: mvebu: a38x: Remove unsupported topologies
A lot of extra configuration information was left over in the
Marvell serdes and DDR3 initialization code for boards that
U-boot does not support.  Remove this extra config information,
and the concept of fixing up board topologies with information
loaded from an EEPROM.  If this needs to be done, it should be
handled in the board file, not in core code.

Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Acked-by: Stefan Roese <sr@denx.de>
Cc: Dirk Eibach <eibach@gdsys.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-11-17 23:41:41 +01:00
Tom Rini
da58dec866 Various Makefiles: Add SPDX-License-Identifier tags
After consulting with some of the SPDX team, the conclusion is that
Makefiles are worth adding SPDX-License-Identifier tags too, and most of
ours have one.  This adds tags to ones that lack them and converts a few
that had full (or in one case, very partial) license blobs into the
equivalent tag.

Cc: Kate Stewart <kstewart@linuxfoundation.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2015-11-10 09:19:52 -05:00
Joakim Tjernlund
e368c20607 drivers/ddr/fsl_ddr: Make SR_IE configurable
SR_IE(Self-refresh interrupt enable) is needed for
Hardware Based Self-Refresh. Make it configurable and let
board code handle the rest.

Signed-off-by: Joakim Tjernlund <joakim.tjernlund@transmode.se>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-10-30 09:19:41 -07:00
Heiko Schocher
92a3188d7d bitops: introduce BIT() definition
introduce BIT() definition, used in at91_udc gadget
driver.

Signed-off-by: Heiko Schocher <hs@denx.de>
[remove all other occurrences of BIT(x) definition]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>
2015-09-11 17:15:32 -04:00
Marek Vasut
35e47b7132 ddr: altera: Repair uninited variable
Fix the following problem:
drivers/ddr/altera/sequencer.c: In function 'sdram_calibration_full':
drivers/ddr/altera/sequencer.c:1943:25: warning: 'found_failing_read' may be used uninitialized in this function [-Wmaybe-uninitialized]
  if (found_passing_read && found_failing_read)
                         ^
drivers/ddr/altera/sequencer.c:1803:26: note: 'found_failing_read' was declared here
  u32 found_passing_read, found_failing_read, initial_failing_dtap;
                          ^

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-23 11:56:19 +02:00
Marek Vasut
6d7a33301a ddr: altera: Replace float multiplication with integer one
This gem is really really rare, there was an actual float used in
the Altera DDR init code, which pulled in floating point ops from
the libgcc, just wow.

Since we don't support floating point operations the same way Linux
does not support them, replace this with an integer multiplication
and division combo. This removes some 2kiB of size from the SPL as
the floating point ops are no longer pulled in from libgcc.

This was detected by enabling CONFIG_USE_PRIVATE_LIBGCC=y , which
does not contain the floating point bits.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-23 11:56:19 +02:00
Stefan Roese
0ceb2dae78 arm: mvebu: Add complete SDRAM ECC scrubbing
This patch introduces the SDRAM scrubbing for ECC enabled board
to fill/initialize the ECC bytes. This is done via the XOR engine
to speed up the process. The scrubbing is a 2-stage process:

1) SPL scrubs the area 0 - 0x100.0000 (16MiB) for the main U-Boot
2) U-Boot scrubs the remaining SDRAM area(s)

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-08-17 18:49:33 +02:00
Stefan Roese
a3ed9789e7 arm: mvebu: sdram: Enable ECC support on Armada XP
This is tested on the DB-MV784MP-GP eval board. To really enable ECC
support on this board the I2C EEPROM needs to get changed. As it
saves the enabling of ECC support internally. For this the following
commands can be used to enable ECC support on this board:

Its recommended for first save (print) the value(s) in this EEPROM
address:

=> i2c md 4e 0.1 2
0000: 05 00    ..

To enable ECC support you need to set bit 1 in the 2nd byte:

Marvell>> i2c mw 4e 1.1 02
Marvell>> i2c md 4e 0.1 2
0000: 05 02    ..

To disable ECC support again, please use this command:

Marvell>> i2c mw 4e 1.1 00
Marvell>> i2c md 4e 0.1 2
0000: 05 00    ..

On other AXP boards, simply plugging an ECC DIMM should be enough to
enable ECC support.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
2015-08-17 18:41:33 +02:00
Marek Vasut
139823ecb2 ddr: altera: sequencer: Clean checkpatch issues
Fix most of the dangling checkpatch issues, no functional change.
There are still 7 warnings, 1 checks , but those are left in place
for the sake of readability of the code.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-08-08 14:14:30 +02:00
Marek Vasut
5ded7320c8 ddr: altera: sequencer: Clean data types
Replace uintNN_t with uNN. No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-08-08 14:14:29 +02:00
Marek Vasut
96fd4362cf ddr: altera: sequencer: Pluck out misc macros from code
Actually convert the sequencer code to use socfpga_sdram_misc_config
instead of the various macros. This is just an sed exercise here, no
manual coding needed.

This patch actually removes the need to include any board-specific
files in sequencer.c , so sequencer.c namespace is now no longer
poluted by QTS-generated macros.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-08-08 14:14:29 +02:00
Marek Vasut
3cd0906cc2 ddr: altera: sequencer: Zap SEQ_T(INIT|RESET)_CNTR._VAL
This is another macro used to obfuscate the real code. The
T(INIT|RESET)_CNTR._VAL is always defined, so this indirection
is unnecessary. Get rid of this.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-08-08 14:14:29 +02:00
Marek Vasut
98cfc9058b ddr: altera: sequencer: Zap VFIFO_SIZE
Just use READ_VALID_FIFO_SIZE directly, no need for this macro obfuscation.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-08-08 14:14:29 +02:00
Marek Vasut
042ff2d0fa ddr: altera: sequencer: Wrap misc remaining macros
Introduce structure socfpga_sdram_misc_config to wrap the remaining
misc configuration values in board file. Again, introduce a function,
socfpga_get_sdram_misc_config(), which returns this the structure. This
is almost the final step toward wrapping the nasty QTS generated macros
in board files and reducing the pollution of the namespace.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-08-08 14:14:29 +02:00
Marek Vasut
160695d886 ddr: altera: sequencer: Pluck out IO_* macros from code
Actually convert the sequencer code to use socfpga_sdram_io_config
instead of the IO_* macros. This is just an sed excercise here, no
manual coding needed.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-08-08 14:14:29 +02:00
Marek Vasut
10c14261f3 ddr: altera: sequencer: Wrap IO_* macros
Introduce structure socfpga_sdram_io_config to wrap the IO configuration
values in board file. Introduce socfpga_get_sdram_io_config() function,
which returns this the structure. This is another step toward wrapping
the nasty QTS generated macros in board files and reducing the pollution
of the namespace.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-08-08 14:14:29 +02:00
Marek Vasut
1fa0c8c4e3 ddr: altera: sequencer: Pluck out RW_MGR_* macros from code
Actually convert the sequencer code to use socfpga_sdram_rw_mgr_config
instead of the RW_MGR_* macros. This is just an sed exercise here, no
manual coding needed.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-08-08 14:14:29 +02:00
Marek Vasut
d718a26b0c ddr: altera: sequencer: Wrap RW_MGR_* macros
Introduce structure socfpga_sdram_rw_mgr_config to wrap the RW manager
configuration values in board file. Introduce a complementary function,
socfpga_get_sdram_rwmgr_config(), which returns this the structure.
This is another step toward wrapping the nasty QTS generated macros
in board files and reducing the pollution of the namespace.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-08-08 14:14:29 +02:00
Marek Vasut
04955cf247 ddr: altera: sequencer: Wrap ac_rom_init and inst_rom_init
Introduce two wrapper functions, socfpga_get_seq_ac_init() and
socfpga_get_seq_inst_init() to avoid direct inclusion of the
sequencer_auto_ac_init.h and sequencer_auto_inst_init.h QTS
generated files. This reduces namespace pollution again.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-08-08 14:14:28 +02:00
Marek Vasut
499b7a7c88 ddr: altera: sequencer: Zap bogus redefinition of RW_MGR_MEM_NUMBER_OF_RANKS
This is defined in the QTS-generated headers, so it must not be
re-defined in sequencer.h .

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-08-08 14:14:28 +02:00
Marek Vasut
f085ac3b14 ddr: altera: sequencer: Zap unused params and macros
These parameters are not used in the code, zap them and the
macros which are used by them as well.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-08-08 14:14:28 +02:00
Marek Vasut
9c76df518c ddr: altera: sequencer: Move qts-generated files to board dir
Move the files generated by QTS into the board directory, they should not
be part of the driver files at all.

Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-08-08 14:14:28 +02:00
Marek Vasut
08eb947004 ddr: altera: sdram: Make sdram_start and sdram_end into u32
Originally, both sdram_start and sdram_end were 64b values. The
sdram_start had no reason for being so, since our address space
is only 32b, so switching sdram_start to u32 is simple.

The sdram_end is a bit more complex, since it can actually be
set to (1 << 32) if someone really wanted to use an SoCFPGA with
4 GiB of DRAM and fixed the code around a little. But, the code
handling the protection rules internally decrements the sdram_end
variable anyway. Thus, instead of calling the code and passing in
the address of the SDRAM end, pass in the address already decremented
by one. This lets the sdram_end be 32b as well.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:28 +02:00
Marek Vasut
6d01595f63 ddr: altera: sdram: Minor cleanup in sdram_get_rule()
Fix the data types and zap unnecessary type change.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:28 +02:00
Marek Vasut
a003740aec ddr: altera: sdram: Minor cleanup in sdram_set_rule()
Zap an obscure unneeded cast and clean other minor nits in this function.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:28 +02:00
Marek Vasut
96b869b6e3 ddr: altera: sdram: Add missing kerneldoc
Add kerneldoc to functions which are missing it, but are already
cleaned up.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:28 +02:00
Marek Vasut
269de4f0ab ddr: altera: sdram: Clean up sdram_write_verify()
Clean the function up so that it's obvious what it is doing,
fix the formating strings in debug outputs, add kerneldoc.
Make the function return proper errno-compliant return values
and propagate this change throughout sdram.c

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:28 +02:00
Marek Vasut
f97606f237 ddr: altera: sdram: Clean up sdram_calculate_size() part 2
Clean up coding style, mostly clean up comments, add kerneldoc.
Also, zap assignment of the "cs" variable, which is outright
dead code, so just remove it.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:27 +02:00
Marek Vasut
bb056d9c07 ddr: altera: sdram: Clean up sdram_calculate_size() part 1
Pluck out all of the CONFIG_HPS_SDR_CTRLCFG_* macros. This change
makes sdram.c completely clear of these macros and allows removing
of the ugly include of sdram.h . The namespace is now a much nicer
place!

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:27 +02:00
Marek Vasut
5af914189e ddr: altera: sdram: Introduce socfpga_sdram_get_config()
Introduce socfpga_sdram_get_config() function implement in a board file,
which returns the socfpga_sdram_config structure. This is the last step
in cleaning up the socfpga_mmr_init_full(), but not the last step which
allows removing the inclusion of sdram.h from drivers/ddr/altera/sdram.c
thus far.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:27 +02:00
Marek Vasut
99f453e953 ddr: altera: sdram: Clean up sdram_mmr_init_full() part 8
Fix the return value so that standard errno return values can be used.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:27 +02:00
Marek Vasut
1e8a85f8c5 ddr: altera: sdram: Clean up sdram_mmr_init_full() part 7
Add kerneldoc.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:27 +02:00
Marek Vasut
1a302a4525 ddr: altera: sdram: Clean up sdram_mmr_init_full() part 6
Pull out the block of register programming into a separate function.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:27 +02:00
Marek Vasut
9d6b012c72 ddr: altera: sdram: Clean up sdram_mmr_init_full() part 5
Rework remaining two register setting functions such that they only
return the final register value. Move the register setting into the
block of register I/O in sdram_mmr_init_full().

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:27 +02:00
Marek Vasut
076470eecd ddr: altera: sdram: Clean up sdram_mmr_init_full() part 4
Merge sdr_set_*() functions which are just setting registers among
the sea of register setting in sdram_mmr_init_full(). There is no
need to keep them separate this way, there is nothing special about
them.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:27 +02:00
Marek Vasut
764aa9a974 ddr: altera: sdram: Clean up sdram_mmr_init_full() part 3
Pluck out the remaining CONFIG_HPS_SDR_CTRLCFG_ and put it into
the socfpga_sdram_config structure.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:27 +02:00
Marek Vasut
dc3b91d9b6 ddr: altera: sdram: Clean up sdram_mmr_init_full() part 2
Suck out all the CONFIG_HPS_SDR_CTRLCFG_* from sdram_mmr_init_full()
into the socfpga_sdram_config structure. There is still one ugly
macro left behind, but this will be taken care of in subsequent patch.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:26 +02:00
Marek Vasut
be9a9fc5e6 ddr: altera: sdram: Clean up sdram_mmr_init_full() part 1
Zap all the ad-hoc readbacks from the registers and other useless
and broken debug output. This is really not useful and is only
confusing.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:26 +02:00
Marek Vasut
04ae448997 ddr: altera: sdram: Introduce socfpga_sdram_config() structure
Introduce this seemingly massive structure, which holds required values
of all the registers of the SDRAM controller. The idea here is to avoid
including the sdram.h header file, which is full of ad-hoc macros that
polute the global namespace. Once the cleanup of sdram.c would be complete
and all registers would be loaded from this new socfpga_sdram_config, a
board file will only pass this structure into the sdram.c . This will
hide all the horrors generated by QTS in the board directory.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:26 +02:00
Marek Vasut
9a48a9ac6c ddr: altera: sdram: Clean up set_sdr_mp_threshold()
Get rid of the constant clrsetbits_le32(), instead prepare the whole
content of the register once and write it at the end of the function.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:26 +02:00
Marek Vasut
ad2ba5d607 ddr: altera: sdram: Clean up set_sdr_mp_pacing()
Get rid of the constant clrsetbits_le32(), instead prepare the whole
content of the register once and write it at the end of the function.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:26 +02:00
Marek Vasut
a5ba929671 ddr: altera: sdram: Clean up set_sdr_mp_weight()
Get rid of the constant clrsetbits_le32(), instead prepare the whole
content of the register once and write it at the end of the function.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:26 +02:00
Marek Vasut
1009e396dd ddr: altera: sdram: Clean up set_sdr_fifo_cfg()
Get rid of the constant clrsetbits_le32(), instead prepare the whole
content of the register once and write it at the end of the function.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:26 +02:00
Marek Vasut
b3bdb2204e ddr: altera: sdram: Clean up set_sdr_static_cfg()
Get rid of the constant clrsetbits_le32(), instead prepare the whole
content of the register once and write it at the end of the function.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:26 +02:00
Marek Vasut
0ef8830037 ddr: altera: sdram: Clean up set_sdr_addr_rw()
Get rid of the constant clrsetbits_le32(), instead prepare the whole
content of the register once and write it at the end of the function.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:26 +02:00
Marek Vasut
60bd0df018 ddr: altera: sdram: Clean up set_sdr_dram_timing*()
Get rid of the constant clrsetbits_le32(), instead prepare the whole
content of the register once and write it at the end of the function.
Merge set_sdr_dram_timing{1,2,3,4,lowpwr}() into single function
set_sdr_dram_timing() , since there's no point in keeping all this
stuff separate anymore.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:26 +02:00
Marek Vasut
067c853fe6 ddr: altera: sdram: Clean up set_sdr_ctrlcfg()
Get rid of the constant clrsetbits_le32(), instead prepare the whole
content of the register once and write it at the end of the function.
The big plan here is to remove all the CONFIG_HPS_SDR_ macros, hide
them in QTS compatibility layer in board implementation and pass only
a small structure into the driver.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:25 +02:00
Marek Vasut
f36716971d ddr: altera: sdram: Clean up compute_errata_rows() part 2
Remove all parameters of this function, since they are only constants
passed in from another function, so make them local. Also, rename the
function to get_errata_rows() as this is closer to what it does.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:25 +02:00
Marek Vasut
791d20e13d ddr: altera: sdram: Clean up compute_errata_rows() part 1
Clean up weird parenthesis and odd type casts from the function.
Fix comment style.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:25 +02:00
Marek Vasut
58d86144d4 ddr: altera: sdram: Switch to generic_hweight32()
Use generic function instead of CPU-specific one.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:25 +02:00
Marek Vasut
3de9622e97 ddr: altera: Clean up of delay_for_n_mem_clocks() part 5
Add kerneldoc.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:24 +02:00
Marek Vasut
0c1b81bdf3 ddr: altera: Clean up of delay_for_n_mem_clocks() part 4
Simplify the loop code, optimizing compiler can deal with this.
No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:24 +02:00
Marek Vasut
6a39be6ca9 ddr: altera: Clean up of delay_for_n_mem_clocks() part 3
Clean up the computation of c_loop, outer and inner variables.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:24 +02:00
Marek Vasut
cbcaf46043 ddr: altera: Clean up of delay_for_n_mem_clocks() part 2
Factor out (afi_clocks - 1) into a single place instead of having it
all around the function.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:24 +02:00
Marek Vasut
90a584b763 ddr: altera: Clean up of delay_for_n_mem_clocks() part 1
Fix data types, clean up comments a bit and fix coding style a bit.
No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:24 +02:00
Marek Vasut
f1f22f7204 ddr: altera: Minor clean up of rw_mgr_mem_handoff()
Add kerneldoc and perform a minor comment cleanup.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:24 +02:00
Marek Vasut
c984278a66 ddr: altera: Clean up rw_mgr_mem_calibrate_lfifo()
Minor coding style cleanup, add kerneldoc. No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:23 +02:00
Marek Vasut
78cdd7d0c8 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_end()
This function is implementing the DDR calibration Stage 3 as
described in Altera EMI_RM 2015.05.04 . The main body of this
function is almost identical to Stage 1.3 (DQ/DQS centering)
for all but two flags -- use_read_test and update_fom. Convert
this function to call rw_mgr_mem_calibrate_dq_dqs_centering()
with the correct flags set to trim down the code duplication.

Moreover, reorder the remnants in the function a little and
convert the function to return either 0 or -EIO in case of
success and failure respectively, to match the common return
value convention.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:23 +02:00
Marek Vasut
8371c2ee68 ddr: altera: Clean up rw_mgr_mem_calibrate_write_test_issue()
Brief clean, add kerneldoc.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:23 +02:00
Marek Vasut
4a82854b07 ddr: altera: Clean up rw_mgr_mem_calibrate_write_test() part 3
Add kerneldoc.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:23 +02:00
Marek Vasut
b9452ea09f ddr: altera: Clean up rw_mgr_mem_calibrate_write_test() part 2
Clean up coding style, mostly broken multiline formatting strings
in debug output. Also clean up data types and constify where applicable.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:23 +02:00
Marek Vasut
ad64769ce0 ddr: altera: Clean up rw_mgr_mem_calibrate_write_test() part 1
Move code around to get rid of the forward declaration. No change
to the actual code.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:23 +02:00
Marek Vasut
a386a50eb2 ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 5
Add kerneldoc.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:23 +02:00
Marek Vasut
d043ee5b49 ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 4
Fix return values to match the common return value convention.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:23 +02:00
Marek Vasut
c654087206 ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 3
Zap the useless addr variable.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:23 +02:00
Marek Vasut
c8570afa04 ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 2
Factor out common code for searching best DM/DQS window.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:22 +02:00
Marek Vasut
3b44f55c3b ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 1
Fix data types and constify where applicable, fix broken multiline
debug strings and fix comments. No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:22 +02:00
Marek Vasut
ac63b9ada5 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 11
Add kerneldoc, no functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:22 +02:00
Marek Vasut
9866824794 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 10
Fix the return value of the function to match common convention
where 0 means success and negative means error. Fix the return
values in case of an error to use errno.h codes.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:22 +02:00
Marek Vasut
0113c3e1fe ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 9
The read_group and write_group arguments are the same in all
cases when this function is invoked, just merge them into one
rw_group argument. Also, clean up the function argument data
types and constify them.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:22 +02:00
Marek Vasut
0c4be198f4 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 8
The search_stop_check() always resets the bit_chk to a new value,
so bit_chk will never survive between search_left_edge() and
search_right_edge() invocation. There is thus no need to pass
it into these functions, so make bit_chk local to them.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:22 +02:00
Marek Vasut
5d6db44485 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 7
Perform minor reordering of the function to make the code more
organised, no functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:22 +02:00
Marek Vasut
ffb8b66ea8 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 6
Factor out center_dq_windows(), which is common code between
stage 2 and stage 3 of the calibration again and cater for
the minor differences.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:22 +02:00
Marek Vasut
afb3eb84b8 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 5
Factor out the get_window_mid_index() for finding the best DQ
window centering. This is again code common to two stages, so
pull it out.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:22 +02:00
Marek Vasut
f0712c3502 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 4
First of all, don't break strings in the debug_cond() calls across
multiple lines. Next, zap a couple of really odd casts in the code.
Finally, make i into a signed variable, so it is possible to avoid
constructs of the form:
    for (i = FOO;; i--) { <code>; if (i == 0) break; }.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:21 +02:00
Marek Vasut
901dc36e7a ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 3
Factor out common code from search_left_edge() and search_right_edge()
which checks whether searching for the window edge should stop. The
code is almost identical, so pull it into separate function and cater
for the minor differences.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:21 +02:00
Marek Vasut
71120773bf ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 2
Factor out common code from rw_mgr_mem_calibrate_writes_center()
and rw_mgr_mem_calibrate_vfifo_center() for searching for the
left edge of the window. The code is almost identical, so pull
it into separate function and cater for the minor differences.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:21 +02:00
Marek Vasut
c4907898a1 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_center() part 1
Factor out common code from rw_mgr_mem_calibrate_writes_center()
and rw_mgr_mem_calibrate_vfifo_center() for searching for the
right edge of the window. The code is almost identical, so pull
it into separate function and cater for the minor differences.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:21 +02:00
Marek Vasut
db3a606158 ddr: altera: Clean up rw_mgr_mem_calibrate_writes()
Reorder the content of the function a little and fix the comments
so they at least become full sentences. Constify function args.
Fix the return value to match the common convention of 0 meaning
success.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:21 +02:00
Marek Vasut
783fcf59bd ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 5
Make the function documentation into kerneldoc.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:21 +02:00
Marek Vasut
ba522c769e ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 4
Clean up the inner loop a bit. No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:21 +02:00
Marek Vasut
7ce23bb6ef ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 3
The C language has signed types, so make use of them. Fix this
obscene loop, which tries to do away with unsigned type, but
just makes the code more cryptic.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:21 +02:00
Marek Vasut
3cb8bf3fc5 ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 2
Clean up data types and constify where applicable. No function change.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:21 +02:00
Marek Vasut
3853d65e20 ddr: altera: Clean up rw_mgr_mem_calibrate_read_test() part 1
Clean up the debug output handling at the end of the function
and factor out common function call from the condition.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:21 +02:00
Marek Vasut
96df60364d ddr: altera: Clean up rw_mgr_mem_calibrate_read_test_all_ranks()
Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:20 +02:00
Marek Vasut
33756893ad ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 7
Add kerneldoc, no functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:20 +02:00
Marek Vasut
914546e7f0 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 6
Fix the return value to match common conventions and propagate
this change through the code.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:20 +02:00
Marek Vasut
5735540fd9 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 5
Fix the data types, constify where applicable.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:20 +02:00
Marek Vasut
52e8f217f9 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 4
Implement common sdr_find_phase_delay() function and convert all
places which use such code to this unified function. No functional
change to the code.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:20 +02:00
Marek Vasut
37b7b13d48 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 3
Clean up odd multiline loop, no functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:20 +02:00
Marek Vasut
23e8ea901a ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 2
If d != 0 after sdr_working_phase() finishes, the else branch
of the condition has no impact on anything at all, since work_end
was already set independently of the value of "d" . Zap this
useless code.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:20 +02:00
Marek Vasut
2f3589ca54 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() part 1
Fix broken multiline debug strings, fix comments.
No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:20 +02:00
Marek Vasut
d145ca9fc3 ddr: altera: Clean up find_vfifo_read()
Fix data types, constify where applicable, fix comments and debug
strings. In case enough failing reads are detected, just return
right away instead of breaking from the loop. This lets us make
the error handling at the end much simpler.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:20 +02:00
Marek Vasut
8c887b6ec3 ddr: altera: Clean up rw_mgr_*_vfifo() part 2
Pluck out all this VFIFO value counting, which turns out to be
completely unused. Thus, remove it to simplify the code.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:19 +02:00
Marek Vasut
60bb8a8a7e ddr: altera: Clean up rw_mgr_*_vfifo() part 1
Perform minor cleanup, fix data types and constify where applicable.
Add kerneldoc.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:19 +02:00
Marek Vasut
4c5e584b2d ddr: altera: Clean up sdr_*_phase() part 10
Clean up data types, constify where applicable and document the
functions with kerneldoc.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:19 +02:00
Marek Vasut
49891df661 ddr: altera: Clean up sdr_*_phase() part 9
The "d" variable is set to 0 in sdr_backup_phase() and is not used
at all in sdr_nonworking_phase(). Make it local and zap it respectively.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:19 +02:00
Marek Vasut
a80f45346e ddr: altera: Clean up sdr_*_phase() part 8
The work_bgn parameter of sdr_nonworking_phase() is unused, zap it.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:19 +02:00
Marek Vasut
35ee867fc2 ddr: altera: Clean up sdr_*_phase() part 7
Wrap dtaps_per_ptap into the sdr_working_phase() function to trim
down the number of params. It's a constant too.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:19 +02:00
Marek Vasut
86a39dc76e ddr: altera: Clean up sdr_*_phase() part 6
It is now clear that the max_working_cnt variable is totally unused.
Zap the variable and zap other variables which became unused due to
this change too.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:19 +02:00
Marek Vasut
192d6f9fa3 ddr: altera: Clean up sdr_*_phase() part 5
Pull out the loop for eaching working/non-working DQS enable phase
into a separate function, as this is mostly common code between.
Clean up sdr_working_phase() and sdr_nonworking_phase() while switching
these two functions to the common sdr_find_phase().

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:19 +02:00
Marek Vasut
38ed692238 ddr: altera: Clean up sdr_*_phase() part 4
Get rid of found_{begin,end} variables. Instead of breaking out
through all of the loops, just return when the begin/end of the
window is found and be done with it. Also clean up the trailing
conditional expression, which is now much easier.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:18 +02:00
Marek Vasut
36edef3c98 ddr: altera: Clean up sdr_*_phase() part 3
Fix the arguments passed to these functions. The bit_chk is
overriden by rw_mgr_mem_calibrate_read_test_all_ranks() which
is invoked by all three sdr_*_phase() functions, so just make
this into local variable.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:18 +02:00
Marek Vasut
521fe39c5f ddr: altera: Clean up sdr_*_phase() part 2
Fix the arguments passed to these functions. The grp argument
does not have to be passed via reference, it's never modified
within either of those functions, so make it into a value.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:18 +02:00
Marek Vasut
0d304ce553 ddr: altera: Clean up sdr_*_phase() part 1
Rename find_working_phase() to sdr_working_phase() for the
sake of consistency.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:18 +02:00
Marek Vasut
0a13a0fb7a ddr: altera: Clean up sdr_find_window_centre() part 3
Reorder the end of the function a little by moving the conditional
debug output around a little. Rename the function from _centre() to
_center(). Document the function in kerneldoc.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:18 +02:00
Marek Vasut
cbb0b7e036 ddr: altera: Clean up sdr_find_window_centre() part 2
This function is a treasure trove of ad-hoc iterative
implementations of mathematical functions. Replace all
of those with their non-iterative counterpart.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:18 +02:00
Marek Vasut
28fd242a18 ddr: altera: Clean up sdr_find_window_centre() part 1
Clean up the arguments of this function. Most of the pointers
passed into the function are either not needed at all, or can
be passed as value instead of reference. Also fix the broken
multiline debug strings. No functional change.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:18 +02:00
Marek Vasut
28ea827d9c ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() part 4
This function is only invoked from rw_mgr_mem_calibrate_dqs_enable_calibration()
and at this point, it is just one level of indirection, so wrap the
rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() into
rw_mgr_mem_calibrate_dqs_enable_calibration() to get rid of the level
of indirection.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:18 +02:00
Marek Vasut
25fefe8bf8 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() part 3
Replace at least one of the loops in this function with call of a
standard function call instead of the ad-hoc implementation. The
other one cannot be replaced, since the delay is incremented for
each group.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:18 +02:00
Marek Vasut
9da1d8f5b4 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() part 2
The read_group and write_group params have the same value for all (one)
invocations of this function, just merge them into a single param.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:18 +02:00
Marek Vasut
9059009185 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay() part 1
Start cleaning up this function. In the first part, just fix
the incorrectly broken debug strings and fix return value to
respect the common convention.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:17 +02:00
Marek Vasut
d844c7d434 ddr: altera: Clean up rw_mgr_mem_calibrate_read_test_patterns()
Rework this function such that the code is more readable. Zap
unused parameter "num_tries" while at it. Also wrap parameter
"bit_chk" into this function as it's value is not used outside.
Finally, fix the return value from this function to match the
common expectation, where 0 means success.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:17 +02:00