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ddr: altera: sequencer: Wrap RW_MGR_* macros
Introduce structure socfpga_sdram_rw_mgr_config to wrap the RW manager configuration values in board file. Introduce a complementary function, socfpga_get_sdram_rwmgr_config(), which returns this the structure. This is another step toward wrapping the nasty QTS generated macros in board files and reducing the pollution of the namespace. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
This commit is contained in:
Marek Vasut
parent
04955cf247
commit
d718a26b0c
3 changed files with 140 additions and 0 deletions
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@ -16,6 +16,7 @@ const struct socfpga_sdram_config *socfpga_get_sdram_config(void);
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void socfpga_get_seq_ac_init(const u32 **init, unsigned int *nelem);
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void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem);
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const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void);
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#define SDR_CTRLGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x5000)
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@ -116,6 +117,69 @@ struct socfpga_sdram_config {
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u32 phy_ctrl0;
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};
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struct socfpga_sdram_rw_mgr_config {
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u8 activate_0_and_1;
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u8 activate_0_and_1_wait1;
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u8 activate_0_and_1_wait2;
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u8 activate_1;
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u8 clear_dqs_enable;
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u8 guaranteed_read;
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u8 guaranteed_read_cont;
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u8 guaranteed_write;
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u8 guaranteed_write_wait0;
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u8 guaranteed_write_wait1;
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u8 guaranteed_write_wait2;
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u8 guaranteed_write_wait3;
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u8 idle;
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u8 idle_loop1;
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u8 idle_loop2;
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u8 init_reset_0_cke_0;
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u8 init_reset_1_cke_0;
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u8 lfsr_wr_rd_bank_0;
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u8 lfsr_wr_rd_bank_0_data;
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u8 lfsr_wr_rd_bank_0_dqs;
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u8 lfsr_wr_rd_bank_0_nop;
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u8 lfsr_wr_rd_bank_0_wait;
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u8 lfsr_wr_rd_bank_0_wl_1;
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u8 lfsr_wr_rd_dm_bank_0;
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u8 lfsr_wr_rd_dm_bank_0_data;
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u8 lfsr_wr_rd_dm_bank_0_dqs;
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u8 lfsr_wr_rd_dm_bank_0_nop;
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u8 lfsr_wr_rd_dm_bank_0_wait;
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u8 lfsr_wr_rd_dm_bank_0_wl_1;
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u8 mrs0_dll_reset;
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u8 mrs0_dll_reset_mirr;
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u8 mrs0_user;
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u8 mrs0_user_mirr;
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u8 mrs1;
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u8 mrs1_mirr;
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u8 mrs2;
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u8 mrs2_mirr;
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u8 mrs3;
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u8 mrs3_mirr;
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u8 precharge_all;
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u8 read_b2b;
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u8 read_b2b_wait1;
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u8 read_b2b_wait2;
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u8 refresh_all;
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u8 rreturn;
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u8 sgle_read;
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u8 zqcl;
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u8 true_mem_data_mask_width;
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u8 mem_address_mirroring;
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u8 mem_data_mask_width;
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u8 mem_data_width;
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u8 mem_dq_per_read_dqs;
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u8 mem_dq_per_write_dqs;
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u8 mem_if_read_dqs_width;
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u8 mem_if_write_dqs_width;
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u8 mem_number_of_cs_per_dimm;
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u8 mem_number_of_ranks;
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u8 mem_virtual_groups_per_read_dqs;
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u8 mem_virtual_groups_per_write_dqs;
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};
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#define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23
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#define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000
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#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22
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@ -12,6 +12,8 @@
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#include "qts/sequencer_auto_ac_init.h"
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#include "qts/sequencer_auto_inst_init.h"
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#include "qts/sequencer_auto.h"
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#include "qts/sequencer_defines.h"
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static const struct socfpga_sdram_config sdram_config = {
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.ctrl_cfg =
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@ -182,6 +184,71 @@ static const struct socfpga_sdram_config sdram_config = {
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.phy_ctrl0 = CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0,
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};
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static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = {
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.activate_0_and_1 = RW_MGR_ACTIVATE_0_AND_1,
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.activate_0_and_1_wait1 = RW_MGR_ACTIVATE_0_AND_1_WAIT1,
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.activate_0_and_1_wait2 = RW_MGR_ACTIVATE_0_AND_1_WAIT2,
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.activate_1 = RW_MGR_ACTIVATE_1,
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.clear_dqs_enable = RW_MGR_CLEAR_DQS_ENABLE,
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.guaranteed_read = RW_MGR_GUARANTEED_READ,
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.guaranteed_read_cont = RW_MGR_GUARANTEED_READ_CONT,
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.guaranteed_write = RW_MGR_GUARANTEED_WRITE,
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.guaranteed_write_wait0 = RW_MGR_GUARANTEED_WRITE_WAIT0,
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.guaranteed_write_wait1 = RW_MGR_GUARANTEED_WRITE_WAIT1,
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.guaranteed_write_wait2 = RW_MGR_GUARANTEED_WRITE_WAIT2,
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.guaranteed_write_wait3 = RW_MGR_GUARANTEED_WRITE_WAIT3,
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.idle = RW_MGR_IDLE,
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.idle_loop1 = RW_MGR_IDLE_LOOP1,
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.idle_loop2 = RW_MGR_IDLE_LOOP2,
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.init_reset_0_cke_0 = RW_MGR_INIT_RESET_0_CKE_0,
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.init_reset_1_cke_0 = RW_MGR_INIT_RESET_1_CKE_0,
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.lfsr_wr_rd_bank_0 = RW_MGR_LFSR_WR_RD_BANK_0,
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.lfsr_wr_rd_bank_0_data = RW_MGR_LFSR_WR_RD_BANK_0_DATA,
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.lfsr_wr_rd_bank_0_dqs = RW_MGR_LFSR_WR_RD_BANK_0_DQS,
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.lfsr_wr_rd_bank_0_nop = RW_MGR_LFSR_WR_RD_BANK_0_NOP,
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.lfsr_wr_rd_bank_0_wait = RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
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.lfsr_wr_rd_bank_0_wl_1 = RW_MGR_LFSR_WR_RD_BANK_0_WL_1,
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.lfsr_wr_rd_dm_bank_0 = RW_MGR_LFSR_WR_RD_DM_BANK_0,
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.lfsr_wr_rd_dm_bank_0_data = RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
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.lfsr_wr_rd_dm_bank_0_dqs = RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
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.lfsr_wr_rd_dm_bank_0_nop = RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
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.lfsr_wr_rd_dm_bank_0_wait = RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
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.lfsr_wr_rd_dm_bank_0_wl_1 = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1,
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.mrs0_dll_reset = RW_MGR_MRS0_DLL_RESET,
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.mrs0_dll_reset_mirr = RW_MGR_MRS0_DLL_RESET_MIRR,
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.mrs0_user = RW_MGR_MRS0_USER,
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.mrs0_user_mirr = RW_MGR_MRS0_USER_MIRR,
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.mrs1 = RW_MGR_MRS1,
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.mrs1_mirr = RW_MGR_MRS1_MIRR,
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.mrs2 = RW_MGR_MRS2,
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.mrs2_mirr = RW_MGR_MRS2_MIRR,
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.mrs3 = RW_MGR_MRS3,
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.mrs3_mirr = RW_MGR_MRS3_MIRR,
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.precharge_all = RW_MGR_PRECHARGE_ALL,
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.read_b2b = RW_MGR_READ_B2B,
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.read_b2b_wait1 = RW_MGR_READ_B2B_WAIT1,
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.read_b2b_wait2 = RW_MGR_READ_B2B_WAIT2,
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.refresh_all = RW_MGR_REFRESH_ALL,
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.rreturn = RW_MGR_RETURN,
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.sgle_read = RW_MGR_SGLE_READ,
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.zqcl = RW_MGR_ZQCL,
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.true_mem_data_mask_width = RW_MGR_TRUE_MEM_DATA_MASK_WIDTH,
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.mem_address_mirroring = RW_MGR_MEM_ADDRESS_MIRRORING,
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.mem_data_mask_width = RW_MGR_MEM_DATA_MASK_WIDTH,
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.mem_data_width = RW_MGR_MEM_DATA_WIDTH,
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.mem_dq_per_read_dqs = RW_MGR_MEM_DQ_PER_READ_DQS,
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.mem_dq_per_write_dqs = RW_MGR_MEM_DQ_PER_WRITE_DQS,
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.mem_if_read_dqs_width = RW_MGR_MEM_IF_READ_DQS_WIDTH,
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.mem_if_write_dqs_width = RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
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.mem_number_of_cs_per_dimm = RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
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.mem_number_of_ranks = RW_MGR_MEM_NUMBER_OF_RANKS,
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.mem_virtual_groups_per_read_dqs =
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RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
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.mem_virtual_groups_per_write_dqs =
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RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS,
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};
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const struct socfpga_sdram_config *socfpga_get_sdram_config(void)
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{
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return &sdram_config;
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@ -198,3 +265,8 @@ void socfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem)
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*init = inst_rom_init;
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*nelem = ARRAY_SIZE(inst_rom_init);
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}
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const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config(void)
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{
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return &rw_mgr_config;
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}
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@ -41,6 +41,8 @@ static struct socfpga_data_mgr *data_mgr =
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static struct socfpga_sdr_ctrl *sdr_ctrl =
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(struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
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const struct socfpga_sdram_rw_mgr_config *rwcfg;
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#define DELTA_D 1
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/*
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@ -3696,6 +3698,8 @@ int sdram_calibration_full(void)
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param = &my_param;
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gbl = &my_gbl;
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rwcfg = socfpga_get_sdram_rwmgr_config();
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/* Set the calibration enabled by default */
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gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;
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/*
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