u-boot/drivers/ddr
Marek Vasut 78cdd7d0c8 ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_end()
This function is implementing the DDR calibration Stage 3 as
described in Altera EMI_RM 2015.05.04 . The main body of this
function is almost identical to Stage 1.3 (DQ/DQS centering)
for all but two flags -- use_read_test and update_fom. Convert
this function to call rw_mgr_mem_calibrate_dq_dqs_centering()
with the correct flags set to trim down the code duplication.

Moreover, reorder the remnants in the function a little and
convert the function to return either 0 or -EIO in case of
success and failure respectively, to match the common return
value convention.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:23 +02:00
..
altera ddr: altera: Clean up rw_mgr_mem_calibrate_vfifo_end() 2015-08-08 14:14:23 +02:00
fsl drivers/ddr/fsl: Adjust bstopre value 2015-08-03 12:06:38 -07:00
marvell arm: mvebu: a38x: Use correct PEX register access macros 2015-07-23 10:39:25 +02:00