u-boot/drivers/ddr
Marek Vasut 60bd0df018 ddr: altera: sdram: Clean up set_sdr_dram_timing*()
Get rid of the constant clrsetbits_le32(), instead prepare the whole
content of the register once and write it at the end of the function.
Merge set_sdr_dram_timing{1,2,3,4,lowpwr}() into single function
set_sdr_dram_timing() , since there's no point in keeping all this
stuff separate anymore.

Signed-off-by: Marek Vasut <marex@denx.de>
2015-08-08 14:14:26 +02:00
..
altera ddr: altera: sdram: Clean up set_sdr_dram_timing*() 2015-08-08 14:14:26 +02:00
fsl drivers/ddr/fsl: Adjust bstopre value 2015-08-03 12:06:38 -07:00
marvell arm: mvebu: a38x: Use correct PEX register access macros 2015-07-23 10:39:25 +02:00