Commit graph

130 commits

Author SHA1 Message Date
Jagan Teki
bb3362b0ca arm: sunxi: Enable DM_MMC and DM_SCSI
- Enable DM_MMC if MMC defined
- Enable DM_SCSI if SCSI defined

globally through Allwinner platform, the effected SoC families
and boards will make use of MMC and SCSI subsystems in driver-model.

Tested DM_MMC in one board from A64, H6, H5, H3, R40, A83T, A20, A10
SoCs.

Tested-by: Pablo Sebastián Greco <pgreco@centosproject.org> # BPI-M2-Ultra
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-17 14:34:45 +05:30
Andre Przywara
067e0b9684 sunxi: Allow booting from 128KB SD/eMMC offset
On modern Allwinner SoCs (tested: H2+, A64, H5, H6) the BootROM can
actually load the SPL also from sector 256 (128KB) of an SD card or eMMC
chip. For more details, see [1].
In this case the boot source indicator (written at offset 0x28 of SRAM A1)
has bit 4 set, so it's 0x10 for SD card and 0x12 for eMMC.

Add those new values to the existing boot source check to allow booting
the SPL from those "high" disk offsets as well. For this to work, the
value of CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR needs to be adjusted,
for instance to 0x140 (right after the high SPL). Doing this dynamically
sounds desirable, but looks nasty to implement.

[1] https://groups.google.com/forum/#!topic/linux-sunxi/MaiijyaAFjk

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-04-10 15:34:32 +05:30
Paul Kocialkowski
9d0f9e8374 arm: sunxi: Enable DRAM ODT by default on H3/H5
Most of the boards we support with H3/H5 enable DRAM on-die termination,
which is consistent with the high DRAM clocks that are used.

Make it the default (like it's done for other similar platforms) instead
of defining it in each defconfig.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-04-10 15:34:32 +05:30
Paul Kocialkowski
882b71e47d arm: sunxi: Set the default DRAM ZQ value to 3881979 on H3/H5
Most H3/H5 boards we support have the DRAM ZQ value set to 3881979,
which is also consistent with the default set for the R40.

Make this value the default on H3/H5 instead of 123.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-04-10 15:34:32 +05:30
Paul Kocialkowski
9c2b0ddc41 arm: sunxi: Allow per-platform DRAM ZQ configuration on sun8i
A few sun8i platforms define specific default DRAM ZQ values, but they
are not taken in account because of MACH_SUN8I being used for the 123
default first.

Replace MACH_SUN8I with the list of platforms that don't have specific
DRAM ZQ values, to avoid overwriting the default for those that do.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2019-04-10 15:34:32 +05:30
Michael Trimarchi
ddd6930215 sunxi: dram_sun8i: Fix A33 memory initialization
While the exact problem is not known, based on discussion between
Philipp Tomsich and André Przywara it is guessed that exit self-refresh
timing is not set with correct value. There may be implicit enter or
exit Self-Refresh anywhere as part of some training phase.

In ZynqMP register guide [1], which is close to the various
Allwinner DRAM controllers, tXSDLL is bits [14:8], while the non-DLL
tXS is bits [6:0]: Self refresh exit delay. So it could be safely
increased and it only affects the time after the self-refresh “exit”,
which happens only after (re-)initialisation.

There was no document for cpu in question so based on oscilloscope
readings [2][3] and observed result by comparing allwinner architecture.
So set it same as  Allwinner H5 silicon.

Before this patch, failure rate of was 7%.

This was tested on A33 allwinner cpu, dual rank connection connected
with two MT41K512M16HA-125:A memory model. Memory is configured as DDR3
1.5V

And also this is tested in A33-OLinuXino dev board.

[1] https://www.xilinx.com/html_docs/registers/ug1087/ddrc___dramtmg8.html
[2] https://ibb.co/R70zmyS
[3] https://ibb.co/HVVCGQ8

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Shyam Saini <shyam.saini@amarulasolutions.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2019-04-10 15:32:59 +05:30
Jagan Teki
85c3d46322 arm: sunxi: Enable DM_MMC on required SoCs
Enabling DM_MMC is forcing CONFIG_BLK=y so if any board which uses
SCSI must need to enable DM_SCSI otherwise SCSI reads on that particular
target making invalid reading to the disk drive.

Allwinner platform do support SCSI on A10, A20 and R40 SoC's out of
these only A10 have DM_SCSI enabled. So enabling DM_MMC on A20, R40
would eventually end-up with scsi disk read failures like [1]

So, enable DM_MMC in all places of respective SoC's instead of enabling
them globally to Allwinner platform.

Now, DM_MMC is enabled in Allwinner SoC's except A20 and R40.

[1] https://lists.denx.de/pipermail/u-boot/2019-April/364057.html

Reported-by: Pablo Sebastián Greco <pgreco@centosproject.org>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2019-04-08 16:35:15 -04:00
Jagan Teki
a7cca57937 arm: sunxi: Enable DM_MMC
Enable DM_MMC for all Allwinner SoCs, this will eventually
enable BLK.

Also removed DM_MMC enablement in few parts of sunxi
configurations.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2019-01-30 18:22:18 +05:30
Olliver Schinagl
c970e8954f sunxi: pmic_bus: Decrease boot time by not writing duplicate data
When we clear a pmic_bus bit, we do a read-modify-write operation.
We waste some time however, by writing back the exact samea value
that was already set in the chip. Let us thus only do the write
in case data was changed.

Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
Signed-off-by: Priit Laes <plaes@plaes.org>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-12-07 22:24:33 +05:30
Michael Trimarchi
aa09a071c3 sunxi: Fix memory 2-rank initialization for a33 cpu
When we initialize the memory we need to autodetect rank and size
but this can happen only if we send the proper reset to both
memory module including cke signal.
For this reason we need initialize the physical on both channel because
we need to presume that both are connected. This way let the CLKE to be
activated at the right time with the memory reset coming from the cpu

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-11-22 13:24:15 +05:30
Vasily Khoruzhick
0e21a2ffb3 sunxi-mmc: use new mode on both controllers on A64
Using new mode improves stability of eMMC and SD cards. Without
it SPL fails to load u-boot from SD on Pinebook.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # Amarula A64-Relic
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-11-22 13:20:16 +05:30
Vasily Khoruzhick
2a8882ecef sunxi-mmc: introduce new MMC_SUNXI_HAS_MODE_SWITCH option
Allwinner A64 has new mode but doesn't have a mode switch in CCM,
and CCM_MMC_CTRL_MODE_SEL_NEW is not defined, so compilation fails
if MMC_SUNXI_HAS_NEW_MODE is enabled

Introduce new MMC_SUNXI_HAS_MODE_SWITCH option to be able to ifdef usage
of CCM_MMC_CTRL_MODE_SEL_NEW

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
[jagan: update commit message]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # Amarula A64-Relic
2018-11-22 13:19:19 +05:30
Icenowy Zheng
7d121a8ea4 sunxi: use 6MHz PLL_VIDEO step for DE2 for higher resolution LCD
DE2 SoCs can support LCDs up to 1080p (e.g. A64), and 3MHz step won't
let PLL_VIDEO be high enough for them.

Use 6MHz step for PLL_VIDEO when using DE2, to satisfy 1080p LCD.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Vasily Khoruzhick <anarsoul@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
2018-11-13 22:17:06 +05:30
Vasily Khoruzhick
31a4ac4d79 sun50i: A64: add support for R_I2C controller
Allwinner A64 has a I2C controller, which is in the R_ MMIO zone and has
two groups of pinmuxes on PL bank, so it's called R_I2C.

Add support for this I2C controller and the pinmux which doesn't conflict
with RSB.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Tested-by: Maxime Ripard <maxime.ripard@bootlin.com>
Cc: Vagrant Cascadian <vagrant@debian.org>
Acked-by: Jagan Teki <jagan@openedev.com>
2018-11-13 22:09:10 +05:30
Icenowy Zheng
f8aa3f8d84 sunxi: add Kconfig option for the maximum accessible DRAM
Allwinner 64-bit SoCs can use 4GiB DRAM chip, however their memory map
has only allocated 3GiB for DRAM, so only 3GiB of the DRAM is
accessible.

Add a Kconfig option for the maximum accessible DRAM.

For A80 it should be a much higher value (8GiB), but as I have no A80
device to test and originally U-Boot only supports 2GiB DRAM on A80, it
currently still falls under the 2GiB situation.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-10-29 20:41:15 +05:30
Icenowy Zheng
7009134c99 sunxi: map DRAM part with 3G size
All Allwinner 64-bit SoCs now are known to be able to access 3GiB of
external DRAM, however the size of DRAM part in the MMU translation
table is still 2GiB.

Change the size of DRAM part in MMU table to 3GiB.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-10-29 20:41:15 +05:30
Icenowy Zheng
c6c2c85e4b sunxi: disable Pine A64 model detection code on other boards
The Pine A64 Plus/non-Plus model detection code is now built on all
64-bit ARM SoCs, even if the code cannot be triggered when H5/H6 is in
use.

Disable them when the board is Pine A64 by adding a Kconfig option that
is only selected on Pine A64.

On GCC 7.3.1 this makes the size of the function reduces 184 bytes, and
saves a 104 byte strstr() function, then makes SPL on H6 succeed to
build.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-10-29 20:41:07 +05:30
Priit Laes
297963f5b5 sunxi: Fix typos of spelling Allwinner
Signed-off-by: Priit Laes <plaes@plaes.org>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-10-24 22:02:15 +05:30
Icenowy Zheng
90de3969be sunxi: fix DRAM gate/reset sequence of H6
Currently the DRAM bus gate and reset is changed at the same time in
H6 DRAM initialization code, which disobeys the user manual's
programming guide.

Fix the sequence by follow the sequence suggested by the user manual
(ungate the bus clock after release the reset signal).

By some experiments it seems to fix the DRAM size detection failure that
rarely happens.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2018-10-10 12:04:07 +05:30
Andre Przywara
8094f0cb0c sunxi: A64: fix default DRAM_ODT_EN symbol
"default" lines in Kconfig are processed in order, the first hit will
stop considering subsequent lines. In the case of the DRAM_ODT_EN symbol
that means that everything following the first two lines will never be
checked:
------------
config DRAM_ODT_EN
	bool "sunxi dram odt enable"
	default n if !MACH_SUN8I_A23
	default y if MACH_SUN8I_A23
	default y if MACH_SUN8I_R40
	default y if MACH_SUN50I
------------

Assuming that the "default y" for the A64 and the R40 were a deliberate
choice, fix the Kconfig stanza to take this into account.
Also remove the now redundant lines from the respective defconfigs.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[jagan: droped 'default n' on original change]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # A64, R40
Tested-by: Chen-Yu Tsai <wens@csie.org> # A23
2018-08-13 16:47:38 +05:30
Icenowy Zheng
6f796a9bb4 sunxi: add support for Allwinner H6 SoC
Allwinner H6 is a new SoC from Allwinner features USB3 and PCIe
interfaces.

This patch adds support for it.

The corresponding DTSI file, from Linux next-20180720, is also
introduced.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:38:13 +05:30
Icenowy Zheng
da2616543a sunxi: add DRAM support to H6
The Allwinner H6 SoC comes with a set of new DRAM controller+PHY combo.
Both the controller and the PHY seem to be originate from DesignWare,
and are similar to the ones in ZynqMP SoCs.

This commit introduces an initial DRAM driver for H6, which contains
only LPDDR3 support. The currently known SBCs with H6 all come with
LPDDR3 memory, including Pine H64 and several Orange Pi's.

The BSP DRAM initialization code is closed source and violates GPL. Code
in this commit is written by experimenting, referring the code/document
of other users of the IPs (mainly the ZynqMP, as it's the only found PHY
reference) and disassebling the BSP blob.

Thanks for Jernej Skrabec for review and fix some issues in this driver
(including the most critical one which made it to work), and rewrite
some code from register dump!

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:38:13 +05:30
Icenowy Zheng
7f51a4020e sunxi: add UART0 setup for H6
The UART0 on H6 is available at PH bank (and PF bank, but the PF one is
muxed with SD card).

Add pinmux configuration.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:38:13 +05:30
Icenowy Zheng
10196c9627 sunxi: use sun6i-style watchdog for H6
The H6 SoC has a sun6i-style watchdog in its timer part.

Enable the usage of it.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:38:13 +05:30
Icenowy Zheng
0558676d4b sunxi: add clock code for H6
The new Allwinner H6 SoC has a brand new CCU layout.

Add clock code for it.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:38:13 +05:30
Icenowy Zheng
80197801f4 sunxi: change RMR64's RVBAR address for H6
Allwinner H6 has a different RVBAR address with A64/H5.

Add conditional RVBAR configuration into the code which does RMR switch.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:38:13 +05:30
Icenowy Zheng
cadc7c20e5 sunxi: change SUNXI_HIGH_SRAM option to SUNXI_SRAM_ADDRESS
The new Allwinner H6 SoC has its SRAM A1 at neither 0x0 nor 0x10000, but
it's at 0x20000. Thus the SUNXI_HIGH_SRAM option needs to be refactored
to support this new configuration.

Change it to SUNXI_SRAM_ADDRESS, which holds the real address of SRAM
A1 in the memory map.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2018-07-31 11:38:13 +05:30
Adam Sampson
df63fcc06f dm: sunxi: Use DM for MMC and SATA on all A10 boards
Use the driver model for MMC and SATA, in preparation for CONFIG_BLK
defaulting to y.

Tested on A10 Cubieboard.

Signed-off-by: Adam Sampson <ats@offog.org>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
2018-07-16 12:26:00 +05:30
Tom Rini
4ac5df4b41 Merge branch 'master' of git://git.denx.de/u-boot-sunxi 2018-07-03 23:09:34 -04:00
Andre Przywara
be0d217952 arm: timer: sunxi: add Allwinner timer erratum workaround
The Allwinner A64 SoCs suffers from an arch timer implementation erratum,
where sometimes the lower 11 bits of the counter value erroneously
become all 0's or all 1's [1]. This leads to sudden jumps, both forwards and
backwards, with the latter one often showing weird behaviour.
Port the workaround proposed for Linux to U-Boot and activate it for all
A64 boards.
This fixes crashes when accessing MMC devices (SD cards), caused by a
recent change to actually use the counter value for timeout checks.

Fixes: 5ff8e54888 ("sunxi: improve throughput
in the sunxi_mmc driver")

[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2018-May/576886.html

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Andreas Färber <afaerber@suse.de>
Tested-by: Guillaume Gardet <guillaume.gardet@free.fr>
2018-07-03 22:00:00 +05:30
Chris Packham
9508ecfbcb ARM: sunxi: remove empty #ifdef/endif block
Whatever code this was guarding has been removed so remove the guards
too.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
2018-06-18 14:02:03 -04:00
Jagan Teki
f5871a66fd sunxi: Drop legacy usb_phy.c
Allwinner PHY USB code is now part of generic-phy framework,
so drop existing legacy handling like arch/arm/mach-sunxi.c
and related code areas.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Jun Nie <jun.nie@linaro.org>
2018-05-28 16:40:43 +05:30
Jagan Teki
dd3228170a usb: sunxi: Switch to use generic-phy
Allwinner USB PHY handling can be done through driver-model
generic-phy so add the generic-phy ops to relevant places
on host and musb sunxi driver and enable them in respective
SOC's.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Jun Nie <jun.nie@linaro.org>
2018-05-28 16:40:43 +05:30
Lokesh Vutla
acf1500138 arm: v7: Kconfig: Rename CPU_V7 as CPU_V7A
Currently CPU_V7 kconfig symbol supports only ARMv7A architectures under
armv7 folder. This led to a misconception of creating separate folders
for armv7m and armv7r. There is no reason to create separate folder for
other armv7 based architectures when it can co-exist with few Kconfig
symbols.

As a first step towards a common folder, rename CPU_V7 as CPUV7A. Later
separate Kconfig symbols can be added for CPU_V7R and CPU_V7M and
can co exist in the same folder.

Reviewed-by: Tom Rini <trini@konsulko.com>
Tested-by: Michal Simek <michal.simek@xilinx.com>
Suggested-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2018-05-07 15:53:24 -04:00
Tom Rini
83d290c56f SPDX: Convert all of our single license tags to Linux Kernel style
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from.  So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry.  Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents.  There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-07 09:34:12 -04:00
Tom Rini
d024236e5a Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTR
We have a large number of places where while we historically referenced
gd in the code we no longer do, as well as cases where the code added
that line "just in case" during development and never dropped it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-04-27 14:54:48 -04:00
Jagan Teki
0354f4bef0 sunxi: Add DRAM_SUN8I_A83T kconfig entry
Add proper and simple kconfig option for dram_sun8i_a83t.c
instead of using MACH type on Makefile.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-03-19 16:46:47 +05:30
Jagan Teki
c335e9903c sunxi: Add DRAM_SUN8I_A33 kconfig entry
Add proper and simple kconfig option for dram_sun8i_a33.c
instead of using MACH type on Makefile.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-03-19 16:46:44 +05:30
Jagan Teki
af30393cb5 sunxi: Add DRAM_SUN8I_A23 kconfig entry
Add proper and simple kconfig option for dram_sun8i_a23.c
instead of using MACH type on Makefile.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-03-19 16:46:41 +05:30
Jagan Teki
7d0b165d5e sunxi: Add DRAM_SUN9I kconfig entry
Add proper and simple kconfig option for dram_sun9i.c
instead of using MACH type on Makefile.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-03-19 16:46:37 +05:30
Jagan Teki
dd928bfbb6 sunxi: Add DRAM_SUN4I kconfig entry
Add proper and simple kconfig option for dram_sun4i.c
instead of using MACH type on Makefile.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-03-19 16:46:14 +05:30
Jagan Teki
fdfa934e6e sunxi: add DRAM_SUN6I kconfig
Add proper and simple kconfig option for dram_sun6i.c
instead of using MACH type on Makefile.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-03-19 15:37:20 +05:30
Jagan Teki
735fb25202 sunxi: Add AXP_PMIC_BUS kconfig entry
Add simple and meaningful kconfig option for pmic_bus.c
instead of using MACH type on Makefile.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-03-19 15:37:20 +05:30
Jagan Teki
6f6f883949 sunxi: Add SUN8I_RSB kconfig entry
Add simple and meaningful kconfig option for rsb.c
instead of using MACH type on Makefile.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-03-19 15:37:20 +05:30
Jagan Teki
63928fa6dd sunxi: Use SUN6I_PRCM if used
SUN6I_PRCM is also used for SUN8I and SUN9I, so
select the same on respective MACH types.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-03-19 15:37:20 +05:30
Jagan Teki
71d9edf47a sunxi: Add SUN6I_P2WI kconfig entry
Add simple and meaningful kconfig option for p2wi.c
instead of using MACH type on Makefile.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-03-19 15:37:20 +05:30
Jagan Teki
2aa697a494 sunxi: Add SUN6I_PRCM kconfig entry
Add simple and meaningful kconfig option for prcm.c
instead of using MACH type on Makefile.

PRCM (Power/Reset/Clock Management) is considered as a
Multi-Functional Device, so used the same on Kconfig definition.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
2018-03-19 15:37:20 +05:30
Tom Rini
6f6b7cfa89 Convert all of CONFIG_CONS_INDEX to Kconfig
This converts the following to Kconfig:
   CONFIG_CONS_INDEX

We have existing entries for this option in a number of places, with
different guards on them.  They're also sometimes used for things not
directly inside of the serial driver.  First, introduce a new symbol to
guard the use of CONFIG_CONS_INDEX, so that in the case where we don't
need this for the serial driver, but for some other use, we can still do
it.  Next, consolidate all of these into the single entry in
drivers/serial/Kconfig.  Finally, introduce CONS_INDEX_[023456] so that
we can imply a correct value here to make the defconfig side of this
smaller.

Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Rework a lot of the logic here, such that I took authorship from
Adam, but kept his S-o-B line]
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-03-16 10:28:52 -04:00
Jagan Teki
c2a7a7ef86 arm: sunxi: Move spl spi sunxi code to mach-sunxi
This SUNXI variant SPL SPI code doesn't use either SPI or
SPL_FLASG subsystems due to size constraints and also placing
this code in drivers/mtd/spi will unnecessary build SPI_FLASH
code(if defined) which never required, hence moved to arch area.

And also renamed the file according to kconfig which resembles
proper name.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-03-13 19:50:10 +05:30
Lukasz Majewski
d695d66278 spl: eMMC/SD: Provide one __weak spl_boot_mode() function
The goal of this patch is to clean up the code related to choosing SPL
MMC boot mode.

The spl_boot_mode() now is called only in spl_mmc_load_image() function,
which is only compiled in if CONFIG_SPL_MMC_SUPPORT is enabled.

To achieve the goal, all per mach/arch implementations eligible for
unification has been replaced with one __weak implementation.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Acked-by: Michal Simek <michal.simek@xilinx.com> (For ZynqMP)
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-02-07 22:06:18 -05:00