Use fixed regulator to control the voltage of vbus. Enable vbus
supply when usb start and disable vbus supply when usb stop.
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
The xhci-rockchip driver depends on DM_REGULATOR and DM_USB.
So add dependent features for xhci-rockchip driver in Kconfig.
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Rockchip using the same bit definition for dram info and write
to os_reg, the col and bw info is not correct and let's fix it.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
rk3036 sdram driver does not use DM, remove CONFIG_RAM first.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Some address relevant varibable is defined originally as u64. To
compatible with arm32, this patch change them to uintptr_t type.
Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
According to rk3288 spec, the pwm register order is:
PWM_PWM0_CNT,
PWM_PWM0_PERIOD_HPR,
PWM_PWM0_DUTY_LPR,
PWM_PWM0_CTRL
but the source code's order is:
struct rk3288_pwm {
u32 cnt;
u32 duty_lpr;
u32 period_hpr;
u32 ctrl;
};
So, correct it here. It is the same as RK3399.
Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Edited the commit message:
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
The origin patch get rockchip dwmmc by name 'ciu', which lead
to the SPL not able to remove 'clock-names' node in dts.
I'm not saying this is not correct, but I would prefer to handle
this in dts or clock driver to save memory for SPL.
For example the rk3288 SPL size has out of memory if not enable
BACK_TO_BROM option, there are many other SoCs has less internal
memory than rk3288.
This reverts commit 480a9b834c.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Enable mmc_dw_rockchip driver, disable CONFIG_SPL_OF_PLATDATA
first for some dependence patches still not merged.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Vagrant Cascadian <vagrant@debian.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Enable sdmmc device and add the spl boot device sequence.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Since the 'clock-freq-min-max' is deprecated, we use max-frequency for
all rockchip SoC dwmmc controller.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Since the 'clock-freq-min-max' is deprecated, we use max-frequency.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Since the 'clock-freq-min-max' is deprecated, we use max-frequency.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Since the 'clock-freq-min-max' is deprecated, we use max-frequency.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Rockchip rk322x sysreset is much like rk3036 and other Rockchip SoCs,
only difference is that the target register address is different.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Enable soc support for SPL and U-boot skeleton.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
The dts files are from kernel and with modify to adapt U-Boot.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Add support for rk322x package header in mkimage tool.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
The rv1108 do not have DRAM driver now, so disable it first,
or else it will get conflict with the sdram common code.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
The bank0 ram size should be the DRAM size minus reserved size,
the DRAM size may be 1GB, 2GB, 4GB, we can not hard code it.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Added DECLARE_GLOBAL_DATA_PTR for RK3328, RK3368 and RK3399:
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Add dmc node to enable sdram driver.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Add a dmc node for sdram driver.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Add sdram driver in U-Boot for get the correct sdram size from
sys_reg, so that U-Boot can co-work with Rockchip loader or SPL
to get different dram capability and then tell the kernel.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Add sdram driver in U-Boot for get the correct sdram size from
sys_reg, so that U-Boot can co-work with Rockchip loader or SPL
to get different dram capability and then tell the kernel.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Replace the sdram_init() in board init and rockchip_sdram_size() in
sdram driver for all the Rockchip SoCs which enable CONFIG_RAM.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Make dram_init() in rk3036-board.c conditional on CONFIG_RAM:
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
There are some functions like sdram_size_mb can be re-used for
different rockchip SoCs, just put them into common file.
Add board_get_usable_ram_top() for ram_top init base on
SDRAM_MAX_SIZE.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Added SDRAM_MAX_SIZE definition for RK3036:
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
fixup: 3036 fix for sdram_common
According to rk3328 TRM:
0~0xff000000 is ddr space;
0xff000000~0xffffffff is device space.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
With the new dev_read functions available, we can convert the rockchip
architecture-specific drivers and common drivers used by these devices
over to the dev_read family of calls.
This covers the DRAM controller initialisation for the RK3188, RK3288
and RK3399... all of these read some of the tuning/setup/timing
parameters from the device-tree.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
With the new dev_read functions available, we can convert the rockchip
architecture-specific drivers and common drivers used by these devices
over to the dev_read family of calls.
This covers the serial driver (ns16550 and compatible) used for the
Rockchip devices.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
With the new dev_read functions available, we can convert the rockchip
architecture-specific drivers and common drivers used by these devices
over to the dev_read family of calls.
This covers the Gigabit Ethernet MAC (i.e. common designware driver and
rockchip-specific wrapper).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
With the new dev_read functions available, we can convert the rockchip
architecture-specific drivers and common drivers used by these devices
over to the dev_read family of calls.
This covers the dw_mmc and sdhci wrapper drivers for Rockchip.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
With the new dev_read functions available, we can convert the rockchip
architecture-specific drivers and common drivers used by these devices
over to the dev_read family of calls.
This change covers the USB3 (xhci) driver for the Rockchip devices.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
With the new dev_read functions available, we can convert the rockchip
architecture-specific drivers and common drivers used by these devices
over to the dev_read family of calls.
This change covers the rk_spi.c (SPI driver) used in Rockchip devices.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
With the new dev_read functions available, we can convert the rockchip
architecture-specific drivers and common drivers used by these devices
over to the dev_read family of calls.
This change covers the pinctrl drivers for the Rockchip devices.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
If the value of either "nand options" or "bbt options" has a zero in
the most significant nibble, the '0x' prefix will be isolated from the
value like shown below:
|Device 0: nand0, sector size 128 KiB
| Page size 2048 b
| OOB size 64 b
| Erase size 131072 b
| subpagesize 2048 b
| options 0x40000200
| bbt options 0x 60000
Change the format string to produce leading zeroes filling the gap.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
This error code has not been upstreamed and is not really needed since it
is unlikely to be triggered. Drop it to maintain compatability with
upstream.
Reported-by: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
It's been a while since I've touched U-Boot on the Raspberry Pi and
other things have been taking my time. Drop my maintainership for this
port.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
CS Systemes d'Information (CSSI) manufactures two boards, named MCR3000
and CMPC885 which are respectively based on MPC866 and MPC885 processors.
This patch adds support for the first board.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
For processors whose core runs at twice the bus frequency,
the fallback frequency calculation in Linux provides a wrong
result. Therefore, U-boot needs to pass the correct value.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Reviewed-by: Heiko Schocher <hs@denx.de>
