Commit graph

66 commits

Author SHA1 Message Date
Bin Meng
5bc60d5a44 x86: coreboot: Convert to use more dm drivers
Move to driver model for RTC, USB and ETH on coreboot.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-09-09 07:48:03 -06:00
Bin Meng
a25bc78e2f x86: coreboot: Allow >=4GiB memory bank size
Some platforms may have >=4GiB memory, so we need make U-Boot report
such configuration correctly when booting as the coreboot payload.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-26 07:54:07 -07:00
Bin Meng
c17ca6b5cd x86: Remove calculate_relocation_address()
Now that we have generic routine to calculate relocation address,
remove the x86 specific one which is now only used by coreboot.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-26 07:54:07 -07:00
Bin Meng
52b778603b x86: coreboot: Correctly report E820 types
coreboot has some extensions (type 6 & 16) to the E820 types.
When we detect this, mark it as E820_RESERVED.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2015-08-26 07:54:07 -07:00
Simon Glass
945cae79e1 x86: pci: Tidy up the generic x86 PCI driver
This driver should use the x86 PCI configuration functions. Also adjust its
compatible string to something generic (i.e. without a vendor name).

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-07-14 18:03:19 -06:00
Bin Meng
5c564226fc x86: qemu: Implement PIRQ routing
Support QEMU PIRQ routing via device tree on both i440fx and q35
platforms. With this commit, Linux booting on QEMU from U-Boot
has working ATA/SATA, USB and ethernet.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 03:03:18 -06:00
Bin Meng
f2653e8dd9 x86: coreboot: Control I/O port 0xb2 writing via device tree
Writing 0xcb to I/O port 0xb2 (Advanced Power Management Control) causes
U-Boot to hang on QEMU q35 target. We introduce a config option in the
device tree "u-boot,no-apm-finalize" under /config node if we don't want
to do that.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 03:03:18 -06:00
Bin Meng
65cdd9be3e x86: coreboot: Fix cosmetic issues
Clean up arch/x86/cpu/coreboot.c to fix several cosmetic issues.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 03:03:17 -06:00
Simon Glass
87f4cd3a30 x86: link: Add PCH driver to support SPI Flash
U-Boot on coreboot does not have a driver for the PCH so cannot see the
SPI peripheral now that it has moved inside the PCH. Add a simple driver so
that SPI flash works again.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-29 18:51:50 -06:00
Simon Glass
801f4f1bbc dm: x86: pci: Convert coreboot to use driver model for pci
Move coreboot-x86 over to driver model for PCI.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-04-18 11:11:09 -06:00
Simon Glass
892ff8e972 x86: Support machines with >4GB of RAM
Some systems have more than 4GB of RAM. U-Boot can only place things below
4GB so any memory above that should not be used. Ignore any such memory so
that the memory size will not exceed the maximum.

This prevents gd->ram_size exceeding 4GB which causes problems for PCI
devices which use DMA.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
2015-04-16 19:27:40 -06:00
Simon Glass
069f5481ba x86: config: Enable hook for saving MRC configuration
Add a hook to ensure that this information is saved.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-01-24 06:13:45 -07:00
Simon Glass
b18c68d891 x86: Use ipchecksum from net/
The existing IP checksum function is only accessible to the 'coreboot' cpu.
Drop it in favour of the new code in the network subsystem.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-24 06:13:44 -07:00
Bin Meng
cdcc17d73d x86: coreboot: Configure pci memory regions
Configure coreboot pci memory regions so that pci device drivers
could work correctly.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:05 -08:00
Bin Meng
9d74f03460 x86: coreboot: Move coreboot-specific defines from coreboot.h to Kconfig
There are many places in the U-Boot source tree which refer to
CONFIG_SYS_COREBOOT, CONFIG_CBMEM_CONSOLE and CONFIG_VIDEO_COREBOOT
that is currently defined in coreboot.h.

Move them to arch/x86/cpu/coreboot/Kconfig so that we can switch
to board configuration file to build U-Boot later.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:03 -08:00
Bin Meng
5c564b0d2f x86: coreboot: Set up timer base correctly
If coreboot is built with CONFIG_COLLECT_TIMESTAMPS, use the value
of base_time in coreboot's timestamp table as our timer base,
otherwise TSC counter value will be used.

Sometimes even coreboot is built with CONFIG_COLLECT_TIMESTAMPS,
the value of base_time in the timestamp table is still zero, so
we must exclude this case too (this is currently seen on booting
coreboot in qemu).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:02 -08:00
Simon Glass
aff2523f69 x86: Add support for MTRRs
Memory Type Range Registers are used to tell the CPU whether memory is
cacheable and if so the cache write mode to use.

Clean up the existing header file to follow style, and remove the unneeded
code.

These can speed up booting so should be supported. Add these to global_data
so they can be requested while booting. We will apply the changes during
relocation (in a later commit).

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:00 -08:00
Masahiro Yamada
afc366f01b Replace <compiler.h> with <linux/compiler.h>
Including <linux/compiler.h> is enough for general use.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-08 09:35:46 -05:00
Simon Glass
65990d5680 x86: Remove board_early_init_r()
This function is not needed. Remove it to improve the generic init sequence
slightly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-25 06:33:59 -07:00
Tom Rini
746667f1e5 Merge git://git.denx.de/u-boot-x86
Conflicts:
	arch/x86/cpu/Makefile

Signed-off-by: Tom Rini <trini@ti.com>
2014-11-24 12:00:00 -05:00
Masahiro Yamada
37c9940a09 x86: use CONFIG_SYS_COREBOOT to descend into coreboot/ directory
The references of CONFIG_SYS_COREBOOT in arch/x86/cpu/coreboot/Makefile
are redundant because the build system descends into the directory
only when CONFIG_SYS_COREBOOT is defined.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
2014-11-23 06:49:02 -05:00
Masahiro Yamada
b41411954d linux/kernel.h: sync min, max, min3, max3 macros with Linux
U-Boot has never cared about the type when we get max/min of two
values, but Linux Kernel does.  This commit gets min, max, min3, max3
macros synced with the kernel introducing type checks.

Many of references of those macros must be fixed to suppress warnings.
We have two options:
 - Use min, max, min3, max3 only when the arguments have the same type
   (or add casts to the arguments)
 - Use min_t/max_t instead with the appropriate type for the first
   argument

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Pavel Machek <pavel@denx.de>
Acked-by: Lukasz Majewski <l.majewski@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
[trini: Fixup arch/blackfin/lib/string.c]
Signed-off-by: Tom Rini <trini@ti.com>
2014-11-23 06:48:30 -05:00
Simon Glass
a49e3c7f09 x86: Make show_boot_progress() common
This function can probably be used on all x86 boards, so move it into the
common file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:15 +01:00
Simon Glass
378a8634ad x86: Tidy up coreboot header usage
There is no need to explicitly write 'arch-coreboot' when including headers,
as when the arch directory points to coreboot the correct files will be
used.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:13 +01:00
Simon Glass
d188b18f65 x86: Refactor PCI to permit alternate init
We want access PCI earlier in the init sequence, so refactor the code so
that it does not require use of a BSS variable to work. This will allow us
to use early malloc() to store information about a PCI hose.

Common PCI code moves to arch/x86/cpu/pci.c and a new
board_pci_setup_hose() function is provided by boards to set up the (single)
hose used by that board.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21 07:34:11 +01:00
Simon Glass
d1cd045982 x86: Emit post codes in startup code for Chromebooks
On x86 it is common to use 'post codes' which are 8-bit hex values emitted
from the code and visible to the user. Traditionally two 7-segment displays
were made available on the motherboard to show the last post code that was
emitted. This allows diagnosis of a boot problem since it is possible to
see where the code got to before it died.

On modern hardware these codes are not normally visible. On Chromebooks
they are displayed by the Embedded Controller (EC), so it is useful to emit
them. We must enable this feature for the EC to see the codes, so add an
option for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21 07:34:11 +01:00
Simon Glass
8ef07571a0 x86: Add chromebook_link board
This board is a 'bare' version of the existing 'link 'board. It does not
require coreboot to run, but is intended to start directly from the reset
vector.

This initial commit has place holders for a wide range of features. These
will be added in follow-on patches and series. So far it cannot be booted
as there is no ROM image produced, but it does build without errors.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:34:11 +01:00
Masahiro Yamada
a5eb04db1a x86: use CONFIG_SYS_COREBOOT to descend into coreboot/ directory
The references of CONFIG_SYS_COREBOOT in arch/x86/cpu/coreboot/Makefile
are redundant because the build system descends into the directory
only when CONFIG_SYS_COREBOOT is defined.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
2014-11-21 07:24:12 +01:00
Simon Glass
727c1a9871 x86: Replace fill_processor_name() with cpu_get_name()
This implementation has a 'cpu' prefix and returns a pointer to the string,
avoiding the need for copying.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21 07:24:12 +01:00
Simon Glass
e1ffd81797 x86: Fix up some missing prototypes
Some functions are missing prototypes. Fix those that are specific to x86.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21 07:24:09 +01:00
Simon Glass
8b37c7694f x86: Use the standard arch_cpu_init() function
Instead of an x86-specific cpu_init_f() function, use the normal U-Boot one
for this purpose. Also remove a useless/misleading comment.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21 07:24:09 +01:00
Simon Glass
07387d1769 x86: Use the standard dram_init() function
Instead of having an x86-specific DRAM init function, adjust things so we
can use the normal one.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2014-11-21 07:24:09 +01:00
Masahiro Yamada
254d68b601 kbuild: move asm-offsets.c from SoC directory to arch/$(ARCH)/lib
U-Boot has supported two kinds of asm-offsets.h.

One is generic for all architectures and its source is located at
./lib/asm-offsets.c.

The other is SoC specific and its source is under SoC directory.
The problem here is that only boards with SoC directory can use
the asm-offsets infrastructure.
Putting asm-offsets.c right under CPU directory does not work.

Now a new demand is coming. PowerPC folks want to use asm-offsets.
But no PowerPC boards have SoC directory.

It seems inconsistent that some boards add asm-offsets.c to SoC
directoreis and some to CPU directories.
It looks more reasonable to put asm-offsets.c under arch/$(ARCH)/lib.

This commit merges asm-offsets.c under SoC directories into
arch/$(ARCH)/lib/asm-offsets.c.

By the way, I doubt the necessity of some entries in asm-offsets.c.
I am leaving refactoring to the board maintainers.
Please check "TODO" in the comment blocks in
arch/{arm,nds32}/lib/asm-offsets.c.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Yuantian Tang <Yuantian.Tang@freescale.com>
2014-03-28 15:06:29 -04:00
Masahiro Yamada
3954b739b3 x86: convert makefiles to Kbuild style
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
2013-11-01 11:42:12 -04:00
Wolfgang Denk
3765b3e7bd Coding Style cleanup: remove trailing white space
Signed-off-by: Wolfgang Denk <wd@denx.de>
2013-10-14 16:06:53 -04:00
Wolfgang Denk
cb3761ea99 SPDX-License-Identifier: convert BSD-3-Clause files
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini Don't remove some copyrights by accident]
Signed-off-by: Tom Rini <trini@ti.com>
2013-08-19 15:45:35 -04:00
Stephen Warren
065202803d config: don't define CONFIG_ARCH_DEVICE_TREE
Now that nothing uses CONFIG_ARCH_DEVICE_TREE, stop defining it.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
2013-08-02 18:30:11 -04:00
Wolfgang Denk
1a4596601f Add GPL-2.0+ SPDX-License-Identifier to source files
Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>
2013-07-24 09:44:38 -04:00
Simon Glass
8f0278eab4 x86: Add coreboot timestamps
Add selected coreboot timestamps into bootstage to get a unified view of
the boot timings.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-05-13 13:33:22 -07:00
Simon Glass
5397d8058c x86: Support adding coreboot timestanps to bootstage
Coreboot provides a lot of useful timing information. Provide a facility
to add this to bootstage on start-up.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-05-13 13:33:22 -07:00
Simon Glass
e761ecdbb8 x86: Add TSC timer
This timer runs at a rate that can be calculated, well over 100MHz. It is
ideal for accurate timing and does not need interrupt servicing.

Tidy up some old broken and unneeded implementations at the same time.

To provide a consistent view of boot time, we use the same time
base as coreboot. Use the base timestamp supplied by coreboot
as U-Boot's base time.

Signed-off-by: Simon Glass <sjg@chromium.org>base
Signed-off-by: Simon Glass <sjg@chromium.org>
2013-05-13 13:33:21 -07:00
Simon Glass
c78a62acdf x86: Implement panic output for coreboot
panic_puts() can be called in early boot to display a message. It might
help with early debugging.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Wai-Hong Tam <waihong@chromium.org>
2013-05-13 13:33:20 -07:00
Simon Glass
8b42dfc3b6 x86: Fix DRAM bank size init with generic board
The intention of the memory init code is that it should work the same with
CONFIG_SYS_GENERIC_BOARD and without. This is tricky because dram_init()
is called prior to relocation with generic board (matching other archs)
and after relocation without generic board.

Adjust the init sequence so that dram_init() is not called in the generic
board case, which seems like the easiest fix for now. Also ensure that
relocation addresses are still calculated.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-04-15 16:26:09 -07:00
Simon Glass
86cfb6bdec x86: Use sections header to obtain link symbols
These are defined in asm-generic/sections.h, so remove them from
architecture-specific files.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-15 16:14:00 -04:00
Simon Glass
bc2df1afb9 x86: Permit bootstage and timer data to be used prior to relocation
It is useful to be able to access the timer before U-Boot has relocated
so that we can fully support bootstage.

Add new global_data members to support this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-04 15:57:36 -08:00
Simon Glass
5e98947f9b x86: Add function to get top of usable ram
The memory layout calculations are done in calculate_relocation_address(),
and coreboot has its own version of this function. But in fact all we
really need is to set the top of usable RAM, and then the base version
will work as is.

So instead of allowing the whole calculate_relocation_address() function
to be replaced, create board_get_usable_ram_top() which can be used by
a board to specify the top of the area where U-Boot relocations to.

Signed-off-by: Simon Glass <sjg@chromium.org>
2013-03-04 15:56:46 -08:00
Stefan Reinauer
c94663170b x86: drop unused code in coreboot.c
The function setup_pcat_compatibility() is weak and implemented as empty
function in board.c hence we don't have to override that with another
empty function.

monitor_flash_len is unused, drop it.

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:44 -08:00
Stefan Reinauer
2b9d2252aa x86: Remove coreboot_ from file name
... because that information is already "encoded" in the directory name.

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:43 -08:00
Vadim Bendebury
1350f1cce1 x86: Provide a way to throttle port80 accesses
Some systems (like Google Link device) provide the ability to keep a
history of the target CPU port80 accesses, which is extremely handy
for debugging. The problem is that the EC handling port 80 access is
orders of magnitude slower than the AP. This causes random loss of
trace data.

This change allows to throttle port 80 accesses such that in case the
AP is trying to post faster than the EC can handle, a delay is
introduced to make sure that the post rate is throttled. Experiments
have shown that on Link the delay should be at least 350,000 of tsc
clocks.

Throttling is not being enabled by default: to enable it one would
have to set MIN_PORT80_KCLOCKS_DELAY to something like 400 and rebuild
the u-boot image. With upcoming EC code optimizations this number
could be decreased (new new value should be established
experimentally).

Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:43 -08:00
Duncan Laurie
b83058cd23 x86: Issue SMI to finalize Coreboot in final stage
This will write magic value to APMC command port which
will trigger an SMI and cause coreboot to lock down
the ME, chipset, and CPU.

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
2012-12-06 14:30:43 -08:00