Vadim Bendebury 1350f1cce1 x86: Provide a way to throttle port80 accesses ... Some systems (like Google Link device) provide the ability to keep a history of the target CPU port80 accesses, which is extremely handy for debugging. The problem is that the EC handling port 80 access is orders of magnitude slower than the AP. This causes random loss of trace data. This change allows to throttle port 80 accesses such that in case the AP is trying to post faster than the EC can handle, a delay is introduced to make sure that the post rate is throttled. Experiments have shown that on Link the delay should be at least 350,000 of tsc clocks. Throttling is not being enabled by default: to enable it one would have to set MIN_PORT80_KCLOCKS_DELAY to something like 400 and rebuild the u-boot image. With upcoming EC code optimizations this number could be decreased (new new value should be established experimentally). Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>		2012-12-06 14:30:43 -08:00
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asm-offsets.c	x86: Initial commit for running as a coreboot payload	2011-12-19 13:26:15 +11:00
config.mk	x86: coreboot: Set CONFIG_ARCH_DEVICE_TREE correctly	2012-12-06 14:30:42 -08:00
coreboot.c	x86: Provide a way to throttle port80 accesses	2012-12-06 14:30:43 -08:00
coreboot_car.S	x86: Initial commit for running as a coreboot payload	2011-12-19 13:26:15 +11:00
ipchecksum.c	x86: Import code from coreboot's libpayload to parse the coreboot table	2011-12-19 13:26:15 +11:00
Makefile	x86: Enable coreboot timestamp facility support in u-boot.	2012-12-06 14:30:38 -08:00
pci.c	x86: coreboot: Implement recursively scanning PCI busses	2012-11-28 11:40:05 -08:00
sdram.c	x86: Override calculate_relocation_address to use the e820 map	2012-12-06 14:30:42 -08:00
tables.c	x86: coreboot: Decode additional coreboot sysinfo tags	2012-11-30 13:44:03 -08:00
timestamp.c	x86: Enable coreboot timestamp facility support in u-boot.	2012-12-06 14:30:38 -08:00