This patch adds NAND booting support for the AMCC Acadia eval board.
Please make sure to configure jumper J7 to position 2-3 when booting
from NOR, and to position 1-2 when booting for NAND.
I also added a board command to configure the I2C bootstrap EEPROM
values. Right now only 267MHz is support for booting either via NOR
or NAND FLASH. Here the usage:
=> bootstrap 267 nor ;to configure the board for 267MHz NOR booting
=> bootstrap 267 nand ;to configure the board for 267MHz NNAND booting
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds NAND booting support for the AMCC Bamboo eval board.
Since the NAND-SPL boot image is limited to 4kbytes, this version
only supports the onboard 64MBytes of DDR. The DIMM modules can't be
supported, since the setup code for I2C DIMM autodetection and
configuration is too big for this NAND bootloader.
Signed-off-by: Stefan Roese <sr@denx.de>
Enable redundant environment, add a MTD partition for it; also add env.
variable command for passing MTD partitions to the kernel command line.
Signed-off-by: Piotr Kruszynski <ppk@semihalf.com>
Acked-by: Bartlomiej Sieka <tur@semihalf.com>
Allow passing longer command line to the kernel - useful especially
for passing MTD partition layout.
Signed-off-by: Piotr Kruszynski <ppk@semihalf.com>
Acked-by: Bartlomiej Sieka <tur@semihalf.com>
Change EEPROM configuration according to the datasheet: "The 24C01A and 24C02A
have a page write capability of two bytes", and "This device offers fast (1ms)
byte write". Add 3ms of extra delay.
Signed-off-by: Piotr Kruszynski <ppk@semihalf.com>
Acked-by: Bartlomiej Sieka <tur@semihalf.com>
After being reset in mpc5xxx_fec_init_phy(), PHY goes into FX mode, in which
networking does not function. This commit switches PHY to TX mode by clearing
the FX_SEL bit of Mode Control Register. It also reverses commit
008861a2f3, i.e., a temporary workaround.
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Acked-by: Bartlomiej Sieka <tur@semihalf.com>
Both CFG_PCISPEED_66 and CFG_IPBSPEED_133 are misnamed, as defining
them does not cause PCI or IPB clocks to run at the specified speed.
Instead, they configure divisors used to calculate said clocks. This
patch renames the defines according to their real function.
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Acked-by: Bartlomiej Sieka <tur@semihalf.com>
This patch updates the Acadia (405EZ) support for the new 1.1 board
revision. It also adds support for NAND FLASH via the 4xx NDFC.
Please note that the jumper J7 must be in position 2-3 for this
NAND support. Position 1-2 is for NAND booting only. NAND booting
support will follow later.
Signed-off-by: Stefan Roese <sr@denx.de>
A '3' got cut off in the formatting of the last patch to automatically
change the clock speed of the system clock on sequoia board.
Signed-off-by: Jeffrey Mann <mannj@embeddedplanet.com>
Signed-off-by: Stefan Roese <sr@denx.de>
MPC5200B systems are incorrectly reported as MPC5200 in U-Boot start-up
message. Use PVR to distinguish between the two variants, and print proper CPU
information.
Signed-off-by: Grzegorz Wianecki <grzegorz.wianecki@gmail.com>
Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
