Merge with /home/wd/git/u-boot/custodian/u-boot-ppc4xx

This commit is contained in:
Wolfgang Denk 2007-05-05 18:07:10 +02:00
commit f51697316a
8 changed files with 55 additions and 171 deletions

View file

@ -277,87 +277,6 @@ int board_early_init_f(void)
return 0;
}
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#include <linux/mtd/nand_legacy.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
/*----------------------------------------------------------------------------+
| nand_reset.
| Reset Nand flash
| This routine will abort previous cmd
+----------------------------------------------------------------------------*/
int nand_reset(ulong addr)
{
int wait=0, stat=0;
out8(addr + NAND_CMD_REG, NAND0_CMD_RESET);
out8(addr + NAND_CMD_REG, NAND0_CMD_READ_STATUS);
while ((stat != 0xc0) && (wait != 0xffff)) {
stat = in8(addr + NAND_DATA_REG);
wait++;
}
if (stat == 0xc0) {
return 0;
} else {
printf("NAND Reset timeout.\n");
return -1;
}
}
void board_nand_set_device(int cs, ulong addr)
{
/* Set NandFlash Core Configuration Register */
out32(addr + NAND_CCR_REG, 0x00001000 | (cs << 24));
switch (cs) {
case 1:
/* -------
* NAND0
* -------
* K9F1208U0A : 4 addr cyc, 1 col + 3 Row
* Set NDF1CR - Enable External CS1 in NAND FLASH controller
*/
out32(addr + NAND_CR1_REG, 0x80002222);
break;
case 2:
/* -------
* NAND1
* -------
* K9K2G0B : 5 addr cyc, 2 col + 3 Row
* Set NDF2CR : Enable External CS2 in NAND FLASH controller
*/
out32(addr + NAND_CR2_REG, 0xC0007777);
break;
}
/* Perform Reset Command */
if (nand_reset(addr) != 0)
return;
}
void nand_init(void)
{
board_nand_set_device(1, CFG_NAND_ADDR);
nand_probe(CFG_NAND_ADDR);
if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
print_size(nand_dev_desc[0].totlen, "\n");
}
#if 0 /* NAND1 not supported yet */
board_nand_set_device(2, CFG_NAND2_ADDR);
nand_probe(CFG_NAND2_ADDR);
if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
print_size(nand_dev_desc[0].totlen, "\n");
}
#endif
}
#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */
int checkboard(void)
{
char *s = getenv("serial#");

View file

@ -68,19 +68,7 @@ SECTIONS
cpu/ppc4xx/start.o (.text)
board/amcc/bamboo/init.o (.text)
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
lib_generic/zlib.o (.text)
/* . = env_offset;*/
/* common/environment.o(.text)*/
board/amcc/bamboo/bamboo.o (.text)
*(.text)
*(.fixup)

View file

@ -371,6 +371,14 @@ void denali_core_search_data_eye(unsigned long memory_size)
}
#endif /* CONFIG_DDR_DATA_EYE */
#if defined(CONFIG_NAND_SPL)
/* Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big
* for the 4k NAND boot image so define bus_frequency to 133MHz here
* which is save for the refresh counter setup.
*/
#define get_bus_freq(val) 133000000
#endif
/*************************************************************************
*
* initdram -- 440EPx's DDR controller is a DENALI Core
@ -404,7 +412,7 @@ long int initdram (int board_type)
mtsdram(DDR0_22, 0x00267F0B);
mtsdram(DDR0_23, 0x00000000);
mtsdram(DDR0_24, 0x01010002);
if (speed > 133333333)
if (speed > 133333334)
mtsdram(DDR0_26, 0x5B26050C);
else
mtsdram(DDR0_26, 0x5B260408);

View file

@ -339,29 +339,41 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
{
unsigned long zmiifer=0x0;
unsigned long pfc1;
/*
* Right now only 2*RGMII is supported. Please extend when needed.
* sr - 2006-08-29
*/
switch (1) {
case 0:
mfsdr(sdr_pfc1, pfc1);
pfc1 &= SDR0_PFC1_SELECT_MASK;
switch (pfc1) {
case SDR0_PFC1_SELECT_CONFIG_2:
/* 1 x GMII port */
out32 (ZMII_FER, 0x00);
out32 (RGMII_FER, 0x00000037);
bis->bi_phymode[0] = BI_PHYMODE_GMII;
bis->bi_phymode[1] = BI_PHYMODE_NONE;
break;
case 1:
case SDR0_PFC1_SELECT_CONFIG_4:
/* 2 x RGMII ports */
out32 (ZMII_FER, 0x00);
out32 (RGMII_FER, 0x00000055);
bis->bi_phymode[0] = BI_PHYMODE_RGMII;
bis->bi_phymode[1] = BI_PHYMODE_RGMII;
break;
case 2:
case SDR0_PFC1_SELECT_CONFIG_6:
/* 2 x SMII ports */
out32 (ZMII_FER,
((ZMII_FER_SMII) << ZMII_FER_V(0)) |
((ZMII_FER_SMII) << ZMII_FER_V(1)));
out32 (RGMII_FER, 0x00000000);
bis->bi_phymode[0] = BI_PHYMODE_SMII;
bis->bi_phymode[1] = BI_PHYMODE_SMII;
break;
case SDR0_PFC1_SELECT_CONFIG_1_2:
/* only 1 x MII supported */
out32 (ZMII_FER, (ZMII_FER_MII) << ZMII_FER_V(0));
out32 (RGMII_FER, 0x00000000);
bis->bi_phymode[0] = BI_PHYMODE_MII;
bis->bi_phymode[1] = BI_PHYMODE_NONE;
break;
default:
break;

View file

@ -1,5 +1,5 @@
/*
* (C) Copyright 2005-2006
* (C) Copyright 2005-2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
@ -43,7 +43,6 @@
* 2nd ethernet port you have to "undef" the following define.
*/
#define CONFIG_BAMBOO_NAND 1 /* enable nand flash support */
#define CFG_NAND_LEGACY
/*-----------------------------------------------------------------------
* Base addresses -- Note these are effective addresses where the
@ -143,65 +142,13 @@
#endif /* CFG_ENV_IS_IN_FLASH */
/*-----------------------------------------------------------------------
* NAND-FLASH related
* NAND FLASH
*----------------------------------------------------------------------*/
#define NAND_CMD_REG (0x00) /* NandFlash Command Register */
#define NAND_ADDR_REG (0x04) /* NandFlash Address Register */
#define NAND_DATA_REG (0x08) /* NandFlash Data Register */
#define NAND_ECC0_REG (0x10) /* NandFlash ECC Register0 */
#define NAND_ECC1_REG (0x14) /* NandFlash ECC Register1 */
#define NAND_ECC2_REG (0x18) /* NandFlash ECC Register2 */
#define NAND_ECC3_REG (0x1C) /* NandFlash ECC Register3 */
#define NAND_ECC4_REG (0x20) /* NandFlash ECC Register4 */
#define NAND_ECC5_REG (0x24) /* NandFlash ECC Register5 */
#define NAND_ECC6_REG (0x28) /* NandFlash ECC Register6 */
#define NAND_ECC7_REG (0x2C) /* NandFlash ECC Register7 */
#define NAND_CR0_REG (0x30) /* NandFlash Device Bank0 Config Register */
#define NAND_CR1_REG (0x34) /* NandFlash Device Bank1 Config Register */
#define NAND_CR2_REG (0x38) /* NandFlash Device Bank2 Config Register */
#define NAND_CR3_REG (0x3C) /* NandFlash Device Bank3 Config Register */
#define NAND_CCR_REG (0x40) /* NandFlash Core Configuration Register */
#define NAND_STAT_REG (0x44) /* NandFlash Device Status Register */
#define NAND_HWCTL_REG (0x48) /* NandFlash Direct Hwd Control Register */
#define NAND_REVID_REG (0x50) /* NandFlash Core Revision Id Register */
/* Nand Flash K9F1208U0A Command Set => Nand Flash 0 */
#define NAND0_CMD_READ1_HALF1 0x00 /* Starting addr for 1rst half of registers */
#define NAND0_CMD_READ1_HALF2 0x01 /* Starting addr for 2nd half of registers */
#define NAND0_CMD_READ2 0x50
#define NAND0_CMD_READ_ID 0x90
#define NAND0_CMD_READ_STATUS 0x70
#define NAND0_CMD_RESET 0xFF
#define NAND0_CMD_PAGE_PROG 0x80
#define NAND0_CMD_PAGE_PROG_TRUE 0x10
#define NAND0_CMD_PAGE_PROG_DUMMY 0x11
#define NAND0_CMD_BLOCK_ERASE 0x60
#define NAND0_CMD_BLOCK_ERASE_END 0xD0
#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
#define SECTORSIZE 512
#define ADDR_COLUMN 1
#define ADDR_PAGE 2
#define ADDR_COLUMN_PAGE 3
#define NAND_ChipID_UNKNOWN 0x00
#define NAND_MAX_FLOORS 1
#define NAND_MAX_CHIPS 1
#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_CMD_REG) = d;} while(0)
#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_ADDR_REG) = d;} while(0)
#define WRITE_NAND(d, adr) do {*(volatile u8 *)((ulong)adr+NAND_DATA_REG) = d;} while(0)
#define READ_NAND(adr) (*(volatile u8 *)((ulong)adr+NAND_DATA_REG))
#define NAND_WAIT_READY(nand) while (!(*(volatile u8 *)((ulong)nand->IO_ADDR+NAND_STAT_REG) & 0x01))
/* not needed with 440EP NAND controller */
#define NAND_CTL_CLRALE(nandptr)
#define NAND_CTL_SETALE(nandptr)
#define NAND_CTL_CLRCLE(nandptr)
#define NAND_CTL_SETCLE(nandptr)
#define NAND_DISABLE_CE(nand)
#define NAND_ENABLE_CE(nand)
#define CFG_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
#define CFG_NAND_CS 1
#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS)
#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
/*-----------------------------------------------------------------------
* DDR SDRAM

View file

@ -360,7 +360,19 @@
EBC_BXCR_BW_16BIT)
/* Memory Bank 1 (Xilinx System ACE controller) initialization */
#define CFG_EBC_PB1AP 0x7F8FFE80
#define CFG_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \
EBC_BXAP_TWT_ENCODE(4) | \
EBC_BXAP_BCE_DISABLE | \
EBC_BXAP_BCT_2TRANS | \
EBC_BXAP_CSN_ENCODE(0) | \
EBC_BXAP_OEN_ENCODE(0) | \
EBC_BXAP_WBN_ENCODE(0) | \
EBC_BXAP_WBF_ENCODE(0) | \
EBC_BXAP_TH_ENCODE(0) | \
EBC_BXAP_RE_DISABLED | \
EBC_BXAP_SOR_NONDELAYED | \
EBC_BXAP_BEM_WRITEONLY | \
EBC_BXAP_PEN_DISABLED)
#define CFG_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CFG_ACE_BASE) | \
EBC_BXCR_BS_1MB | \
EBC_BXCR_BU_RW | \

View file

@ -38,7 +38,9 @@
#define CONFIG_440GRX 1 /* Specific PPC440GRx */
#endif
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_SYS_CLK_FREQ 33000000 /* external freq to pll */
/* Detect Sequoia PLL input clock automatically via CPLD bit */
#define CONFIG_SYS_CLK_FREQ ((in8(CFG_BCSR_BASE + 3) & 0x80) ? \
3333333 : 33000000)
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */

View file

@ -30,7 +30,7 @@ AFLAGS += -DCONFIG_NAND_SPL
CFLAGS += -DCONFIG_NAND_SPL
SOBJS = start.o init.o resetvec.o
COBJS = nand_boot.o ndfc.o sdram.o speed.o
COBJS = nand_boot.o ndfc.o sdram.o
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
@ -69,10 +69,6 @@ $(obj)start.S:
@rm -f $(obj)start.S
ln -s $(SRCTREE)/cpu/ppc4xx/start.S $(obj)start.S
$(obj)speed.c:
@rm -f $(obj)speed.c
ln -s $(SRCTREE)/cpu/ppc4xx/speed.c $(obj)speed.c
# from board directory
$(obj)init.S:
@rm -f $(obj)init.S