Merge with /home/tur/git/u-boot#motionpro

This commit is contained in:
Wolfgang Denk 2007-05-28 01:11:11 +02:00
commit 19bf91f962
25 changed files with 190 additions and 91 deletions

View file

@ -28,11 +28,15 @@
#include <common.h>
#include <mpc5xxx.h>
#include <miiphy.h>
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
#endif
#if defined(CONFIG_STATUS_LED)
#include <status_led.h>
#endif /* CONFIG_STATUS_LED */
/* Kollmorgen DPR initialization data */
struct init_elem {
unsigned long addr;
@ -78,11 +82,27 @@ int board_early_init_r(void)
}
/*
* Additional PHY intialization. After being reset in mpc5xxx_fec_init_phy(),
* PHY goes into FX mode. To take it out of the FX mode and switch into
* desired TX operation, one needs to clear the FX_SEL bit of Mode Control
* Register.
*/
void reset_phy(void)
{
unsigned short mode_control;
miiphy_read("FEC ETHERNET", CONFIG_PHY_ADDR, 0x15, &mode_control);
miiphy_write("FEC ETHERNET", CONFIG_PHY_ADDR, 0x15,
mode_control & 0xfffe);
return;
}
#ifndef CFG_RAMBOOT
/*
* Helper function to initialize SDRAM controller.
*/
static void sdram_start (int hi_addr)
static void sdram_start(int hi_addr)
{
long hi_addr_bit = hi_addr ? 0x01000000 : 0;
@ -114,7 +134,7 @@ static void sdram_start (int hi_addr)
/*
* Initalize SDRAM - configure SDRAM controller, detect memory size.
*/
long int initdram (int board_type)
long int initdram(int board_type)
{
ulong dramsize = 0;
#ifndef CFG_RAMBOOT
@ -168,9 +188,10 @@ long int initdram (int board_type)
}
int checkboard (void)
int checkboard(void)
{
puts("Board: Promess Motion-PRO board\n");
uchar rev = *(vu_char *)CPLD_REV_REGISTER;
printf("Board: Promess Motion-PRO board (CPLD rev. 0x%02x)\n", rev);
return 0;
}
@ -181,3 +202,29 @@ void ft_board_setup(void *blob, bd_t *bd)
ft_cpu_setup(blob, bd);
}
#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
#if defined(CONFIG_STATUS_LED)
void __led_init(led_id_t regaddr, int state)
{
*((vu_long *) regaddr) |= ENABLE_GPIO_OUT;
if (state == STATUS_LED_ON)
*((vu_long *) regaddr) |= LED_ON;
else
*((vu_long *) regaddr) &= ~LED_ON;
}
void __led_set(led_id_t regaddr, int state)
{
if (state == STATUS_LED_ON)
*((vu_long *) regaddr) |= LED_ON;
else
*((vu_long *) regaddr) &= ~LED_ON;
}
void __led_toggle(led_id_t regaddr)
{
*((vu_long *) regaddr) ^= LED_ON;
}
#endif /* CONFIG_STATUS_LED */

View file

@ -1191,6 +1191,8 @@ static void process_macros (const char *input, char *output)
if (outputcnt)
*output = 0;
else
*(output - 1) = 0;
#ifdef DEBUG_PARSER
printf ("[PROCESS_MACROS] OUTPUT len %d: \"%s\"\n",

View file

@ -156,21 +156,21 @@ void cpu_init_f (void)
*(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 15);
*(vu_long *)(MPC5XXX_XLBARB + 0x70) = CFG_SDRAM_BASE | 0x1d;
# if defined(CFG_IPBSPEED_133)
# if defined(CFG_IPBCLK_EQUALS_XLBCLK)
/* Motorola reports IPB should better run at 133 MHz. */
*(vu_long *)MPC5XXX_ADDECR |= 1;
/* pci_clk_sel = 0x02, ipb_clk_sel = 0x00; */
addecr = *(vu_long *)MPC5XXX_CDM_CFG;
addecr &= ~0x103;
# if defined(CFG_PCISPEED_66)
# if defined(CFG_PCICLK_EQUALS_IPBCLK_DIV2)
/* pci_clk_sel = 0x01 -> IPB_CLK/2 */
addecr |= 0x01;
# else
/* pci_clk_sel = 0x02 -> XLB_CLK/4 = IPB_CLK/4 */
addecr |= 0x02;
# endif /* CFG_PCISPEED_66 */
# endif /* CFG_PCICLK_EQUALS_IPBCLK_DIV2 */
*(vu_long *)MPC5XXX_CDM_CFG = addecr;
# endif /* CFG_IPBSPEED_133 */
# endif /* CFG_IPBCLK_EQUALS_XLBCLK */
/* Configure the XLB Arbiter */
*(vu_long *)MPC5XXX_XLBARB_MPRIEN = 0xff;
*(vu_long *)MPC5XXX_XLBARB_MPRIVAL = 0x11111111;

View file

@ -395,9 +395,7 @@ static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis)
{
mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
#ifndef CONFIG_MOTIONPRO
const uint8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */
#endif /* !CONFIG_MOTIONPRO */
#if (DEBUG & 0x1)
printf ("mpc5xxx_fec_init_phy... Begin\n");
@ -437,7 +435,6 @@ static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis)
* PHY initialization for the Motion-PRO board, until a proper fix is found.
*/
#ifndef CONFIG_MOTIONPRO
if (fec->xcv_type != SEVENWIRE) {
/*
* Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
@ -564,7 +561,6 @@ static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis)
}
}
#endif /* !CONFIG_MOTIONPRO */
#if (DEBUG & 0x2)
if (fec->xcv_type != SEVENWIRE)

View file

@ -282,17 +282,17 @@
/*
* IPB Bus clocking configuration.
*/
#define CFG_IPBSPEED_133 /* define for 133MHz speed */
#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
/*
* PCI Bus clocking configuration
*
* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
* CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet
* hasn't been tested with a IPB Bus Clock of 66 MHz.
* CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
* of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
*/
#if defined(CFG_IPBSPEED_133)
# define CFG_PCISPEED_66 /* define for 66MHz speed */
#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
# define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
#endif
/*
@ -488,7 +488,7 @@
#define CFG_BOOTCS_START CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
#ifdef CFG_PCISPEED_66
#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
# define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
#else
# define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */

View file

@ -167,9 +167,9 @@
* IPB Bus clocking configuration.
*/
#if defined(CONFIG_LITE5200B)
#define CFG_IPBSPEED_133 /* define for 133MHz speed */
#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
#else
#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
#endif
#endif /* CONFIG_MPC5200 */

View file

@ -160,7 +160,7 @@
/*
* IPB Bus clocking configuration.
*/
#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
#endif
/*
* I2C configuration

View file

@ -200,17 +200,17 @@
/*
* IPB Bus clocking configuration.
*/
#define CFG_IPBSPEED_133 /* define for 133MHz speed */
#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
#if defined(CFG_IPBSPEED_133)
#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
/*
* PCI Bus clocking configuration
*
* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
* CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
* been tested with a IPB Bus Clock of 66 MHz.
* CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
* of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
*/
#define CFG_PCISPEED_66 /* define for 66MHz speed */
#define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
#endif
/*
@ -432,7 +432,7 @@
#define CFG_BOOTCS_START CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
#ifdef CFG_PCISPEED_66
#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
#else
#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */

View file

@ -186,7 +186,7 @@
/*
* IPB Bus clocking configuration.
*/
#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
/*
* I2C configuration

View file

@ -269,17 +269,17 @@
/*
* IPB Bus clocking configuration.
*/
#define CFG_IPBSPEED_133 /* define for 133MHz speed */
#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
#if defined(CFG_IPBSPEED_133) && !defined(CONFIG_CAM5200)
#if defined(CFG_IPBCLK_EQUALS_XLBCLK) && !defined(CONFIG_CAM5200)
/*
* PCI Bus clocking configuration
*
* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
* CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
* been tested with a IPB Bus Clock of 66 MHz.
* CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock of
* 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
*/
#define CFG_PCISPEED_66 /* define for 66MHz speed */
#define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
#endif
/*
@ -594,7 +594,7 @@
#define CFG_BOOTCS_START CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
#ifdef CFG_PCISPEED_66
#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
#else
#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */

View file

@ -183,7 +183,7 @@
/*
* IPB Bus clocking configuration.
*/
#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
#endif
/*

View file

@ -166,17 +166,17 @@
/*
* IPB Bus clocking configuration.
*/
#define CFG_IPBSPEED_133 /* define for 133MHz speed */
#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
#if defined(CFG_IPBSPEED_133)
#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
/*
* PCI Bus clocking configuration
*
* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
* CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
* been tested with a IPB Bus Clock of 66 MHz.
* CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
* of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
*/
#define CFG_PCISPEED_66 /* define for 66MHz speed */
#define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
#endif
/*
@ -362,7 +362,7 @@
#define CFG_BOOTCS_START CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
#ifdef CFG_PCISPEED_66
#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
#else
#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */

View file

@ -111,7 +111,7 @@
/*
* IPB Bus clocking configuration.
*/
#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
/*
* Flash configuration, expect one 16 Megabyte Bank at most

View file

@ -179,7 +179,7 @@
/*
* IPB Bus clocking configuration.
*/
#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
#endif
/*
* I2C configuration

View file

@ -110,7 +110,7 @@
/*
* IPB Bus clocking configuration.
*/
#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
/*
* I2C configuration

View file

@ -147,7 +147,7 @@
/*
* IPB Bus clocking configuration.
*/
#define CFG_IPBSPEED_133 /* define for 133MHz speed */
#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
/*
* Flash configuration

View file

@ -169,7 +169,7 @@
/*
* IPB Bus clocking configuration.
*/
#define CFG_IPBSPEED_133 /* define for 133MHz speed */
#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
/*
* I2C configuration

View file

@ -54,7 +54,8 @@
CFG_CMD_JFFS2 | \
CFG_CMD_I2C | \
CFG_CMD_DATE | \
CFG_CMD_EEPROM)
CFG_CMD_EEPROM | \
CFG_CMD_DTT)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
@ -75,7 +76,7 @@
#define CONFIG_MPC5xxx_FEC 1
#define CONFIG_PHY_ADDR 0x2
#define CONFIG_PHY_TYPE 0x79c874
#define CONFIG_RESET_PHY_R 1
/*
* Autobooting
@ -116,26 +117,27 @@
"fdt_file=/tftpboot/motionpro/motionpro.dtb\0" \
"ramdisk_file=/tftpboot/motionpro/uRamdisk\0" \
"multi_image_file=kernel+initrd+dtb.img\0" \
"load=tftp $(u-boot_addr) $(u-boot)\0" \
"load=tftp ${u-boot_addr} ${u-boot}\0" \
"update=prot off fff00000 fff3ffff; era fff00000 fff3ffff; " \
"cp.b $(u-boot_addr) fff00000 $(filesize);" \
"cp.b ${u-boot_addr} fff00000 ${filesize};" \
"prot on fff00000 fff3ffff\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=$(serverip):$(rootpath)\0" \
"nfsroot=${serverip}:${rootpath}\0" \
"fat_args=setenv bootargs rw\0" \
"addip=setenv bootargs $(bootargs) " \
"ip=$(ipaddr):$(serverip):$(gatewayip):" \
"$(netmask):$(hostname):$(netdev):off panic=1 " \
"console=$(console)\0" \
"net_nfs=tftp $(kernel_addr) $(bootfile); " \
"tftp $(fdt_addr) $(fdt_file); run nfsargs addip; " \
"bootm $(kernel_addr) - $(fdt_addr)\0" \
"net_self=tftp $(kernel_addr) $(bootfile); " \
"tftp $(fdt_addr) $(fdt_file); " \
"tftp $(ramdisk_addr) $(ramdisk_file); " \
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:" \
"${netmask}:${hostname}:${netdev}:off panic=1 " \
"console=${console}\0" \
"net_nfs=tftp ${kernel_addr} ${bootfile}; " \
"tftp ${fdt_addr} ${fdt_file}; run nfsargs addip; " \
"bootm ${kernel_addr} - ${fdt_addr}\0" \
"net_self=tftp ${kernel_addr} ${bootfile}; " \
"tftp ${fdt_addr} ${fdt_file}; " \
"tftp ${ramdisk_addr} ${ramdisk_file}; " \
"run ramargs addip; " \
"bootm $(kernel_addr) $(ramdisk_addr) $(fdt_addr)\0" \
"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
"fat_multi=run fat_args addip; fatload ide 0:1 " \
"${multi_image_addr} ${multi_image_file}; " \
"bootm ${multi_image_addr}\0" \
@ -160,9 +162,9 @@
/*
* Set IPB speed to 100MHz (yes, the #define is misnamed)
* Set IPB speed to 100MHz
*/
#define CFG_IPBSPEED_133
#define CFG_IPBCLK_EQUALS_XLBCLK
/*
@ -268,7 +270,8 @@
#define MTDIDS_DEFAULT "nor0=motionpro-0"
#define MTDPARTS_DEFAULT "mtdparts=motionpro-0:" \
"13m(fs),2m(kernel),256k(uboot)," \
"64k(env),64k(dtb),-(user_data)"
"64k(env),64k(redund_env),64k(dtb)," \
"-(user_data)"
/*
* IDE/ATA configuration
@ -297,8 +300,9 @@
* EEPROM configuration
*/
#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_EEPROM_PAGE_WRITE_BITS 3
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
#define CFG_EEPROM_PAGE_WRITE_ENABLE 1 /* DTT driver needs this */
#define CFG_EEPROM_PAGE_WRITE_BITS 1 /* 2 bytes per write cycle */
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 5 /* 2ms/cycle + 3ms extra */
#define CFG_I2C_MULTI_EEPROMS 1 /* 2 EEPROMs (addr:50,52) */
@ -309,6 +313,35 @@
#define CFG_I2C_RTC_ADDR 0x68
/*
* Status LED configuration
*/
#define CONFIG_STATUS_LED /* Status LED enabled */
#define CONFIG_BOARD_SPECIFIC_LED
#define ENABLE_GPIO_OUT 0x00000024
#define LED_ON 0x00000010
#ifndef __ASSEMBLY__
/*
* In case of Motion-PRO, a LED is identified by its corresponding
* GPT Enable and Mode Select Register.
*/
typedef volatile unsigned long * led_id_t;
extern void __led_init(led_id_t id, int state);
extern void __led_toggle(led_id_t id);
extern void __led_set(led_id_t id, int state);
#endif /* __ASSEMBLY__ */
/*
* Temperature sensor
*/
#define CONFIG_DTT_LM75 1
#define CONFIG_DTT_SENSORS { 0x49 }
/*
* Environment settings
*/
@ -318,6 +351,9 @@
#define CFG_ENV_SIZE 0x1000
#define CFG_ENV_SECT_SIZE 0x10000
/* Configuration of redundant environment */
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
/*
* Pin multiplexing configuration
@ -334,12 +370,18 @@
#define CFG_GPS_PORT_CONFIG 0x1105a004
/*
* Motion-PRO's CPLD revision control register
*/
#define CPLD_REV_REGISTER (CFG_CS2_START + 0x06)
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
@ -376,6 +418,6 @@
#define OF_CPU "PowerPC,5200@0"
#define OF_SOC "soc5200@f0000000"
#define OF_TBCLK (bd->bi_busfreq / 4)
#define OF_STDOUT_PAT "/soc5200@f0000000/serial@2000"
#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
#endif /* __CONFIG_H */

View file

@ -137,17 +137,17 @@
/*
* IPB Bus clocking configuration.
*/
#define CFG_IPBSPEED_133 /* define for 133MHz speed */
#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
#if defined(CFG_IPBSPEED_133)
#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
/*
* PCI Bus clocking configuration
*
* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
* CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
* been tested with a IPB Bus Clock of 66 MHz.
* CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
* of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
*/
#define CFG_PCISPEED_66 /* define for 66MHz speed */
#define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
#endif
#endif
@ -276,7 +276,7 @@
#define CFG_BOOTCS_START CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
#ifdef CFG_PCISPEED_66
#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
/*
* For 66 MHz PCI clock additional Wait State is needed for CS0 (flash).
*/

View file

@ -171,7 +171,7 @@
/*
* IPB Bus clocking configuration.
*/
#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
#endif
/*
* I2C configuration

View file

@ -138,17 +138,17 @@
/*
* IPB Bus clocking configuration.
*/
#define CFG_IPBSPEED_133 /* define for 133MHz speed */
#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
#if defined(CFG_IPBSPEED_133)
#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
/*
* PCI Bus clocking configuration
*
* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
* CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
* been tested with a IPB Bus Clock of 66 MHz.
* CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
* of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
*/
#define CFG_PCISPEED_66 /* define for 66MHz speed */
#define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
#endif
/*
@ -357,7 +357,7 @@
#define CFG_BOOTCS_START CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
#ifdef CFG_PCISPEED_66
#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
#else
#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */

View file

@ -219,17 +219,17 @@
/*
* IPB Bus clocking configuration.
*/
#define CFG_IPBSPEED_133 /* define for 133MHz speed */
#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
#if defined(CFG_IPBSPEED_133)
#if defined(CFG_IPBCLK_EQUALS_XLBCLK)
/*
* PCI Bus clocking configuration
*
* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
* CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
* been tested with a IPB Bus Clock of 66 MHz.
* CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
* of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
*/
#define CFG_PCISPEED_66 /* define for 66MHz speed */
#define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
#endif
/*
@ -444,7 +444,7 @@
#define CFG_BOOTCS_START CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
#ifdef CFG_PCISPEED_66
#ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
#else
#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */

View file

@ -114,7 +114,7 @@
/*
* IPB Bus clocking configuration.
*/
#define CFG_IPBSPEED_133 /* define for 133MHz speed */
#define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
/*
* I2C configuration

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@ -167,7 +167,7 @@
/*
* IPB Bus clocking configuration.
*/
#undef CFG_IPBSPEED_133 /* define for 133MHz speed */
#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
#endif
/*

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@ -355,6 +355,18 @@ void status_led_set (int led, int state);
# define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
#elif defined(CONFIG_MOTIONPRO)
#define STATUS_LED_BIT ((vu_long *) MPC5XXX_GPT6_ENABLE)
#define STATUS_LED_PERIOD (CFG_HZ / 10)
#define STATUS_LED_STATE STATUS_LED_BLINKING
#define STATUS_LED_BIT1 ((vu_long *) MPC5XXX_GPT7_ENABLE)
#define STATUS_LED_PERIOD1 (CFG_HZ / 10)
#define STATUS_LED_STATE1 STATUS_LED_OFF
#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
#else
# error Status LED configuration missing
#endif