Commit graph

81610 commits

Author SHA1 Message Date
Ashok Reddy Soma
afe03866a0 spi: zynqmp_qspi: Code alignment
Few lines are extented to next line though they can fit in 80 character
limit, align them to single line. No functional change.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20220825125906.11581-6-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-09-13 11:32:48 +02:00
Ashok Reddy Soma
a3d4bfb427 spi: zynqmp_gqspi: Fix issue of reading more than 32bits length
As the flash sizes are increasing day by day, QSPI can have devices of
size > 512MB. In qspi driver we are trying to read all the data at once
using DMA.

The DMA descriptor destination size is only 29bits long.

QSPIDMA_DST_SIZE 0xFF0F0804

BITS:  1:0      Reserved to keep word alignment
BITS: 28:2      Number of 4-byte words the DMA will transfer
BITS: 31:29     Reserved: Returns 0 when read, writes ignored

So we can only transfer data of 0x1FFFFFF0(512MB minus 4bytes) bytes.
Anything above will overflow this register and will ignore higher bits
above 29 bits.

Change the DMA functionality if the requested size is greater than or
equal to 512MB to read 256MB chunks.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20220825125906.11581-5-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-09-13 11:32:48 +02:00
Ashok Reddy Soma
d91b0f4a18 spi: zynqmp_gqspi: Add support for IO mode
Add support for io-mode transfers. This is necessary for UBIFS to work
properly with spi-nor devices. The driver will work in IO mode when
"has-io-mode" is passed from device tree instead of DMA.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20220825125906.11581-4-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-09-13 11:32:48 +02:00
Michal Simek
9e89e30d4d arm64: versal: Define zynqmp_mmio_write() for versal
GQSPI driver is using it but this function is never called for Versal
because it is removed by linker. But function should be declared to avoid
this build warning:
drivers/spi/zynqmp_gqspi.c: In function 'zynqmp_qspi_set_tapdelay':
drivers/spi/zynqmp_gqspi.c:378:3: warning: implicit declaration of function
'zynqmp_mmio_write' [-Wimplicit-function-declaration]
  378 |   zynqmp_mmio_write(IOU_TAPDLY_BYPASS_OFST,

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20220825125906.11581-3-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-09-13 11:32:48 +02:00
Ashok Reddy Soma
f4f1b65cc6 spi: zynqmp_gqspi: Add tap delays for Versal
Add tap delays for Versal platform and re-align the tapdelays code.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20220825125906.11581-2-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-09-13 11:32:48 +02:00
Ashok Reddy Soma
f7d4cab1b3 spi: cadence-qspi: Use priv instead of plat across the driver
As per driver model we should enumerate plat structure only in
of_to_plat() and should be used only in probe(). Copy required
plat structure info into priv structure in probe() and use priv
structure across the driver. So replace plat with priv structure across
the driver.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/20220824113847.7482-4-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-09-13 11:32:48 +02:00
Ashok Reddy Soma
d0003b5edf spi: cadence_qspi: Call read_setup for STIG_READ
In cadence_spi_read_id we are using STIG mode to read flash id's.
Call cadence_qspi_apb_command_read_setup() to setup cmd, addr and data
bus width properly before cadence_qspi_apb_command_read().

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/20220824113847.7482-3-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-09-13 11:32:48 +02:00
Ashok Reddy Soma
68852f3241 spi: cadence-qspi: Correct flash reset function name
In cadence_spi_probe, cadence_qspi_versal_flash_reset() is called to reset
the flash device. Looks like there is a mistake in previous series of
patches where it is defined as cadence_spi_versal_flash_reset() but
called as cadence_qspi_versal_flash_reset. Since there is a weak function
defined with the same name this issue was not caught.

Fix the issue by renaming cadence_spi_versal_flash_reset as
cadence_qspi_versal_flash_reset().

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/20220824113847.7482-2-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-09-13 11:32:48 +02:00
Ovidiu Panait
f459986e86 microblaze: add arch_print_bdinfo() implementation
Allow bdinfo command to print icache/dcache information:
U-Boot-mONStR> bdinfo
boot_params = 0x00000000
DRAM bank   = 0x00000000
-> start    = 0x04000000
-> size     = 0x04000000
flashstart  = 0x00000000
flashsize   = 0x00000000
flashoffset = 0x00000000
baudrate    = 9600 bps
relocaddr   = 0x07f76000
reloc off   = 0x02f76000
Build       = 32-bit
current eth = unknown
ethaddr     = (not set)
IP addr     = <NULL>
fdt_blob    = 0x07fec7e0
new_fdt     = 0x00000000
fdt_size    = 0x00000000
lmb_dump_all:
 memory.cnt  = 0x1
 memory[0]      [0x4000000-0x7ffffff], 0x04000000 bytes flags: 0
 reserved.cnt  = 0x1
 reserved[0]    [0x7e94b8c-0x7ffffff], 0x0016b474 bytes flags: 0
devicetree  = embed
icache      = 32 KiB
icache line = 4 Bytes
dcache      = 32 KiB
dcache line = 4 Bytes

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220829170205.1274484-4-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-09-13 11:32:48 +02:00
Ovidiu Panait
ae90d16ac7 cmd: bdinfo: introduce bdinfo_print_size() helper
Add bdinfo_print_size() helper to display size variables (such as cache
sizes) in bdinfo format. The size is printed as "xxx Bytes", "xxx KiB",
"xxx MiB", "xxx GiB", etc as needed;

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Reviewed-by: Jason Liu <jason.hui.liu@nxp.com>
Link: https://lore.kernel.org/r/20220829170205.1274484-3-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-09-13 11:32:48 +02:00
Ovidiu Panait
3f351cd358 cpu: microblaze: add error handling in microblaze_cpu_get_desc()
Check snprintf() return value for errors.

Make microblaze_cpu_get_desc() directly return snprintf() error code if
ret < 0. Otherwise, if the return value is greater than or equal to size,
the resulting string is truncated, so return -ENOSPC.

Fixes: 816226d27e ("cpu: add CPU driver for microblaze")
Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220829170205.1274484-2-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-09-13 11:32:48 +02:00
Ovidiu Panait
3a6948ce71 microblaze: drop CONFIG_SYS_INIT_RAM_ADDR and CONFIG_SYS_INIT_RAM_SIZE
These macros are not used anymore in microblaze code since commit
f113d7d303 ("Convert CONFIG_SPL_STACK to Kconfig"), so remove them.

Fixes: f113d7d303 ("Convert CONFIG_SPL_STACK to Kconfig")
Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Link: https://lore.kernel.org/r/20220829170205.1274484-1-ovpanait@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-09-13 11:32:48 +02:00
Michal Simek
bae7d37e52 net: gem: Check rate before setting it up
On QEMU setting rate for fixed clock is failing. That's why check a rate
first if the rate is the same there is no need to ask for the change.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/bc465ffd4904bfd65208b782daa06732b915db54.1661502645.git.michal.simek@amd.com
2022-09-13 11:32:48 +02:00
Michal Simek
aaf0793be3 xilinx: versal: Disable LMB for mini configurations
There shouldn't be a reason to have LMB on for these configurations.
LMB was already disabled for ZynqMP by commit 0063487a5b60 ("configs:
zynqmp: Disable LMB for mini u-boot").

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/17d1e9b50b2fd032352911f94f4f213828e0a3f7.1662460892.git.michal.simek@amd.com
2022-09-13 11:32:48 +02:00
Michal Simek
a32c3e9e4f arm64: xilinx: Move board_get_usable_ram_top() to common location
The commit ce39ee28ec ("zynqmp: Do not place u-boot to reserved memory
location") adds functionality for ZynqMP to read reserved memory node and
do not place U-Boot to reserved location. This functionality is generic
across all Xilinx SOCs that's why move it to common location to be used by
all Xilinx SOCs.

On zynq platform this is also fixing issue where U-Boot was placed to
locating which was reserved already which ends up with error message
"ERROR: reserving fdt memory region failed (addr=30000000 size=10000000
flags=4)" which is shown when bdinfo is called.

Tested on vck190, zcu102, zc706 and kc705 to cover all platforms.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/b0817807912f7c7af6a8e1cf9ee04e5ab5de5f6a.1661430188.git.michal.simek@amd.com
2022-09-13 11:32:48 +02:00
Michal Simek
be3a73c0c4 ARM: zynq: Align bss and end of u-boot image to 64bits
The main reason is that DT memory reserved code is expecting DT to be 64bit
aligned. For more information take a look at commit 5bd5ee02b2 ("xilinx:
zynqmp: Check that DT is 64bit aligned").

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/9f3688cda188d8ea0b462df2aa08a10ddcc9c149.1661938136.git.michal.simek@amd.com
2022-09-13 11:32:48 +02:00
Michal Simek
a27278f054 xilinx: Enable CMD_GREPENV/SETEXPR by default
Enable both of these commands in Xilinx SoCs to be able to use them in boot
scripts.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/1a612be7e09e9bc502f30e1f025441ccf8accba5.1661340513.git.michal.simek@amd.com
2022-09-13 11:32:48 +02:00
T Karthik Reddy
ce8808628e xilinx: Add env redund offset
ENV_OFFSET_REDUND config is by default set to 0 for flashes. Saving the env
variables is overwriting data at 0 offset, which is wrong. So add default
redund env offset for Zynq, ZynqMP, Versal and microblaze platforms.
Configured ENV_OFFSET_REDUND offsets by ENV_OFFSET + (2 * ENV_SIZE).

In case of versal, we configured ENV_OFFSET_REDUND at 0x7F00000 instead
of 0x7F80000. As BOOT_SCRIPT_OFFSET is already configured at 0x7F80000.

Added ENV_OFFSET_REDUND in Kconfig for microblaze due to dependency of
ENV_IS_IN_SPI_FLASH config.

Below table specifies platform specific env and env redund offsets.

PLAT		ENV_OFFSET	ENV_OFFSET_REDUND
----		----------	-----------------
ZYNQ		0xE0000		0xE40000
ZYNQMP		0x1E00000	0x1E80000
VERSAL		0x7F40000	0x7F00000
MICROBLAZE	0x1080000	0x10C0000

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/92656dc08f0f5a749d62b71ca6e77fe1be72e9e0.1661340204.git.michal.simek@amd.com
2022-09-13 11:32:48 +02:00
Piyush Mehta
1bff67eda7 arm64: zynqmp: add ref_clk property for REFCLKPER calculation
Added ref_clk 'ref' property for GUCTL_REFCLKPER and GFLADJ_REFCLK_FLADJ
calculation. This property configure correct value for SOF/ITP counter
and period of ref_clk.
This patch adds 'ref' property for both dwc3_0 and dwc3_1 cores.

Signed-off-by: Piyush Mehta <piyush.mehta@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/417545b948ea12a9301a5e80851f98523be2b443.1661259809.git.michal.simek@amd.com
2022-09-13 11:32:48 +02:00
Michal Simek
fd9c9f2932 arm64: zynqmp: Add missing tca6416 to zynqmp SC
Add missing tca6416 i2c gpio controller to SC dts file.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/a19c191d0dffb213d9dc8809d22728d79cf73a22.1661259623.git.michal.simek@amd.com
2022-09-13 11:32:48 +02:00
Harini Katakam
ddcc161c4e arm: dts: Add xlnx prefix to GEM compatible string
cdns,zynq/zynqmp were recentle deprecated in Linux in favour of xlnx
prefix. Add this new compatible string and retain the existing string for
compatibility with uboot drivers.

Signed-off-by: Harini Katakam <harini.katakam@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/a38b1b55132fc026cc09224dba61e42fd03b1a36.1661259558.git.michal.simek@amd.com
2022-09-13 11:32:48 +02:00
Amit Kumar Mahapatra
c8630167e0 arm64: zynqmp: Add mtd partition for secure OS storage area
Update MTD partitions of Kria device trees to allocate 128KB of QSPI
memory for secure OS. Increased "SHA256" partition size & changed
starting address of "User" partition to accommodate the new partition
"Secure OS Storage"

Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/9cc64b8c731d11439de73d0af54c65080068f00b.1661242681.git.michal.simek@amd.com
2022-09-13 11:32:48 +02:00
Michal Simek
88eaca26f6 xilinx: Define only mmc devnum not partition
The commit 53b406369e ("DFU: Check the number of arguments and argument
string strictly") added strict control over string that 0:1 partition
definition is not valid anymore that's why use only device number without
partition ID. Device is specified by 2nd parameter and partition by 3rd.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/840eca944f4f2abeeb63b5d724f9ba5fe9a9213b.1660055571.git.michal.simek@amd.com
2022-09-13 11:32:48 +02:00
Michal Simek
93020aa3dc xilinx: zynq: Use CONFIG_SPL_FS_LOAD_PAYLOAD_NAME for dfu_alt_info
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME stores the name of firmware file to be
loaded by SPL. Name can be selected via Kconfig that's why use the macro.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/601fbc2dfd16b4708fc6b5f86954e10add43334e.1660055571.git.michal.simek@amd.com
2022-09-13 11:32:48 +02:00
Michal Simek
ce183fd79c xilinx: Fix logic when dfu_alt_info is generated
Generate dfu_alt_info only when it is not defined.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/464e4b325c644e52a660df9cf44eeb4d80427f6a.1660055571.git.michal.simek@amd.com
2022-09-13 11:32:48 +02:00
Michal Simek
79f0151389 xilinx: zynq: Enable mkeficapsule tools compilation
Zynq can use efi capsule infrastructure that's why enable it by default.
For capsule generation for zynq you can use:

pushd spl
../tools/mkeficapsule -g "1ba29a15-9969-40aa-b424-e86121618664" boot.bin \
--index 1 ../capsule1.bin
popd
./tools/mkeficapsule -g "1a5178f0-87d3-4f36-ac63-3b31a23be305" u-boot.img \
--index 2 capsule2.bin

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/a8194ecfa7932f2d8ada5ee508b2a026c782f15e.1660055571.git.michal.simek@amd.com
2022-09-13 11:32:48 +02:00
Ashok Reddy Soma
64c71d1c73 xilinx: versal: Define CONFIG_CQSPI_REF_CLK
With commit 55b3ba4c2b ("spi: cadence_qspi: Migrate CONFIG_CQSPI_REF_CLK
to Kconfig") CONFIG_CQSPI_REF_CLK is moved to Kconfig.

The static value via Kconfig is a fallback option in case of clock
framework is not enabled or fails for some reason.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/fe7c38a19e878c307d5b75311bbfd8cf6c1f601e.1659691195.git.michal.simek@amd.com
2022-09-13 11:32:48 +02:00
Ashok Reddy Soma
4a72f80368 xilinx: versal: Enable power domain driver
Enable power domain driver to request node for all the IP's that are
enabled in DT.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/dbed54df622d647b8d520d8ce5289cd69ba66e0b.1659691195.git.michal.simek@amd.com
2022-09-13 11:32:48 +02:00
Ashok Reddy Soma
ad8024e040 firmware: zynqmp: Skip loading config object for Versal
SET_CONFIGURATION is not yet implemented for Versal platforms. Skip
loading config object for Versal until support is added.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/eb7ef6c6de36a1f7d056de43042f96fe3639f18e.1659691195.git.michal.simek@amd.com
2022-09-13 11:32:48 +02:00
Simon Glass
d1962ac797 Makefile: Add a pcheck option to run tests in parallel
Running tests in parallel is much faster, e.g. 15 seconds to run the tests
on sandbox (only), instead of 100 seconds (on a 16-core machine). Add a
'make pcheck' option to access this feature.

Note that the tools/ tests still run each tool's tests once after the
other, although within that, they do run in parallel. So for example,
the buildman tests run in parallel, then the binman tests run in
parallel. There would be a signiificant advantage to running them all
in parallel together, but that would require a large amount of
refactoring, e.g. with more use of pytest fixtures.

Update the documentation to represent the current state.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-12 18:06:36 -04:00
Simon Glass
e1c0811114 dtoc: Drop sys.exit() in test_fdt
This breaks using pytest to run the tests. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-12 18:06:36 -04:00
Simon Glass
45a226a16b test/py: Support --build when running tests in parallel
At present when -n is used, all workers try to build U-Boot at once.
Add a lock to ensure that only one of them builds, with the others using
the build that is produced.

The lock file is removed on startup.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-12 18:06:36 -04:00
Simon Glass
486680272e test/py: Move U-Boot building into a function
This is a lot of code in a function that is too long. Split out the
building code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-12 18:06:36 -04:00
Simon Glass
f6e6022ff1 test: Refactor arg parsing for the run script
Tidy up this code a little. Also use '-k' consistently, since -m is more
limited in what it can accept.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-12 18:06:36 -04:00
Simon Glass
b681669aa5 test: Make test_gpio_read() independent
This assumes that the GPIO starts as 0 but it does not if
test_gpio_input() ran first and test_gpio_exit_statuses() was skipped.
This can happen when running tests in parallel.

Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-12 18:06:36 -04:00
Simon Glass
d401187fec test: Mark test_gpt tests as slow
Mark all the tests in this file as slow, since they take a while.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-12 18:06:36 -04:00
Simon Glass
c7c113dc13 test: Mark all but the first vboot test as slow
When doing a quick check we don't need to run all the vboot tests. Just
run the first one, which is enough to catch most problems.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-12 18:06:36 -04:00
Simon Glass
a1f620eb4f test: Make test_efi_bootmgr() single-threaded
This test seems to fail when run in parallel. Mark it single-threaded to
avoid any problems.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-12 18:06:36 -04:00
Simon Glass
e2c5113523 test: Make test_sqfs_ls() single-threaded
This test seems to interfere with the other test in this file. Mark it
single-threaded to avoid any problems.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-12 18:06:36 -04:00
Simon Glass
c620ea45a7 test: Update FIT tests to run in parallel
Use a different temporary dir for each test, to allow them to run in
parallel.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-12 18:06:36 -04:00
Simon Glass
78ac0deafd test: Make test_bind_unbind_with_uclass() single-threaded
This test seems to rely on the other test in this file. Mark it
single-threaded to avoid any problems.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-12 18:06:36 -04:00
Simon Glass
cc85d905cd test/py: Allow tests to be marked single-threaded only
Add a new 'singlethread' marker to allow tests to be skipped when running
in parallel.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-12 18:06:36 -04:00
Simon Glass
44384c70f9 test: Fix bootm_test_subst_var() running independently
This test relies on the silent_linux env variable being set. Add this
to the code so it can run without relying on other bootm tests having been
run first.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-12 18:06:36 -04:00
Simon Glass
2aa1188467 test: Fix test_pinmux to run in parallel
At present test_pinmux_status() assumes that test_pinmux_dev() has run
beforehand. Drop this assumption so we can run the tests in parallel.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-09-12 18:06:36 -04:00
Michal Simek
91687c4c3c xilinx: zynq: Disable LMB for mini configurations
There shouldn't be a reason to have LMB on for these configurations.
LMB was already disabled for ZynqMP by commit 0063487a5b60 ("configs:
zynqmp: Disable LMB for mini u-boot").

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/07d95f619a15672d1a234eddcfbb54c0ab382eaa.1662460867.git.michal.simek@amd.com
2022-09-12 12:05:06 +02:00
Ashok Reddy Soma
d434921def xilinx: zynqmp: Disable LMB for mini u-boot
LMB is not required for mini u-boot which runs out of on chip memory.
Disable CONFIG_LMB from mini u-boot defconfig's.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/45fad28825f0f236ad45e700aca1f39afbb22236.1659691195.git.michal.simek@amd.com
2022-09-12 12:05:06 +02:00
Michal Simek
85007da94b cmd: bdinfo: Enable dumping lmb data when LMB is enabled
The commit 9996cea75f ("lmb/bdinfo: dump lmb info via bdinfo") added
support for dumping LMB information as the part of bdinfo. But code itself
should be called only when LMB is enabled.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/3e40c8bb77550dfca9f7eb48fe644a018d971411.1662537127.git.michal.simek@amd.com
2022-09-12 12:05:06 +02:00
Ashok Reddy Soma
2fb4b5ae54 xilinx: zynqmp: Disable various configs for mini U-Boot
With 2022.01-rc3 upgrade, the size of the mini U-Boot increased and is
not able to fit in OCM. Hence disable unnecessary configs and make room.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/306b57818601fa3571bc75c4182f25aaa3f2a793.1659691195.git.michal.simek@amd.com
2022-09-12 12:03:17 +02:00
Michal Simek
86cba52a98 xilinx: versal: Enable i2c mux uclass with pca954x driver
Xilinx is using pca954x i2c muxes on a lot of boards that's why enable this
driver by default.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c090aea3436c7a4ebe698da6cbc70e70a14baae3.1659691195.git.michal.simek@amd.com
2022-09-12 12:03:17 +02:00
Janne Ylalehto
cf5c48d102 xilinx: zynqmp: Fix AES with a user provided key
The user provided key address was not flushed in struct aes because of
the flushing location in the function.

Signed-off-by: Janne Ylalehto <ylalehto@gmail.com>
Link: https://lore.kernel.org/r/20220816124525.19671-1-ylalehto@gmail.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2022-09-12 12:03:17 +02:00