Also drop a few files referring to no longer / not yet supported
boards.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Kim Phillips <kim.phillips@freescale.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Jason Jin <jason.jin@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Most 85xx boards can be built as a 32-bit or a 36-bit. Current code sometimes
displays which of these is actually built, but it's inconsistent. This is
especially problematic since the "default" build for a given 85xx board can
be either one, so if you don't see a message, you can't always know which
size is being used. Not only that, but each board includes code that displays
the message, so there is duplication.
The 'bdinfo' command has been updated to display this information, so
we don't need to display it at boot time. The board-specific code is
deleted.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
The top level Makefile does not do any recursion into subdirs when
cleaning, so these clean/distclean targets in random arch/board dirs
never get used. Punt them all.
MAKEALL didn't report any errors related to this that I could see.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
It is not necessary to keep multiple entries for the same setting in DDR
speed tables. Merge them for smaller tables. Also restructure the tables
for smaller size. Cleanup some typedefs.
Enforce strict checking for speed table. If DIMM is running at higher than
known speed, try to use the highest speed setting. If rank is unknown, it
has to panic.
Removed ODT overriding for P2020DS as it is not necessary.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Current code would print RAM size information like this:
DRAM: DDR: 256 MiB (DDR1, 64-bit, CL=2, ECC off)
Turn a number of printf()s into debug() to get rid of the redundant
"DDR: " string like this:
DRAM: 256 MiB (DDR1, 64-bit, CL=2, ECC off)
Signed-off-by: Wolfgang Denk <wd@denx.de>
Acked-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
If DDR initialziation uses a speed table and the speed is not matched,
print a warning message instead of silently ignoring.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Remove an empty board_early_init_f() from the MPC8641HPCN board.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Move fsl_ddr_get_spd into common mpc8xxx/ddr/main.c as most boards
pretty much do the same thing. The only variations are in how many
controllers or DIMMs per controller exist. To make this work we
standardize on the names of the SPD_EEPROM_ADDRESS defines based on the
use case of the board.
We allow boards to override get_spd to either do board specific fixups
to the SPD data or deal with any unique behavior of how the SPD eeproms
are wired up.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Every 85xx board implements fsl_ddr_get_mem_data_rate via get_ddr_freq()
and every 86xx board uses get_bus_freq(). If implement get_ddr_freq()
as a static inline to call get_bus_freq() we can remove
fsl_ddr_get_mem_data_rate altogether and just call get_ddr_freq()
directly.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We've been utilizing board_lmb_reserve to reserve the boot page for MP
systems. We can just move this into arch_lmb_reserve for 85xx & 86xx
systems rather than duplicating in each board port.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Remove duplicated code in MPC8641HPCN board and utilize the common
fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI
controllers based on which PCIe controllers are enabled.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Now that we have serdes support for all 85xx/86xx/Pxxx chips we can
replace the is_fsl_pci_cfg() code with the is_serdes_configured().
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Since board_hwconfig & cpu_hwconfig are defined as weak and dont have a
default value they will get put into the BSS if they aren't defined
elsewhere. This is problematic as we try to utilize hwconfig before
we've relocated and thus BSS isn't setup.
Instead of giving dummy values in the board files that utilize this
feature, we can just initialize the variables to an empty string and
thus move them out of the BSS if they aren't defined elsewhere.
Also made board_hwconfig & cpu_hwconfig arrays to reduce size associated
with string pointers vs arrays.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Before this commit, weak symbols were not overridden by non-weak symbols
found in archive libraries when linking with recent versions of
binutils. As stated in the System V ABI, "the link editor does not
extract archive members to resolve undefined weak symbols".
This commit changes all Makefiles to use partial linking (ld -r) instead
of creating library archives, which forces all symbols to participate in
linking, allowing non-weak symbols to override weak symbols as intended.
This approach is also used by Linux, from which the gmake function
cmd_link_o_target (defined in config.mk and used in all Makefiles) is
inspired.
The name of each former library archive is preserved except for
extensions which change from ".a" to ".o". This commit updates
references accordingly where needed, in particular in some linker
scripts.
This commit reveals board configurations that exclude some features but
include source files that depend these disabled features in the build,
resulting in undefined symbols. Known such cases include:
- disabling CMD_NET but not CMD_NFS;
- enabling CONFIG_OF_LIBFDT but not CONFIG_QE.
Signed-off-by: Sebastien Carlier <sebastien.carlier@gmail.com>
Update to use the recent, common FSL PCI initialization code.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Clean up Makefile, and drop a lot of the config.mk files on the way.
We now also automatically pick all boards that are listed in
boards.cfg (and with all configurations), so we can drop the redundant
entries from MAKEALL to avoid building these twice.
Signed-off-by: Wolfgang Denk <wd@denx.de>
The change is currently needed to be able to remove the board
configuration scripting from the top level Makefile and replace it by
a simple, table driven script.
Moving this configuration setting into the "CONFIG_*" name space is
also desirable because it is needed if we ever should move forward to
a Kconfig driven configuration system.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Verified on MPC8641HPCN with four DDR2 dimms. Each dimm has dual
rank with 512MB each rank.
Also check dimm size and rank size for memory controller interleaving
Signed-off-by: York Sun <yorksun@freescale.com>
Previously we used an alias the pci node to determine which node to
fixup or delete. Now we use the new fdt_node_offset_by_compat_reg to
find the node to update.
Additionally, we replace the code in each board with a single macro call
that makes assumes uniform naming and reduces duplication in this area.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The MPC8641 boards actually only have PCIE not PCI. Rename so we are
uniform with regards to names so we can replace this code with templated
code.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Remove dupliacted setting of PCI/PCIe address and offsets in board
config.h. Renamed CONFIG_SYS_PCI1/2_ADDR to CONFIG_SYS_PCI1/2ADDR on
MPC8641 boards since its really PCIE controllers and not PCI.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
As discussed on the list, move "arch/ppc" to "arch/powerpc" to
better match the Linux directory structure.
Please note that this patch also changes the "ppc" target in
MAKEALL to "powerpc" to match this new infrastructure. But "ppc"
is kept as an alias for now, to not break compatibility with
scripts using this name.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Wolfgang Denk <wd@denx.de>
Acked-by: Detlev Zundel <dzu@denx.de>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Cc: Peter Tyser <ptyser@xes-inc.com>
Cc: Anatolij Gustschin <agust@denx.de>
Now that the other architecture-specific lib directories have been
moved out of the top-level directory there's not much reason to have the
'_generic' suffix on the common lib directory.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Also move lib_$ARCH/config.mk to arch/$ARCH/config.mk
This change is intended to clean up the top-level directory structure
and more closely mimic Linux's directory organization.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Refactor and document the Freescale PIXIS code, used on most 85xx and 86xx
boards. This makes the code easier to read and more flexible.
Delete pixis.h, because none of the exported functions were actually being
used by any other file. Make all of the functions in pixis.c 'static'.
Remove "#include pixis.h" from every file that has it.
Remove some unnecessary #includes.
Make 'pixis_base' into a macro, so that we don't need to define it in every
function.
Add "while(1);" loops at the end of functions that reset the board, so that
execution doesn't continue while the reset is in progress.
Replace in_8/out_8 calls with clrbits_8, setbits_8, or clrsetbits_8, where
appropriate.
Replace ulong/uint with their spelled-out equivalents. Remove unnecessary
typecasts, changing the types of some variables if necessary.
Add CONFIG_SYS_PIXIS_VCFGEN0_ENABLE and CONFIG_SYS_PIXIS_VBOOT_ENABLE to make
it easier for specific boards to support variations in the PIXIS registers
sets. No current boards appears to need this feature.
Fix the definition of CONFIG_SYS_PIXIS_VBOOT_MASK for the MPC8610 HPCD.
Apparently, "pixis_reset altbank" has never worked on this board.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
After determining how much DDR is actually in the system, set DBAT0 and
IBAT0 accordingly. This ensures that the CPU won't attempt to access
(via speculation) addresses outside of actual memory.
On 86xx systems, DBAT0 and IBAT0 (the BATs for DDR) are initialized to 2GB
and kept that way. If the system has less than 2GB of memory (typical for
an MPC8610 HPCD), the CPU may attempt to access this memory during
speculation. The zlib code is notorious for generating such memory reads,
and indeed on the MPC8610, uncompressing the Linux kernel causes a machine
check (without this patch).
Currently we are limited to power of two sized DDR since we only use a
single bat. If a non-power of two size is used that is less than
CONFIG_MAX_MEM_MAPPED u-boot will crash.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The same code exists both inside an #ifdef and outside of it.
Remove the extra code for all the 86xx boards.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The following changes allow U-Boot to fully relocate from flash to
RAM:
- Remove linker scripts' .fixup sections from the .text section
- Add -mrelocatable to PLATFORM_RELFLAGS for all boards
- Define CONFIG_RELOC_FIXUP_WORKS for all boards
Previously, U-Boot would partially relocate, but statically initialized
pointers needed to be manually relocated.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Refactor the code into a simple bitmask lookup table that determines if
a given PCI controller is enabled and if its in host/root-complex or
agent/end-point mode.
Each processor in the PQ3/MPC86xx family specified different encodings
for the cfg_host_agt[] and cfg_IO_ports[] boot strapping signals.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
For historic reasons we had defined some additional PLATFORM_CPPFLAGS like:
PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1
PLATFORM_CPPFLAGS += -DCONFIG_MPC8641=1
However these are all captured in the config.h and thus redudant. Also
moved common 86xx flags into cpu/mpc86xx/config.mk.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Every platform that calls fsl_pci_init calls fsl_pci_setup_inbound_windows
before it calls fsl_pci_init. There isn't any reason to just call it
from fsl_pci_init and simplify things a bit.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Every platform that calls fsl_pci_init calls pci_setup_indirect before
it calls fsl_pci_init. There isn't any reason to just call it from
fsl_pci_init and simplify things a bit.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Rename sdram_mode_1 to sdram_mode and sdram_cfg_1 to sdram_cfg to match
the 86xx user's manual and other Freescale architectures
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The MPC8641HPCN board is capable of swizzling the upper address bit of
the NOR flash we boot out of which creates the concept of "virtual"
banks. This is useful in that we can flash a test of image of u-boot
and reset to one of the virtual banks while still maintaining a
working image in "bank 0".
The PIXIS FPGA exposes registers on LBC which we can use to determine
which "bank" we are booting out of (as well as setting which bank to
boot out of).
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Rename the pci header for FSL HW so we can move some prototypes
in there and stop doing explicit externs
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Use CONFIG_MP instead of CONFIG_NUM_CPUS to match 85xx
* Introduce determine_mp_bootpg() helper. We'll need this to address a
bug introduced in v2009.03 with 86xx MP booting. We have to make sure
to reserve the region of memory used for the MP bootpg() so other
u-boot code doesn't use it.
* Added dummy versions of cpu_reset(), cpu_status() & cpu_release() to
allow cmd_mp.c to build and work. In the future we should look at
implementing all these functions. This could be common w/85xx if we
use spin tables on 86xx.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We're missing the board_lmb_reserve definitions that allow
cpu_mp_lmb_reserve to be called; this means that Linux
is free to reallocate reserved pages. Linux currently boots
because we're getting lucky - the page we've reserved is
high enough in memory that it isn't allocated by Linux
while we still need it to be in existence.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
A recent gcc added a new unaligned rodata section called '.rodata.str1.1',
which needs to be added the the linker script. Instead of just adding this
one section, we use a wildcard ".rodata*" to get all rodata linker section
gcc has now and might add in the future.
However, '*(.rodata*)' by itself will result in sub-optimal section
ordering. The sections will be sorted by object file, which causes extra
padding between the unaligned rodata.str.1.1 of one object file and the
aligned rodata of the next object file. This is easy to fix by using the
SORT_BY_ALIGNMENT command.
This patch has not be tested one most of the boards modified. Some boards
have a linker script that looks something like this:
*(.text)
. = ALIGN(16);
*(.rodata)
*(.rodata.str1.4)
*(.eh_frame)
I change this to:
*(.text)
. = ALIGN(16);
*(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
This means the start of rodata will no longer be 16 bytes aligned.
However, the boundary between text and rodata/eh_frame is still aligned to
16 bytes, which is what I think the real purpose of the ALIGN call is.
Signed-off-by: Trent Piepho <xyzzy@speakeasy.org>
Update the 86xx reset sequence to try executing a board-specific reset
function. If the board-specific reset is not implemented or does not
succeed, then assert #HRESET_REQ. Using #HRESET_REQ is a more standard
reset procedure than the previous method and allows all board
peripherals to be reset if needed.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Clean up PCI mapping concepts in the 8641 config - rename _BASE
to _BUS, as it's actually a PCI bus address, separate virtual
and physical addresses into _VIRT and _PHYS, and use each
appopriately.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Because the inbound pci windows are mapped generously, set up
the more specific outbound windows first. This way, when we
search the pci regions for something, we will hit on the more
specific region. This can actually be a problem on systems
with large amounts of RAM.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
For light loaded system, we use the 1T timing to gain better
memory performance, but for some heavily loaded system,
you have to add the 2T timing options to board files.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Acked-by: Andy Fleming <afleming@freescale.com>
