u-boot/board/freescale/mpc8641hpcn
Peter Tyser 8ca78f2c89 fsl: Clean up printing of PCI boot info
Previously boards used a variety of indentations, newline styles, and
colon styles for the PCI information that is printed on bootup.  This
patch unifies the style to look like:

...
NAND:  1024 MiB
PCIE1: connected as Root Complex
           Scanning PCI bus 01
        04  01  8086  1010  0200  00
        04  01  8086  1010  0200  00
        03  00  10b5  8112  0604  00
        02  01  10b5  8518  0604  00
        02  02  10b5  8518  0604  00
        08  00  1957  0040  0b20  00
        07  00  10b5  8518  0604  00
        09  00  10b5  8112  0604  00
        07  01  10b5  8518  0604  00
        07  02  10b5  8518  0604  00
        06  00  10b5  8518  0604  00
        02  03  10b5  8518  0604  00
        01  00  10b5  8518  0604  00
PCIE1: Bus 00 - 0b
PCIE2: connected as Root Complex
           Scanning PCI bus 0d
        0d  00  1957  0040  0b20  00
PCIE2: Bus 0c - 0d
In:    serial
...

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
CC: wd@denx.de
CC: sr@denx.de
CC: galak@kernel.crashing.org
2010-11-14 23:46:42 +01:00
..
ddr.c fsl-ddr: use the 1T timing as default configuration 2009-01-23 17:03:14 -06:00
law.c powerpc/86xx: Rename PCI1/2 to PCIE1/2 on MPC8641HPCN & SBC8641 2010-07-20 04:37:11 -05:00
Makefile FSL DDR: Convert MPC8641HPCN to new DDR code. 2008-08-27 02:06:02 +02:00
mpc8641hpcn.c fsl: Clean up printing of PCI boot info 2010-11-14 23:46:42 +01:00