Commit graph

25115 commits

Author SHA1 Message Date
Marc Zyngier
64fd44dcae ARM: non-sec: reset CNTVOFF to zero
Before switching to non-secure, make sure that CNTVOFF is set
to zero on all CPUs. Otherwise, kernel running in non-secure
without HYP enabled (hence using virtual timers) may observe
timers that are not synchronized, effectively seeing time
going backward...

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-28 17:06:28 +02:00
Marc Zyngier
800c83522c ARM: HYP/non-sec: add a barrier after setting SCR.NS==1
A CP15 instruction execution can be reordered, requiring an
isb to be sure it is executed in program order.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-28 17:06:19 +02:00
Marc Zyngier
c19e0dd741 ARM: HYP/non-sec: move switch to non-sec to the last boot phase
Having the switch to non-secure in the "prep" phase is causing
all kind of troubles, as that stage can be called multiple times.

Instead, move the switch to non-secure to the last possible phase,
when there is no turning back anymore.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
2014-07-28 17:05:59 +02:00
Albert ARIBAUD
b1cdd8baa1 Merge branch 'u-boot-ti/master' into 'u-boot-arm/master' 2014-07-28 12:26:21 +02:00
Albert ARIBAUD
48b3ed217f Merge branch 'u-boot-sh/rmobile' into 'u-boot-arm/master' 2014-07-28 10:54:54 +02:00
Albert ARIBAUD
740f41d3cb Merge branch 'u-boot-sunxi/master' into 'u-boot-arm/master' 2014-07-28 10:12:45 +02:00
Masahiro Yamada
ee860c60d2 patman: make "No recipient" checking more tolerant
If Series-to tag is missing, Patman exits with a message
"No recipient".

This is just annoying for those who had already added
sendemail.to configuration.

I guess many developers have

  [sendemail]
          to = u-boot@lists.denx.de

in their .git/config because the 'To: u-boot@lists.denx.de' field
should always be added when sending patches.

That seems more reasonable rather than adding
'Series-to: u-boot@lists.denx.de' to every patch series.

Patman should exit only when both Series-to tag and sendemail.to
configuration are mising.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
2014-07-28 04:57:24 +01:00
Simon Glass
189a496825 buildman: Support in-tree builds
At present buildman always builds out-of-tree, that is it uses a separate
output directory from the source directory. Normally this is what you want,
but it is important that in-tree builds work also. Some Makefile changes may
break this.

Add a -i option to tell buildman to use in-tree builds, so that it is easy
to test this feature.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-28 04:52:55 +01:00
Simon Glass
97e915262e buildman: Add -C option to force a reconfigure for each commit
Normally buildman wil try to configure U-Boot for a particular board on the
first commit that it builds in a series. Subsequent commits are built
without reconfiguring which normally works. Where it doesn't, buildman
automatically reconfigures and retries.

To fully emulate the way MAKEALL works, we should have an option to disable
this optimisation.

Add a -C option to cause buildman to always reconfigure on each commit.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-07-28 04:52:48 +01:00
Albert ARIBAUD
f2c8d7f591 Merge branch 'u-boot-microblaze/zynq' into 'u-boot-arm/master' 2014-07-26 14:08:36 +02:00
pekon gupta
434f2cfcad ARM: omap: move board specific NAND configs out from ti_armv7_common.h
This patch moves some board specific NAND configs:
- FROM: generic config file 'ti_armv7_common.h'
- TO:   individual board config files using these configs.
So that each board can independently set the value as per its design.

Following configs are affected in this patch:
  CONFIG_SYS_NAND_U_BOOT_OFFS: <refer doc/README.nand>
  CONFIG_CMD_SPL_NAND_OFS: <refer doc/README.falcon>
  CONFIG_SYS_NAND_SPL_KERNEL_OFFS: <refer doc/README.falcon>
  CONFIG_CMD_SPL_WRITE_SIZE: <refer doc/README.falcon>

This patch also updates documentation for few of above NAND configs.

Signed-off-by: Pekon Gupta <pekon@ti.com>
2014-07-25 16:26:12 -04:00
pekon gupta
222a3113b4 ARM: omap: clean redundant PISMO_xx macros used in OMAP3
PISMO_xx macros were used to define 'Platform Independent Storage MOdule'
related GPMC configurations. This patch
- Replaces these OMAP3 specific macros with generic CONFIG_xx macros as provided
  by current u-boot infrastructure.
- Removes unused redundant macros, which are no longer required after
  merging of common platform code in following commit
      commit a0a37183bd
      ARM: omap: merge GPMC initialization code for all platform

+-----------------+-----------------------------------------------------------+
| Macro           | Reason for removal                                        |
+-----------------+-----------------------------------------------------------+
| PISMO1_NOR_BASE | duplicate of CONFIG_SYS_FLASH_BASE                        |
+-----------------+-----------------------------------------------------------+
| PISMO1_NAND_BASE| duplicate of CONFIG_SYS_NAND_BASE                         |
+-----------------+-----------------------------------------------------------+
| PISMO1_ONEN_BASE| duplicate of CONFIG_SYS_ONENAND_BASE                      |
+-----------------+-----------------------------------------------------------+
| PISMO1_NAND_SIZE| GPMC accesses NAND device via I/O mapped registers so     |
|                 | configuring GPMC chip-select for smallest allowable       |
|                 | segment (GPMC_SIZE_16M) is enough.                        |
+-----------------+-----------------------------------------------------------+
| PISMO1_ONEN_SIZE| OneNAND uses a fixed GPMC chip-select address-space of    |
|                 | 128MB (GPMC_SIZE_128M)                                    |
+-----------------+-----------------------------------------------------------+
+-----------------+-----------------------------------------------------------+
| PISMO1_NOR      |  Unused Macros                                            |
| PISMO1_NAND     |                                                           |
| PISMO2_CS0      |                                                           |
| PISMO2_CS1      |                                                           |
| PISMO1_ONENAND  |                                                           |
| PISMO2_NAND_CS0 |                                                           |
| PISMO2_NAND_CS1 |                                                           |
| PISMO1_NOR_BASE |                                                           |
| PISMO1_NAND_BASE|                                                           |
| PISMO2_CS0_BASE |                                                           |
+-----------------+-----------------------------------------------------------+

Signed-off-by: Pekon Gupta <pekon@ti.com>
2014-07-25 16:26:12 -04:00
pekon gupta
77cd89e755 ARM: omap: fix GPMC address-map size for NAND and NOR devices
Fixes commit a0a37183bd
    ARM: omap: merge GPMC initialization code for all platform

1) NAND device are not directly memory-mapped to CPU address-space, they are
 indirectly accessed via following GPMC registers:
 - GPMC_NAND_COMMAND_x
 - GPMC_NAND_ADDRESS_x
 - GPMC_NAND_DATA_x
 Therefore from CPU's point of view, NAND address-map can be limited to just
 above register addresses. But GPMC chip-select address-map can be configured
 in granularity of 16MB only.
 So this patch uses GPMC_SIZE_16M for all NAND devices.

2) NOR device are directly memory-mapped to CPU address-space, so its
 address-map size depends on actual addressable region in NOR FLASH device.
 So this patch uses CONFIG_SYS_FLASH_SIZE to derive GPMC chip-select address-map
 size configuration.

Signed-off-by: Pekon Gupta <pekon@ti.com>
2014-07-25 16:26:12 -04:00
Rajendra Nayak
8c16dd6fa7 ARM: OMAP: Fix handling of errata i727
The errata is applicable on all OMAP4 (4430 and 4460/4470) and OMAP5
ES 1.0 devices. The current revision check erroneously implements this
on all DRA7 varients and with DRA722 device (which has only 1 EMIF instance)
infact causes an asynchronous abort and ends up masking it in CPSR,
only to be uncovered once the kernel switches to userspace.

Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Sricharan R <r.sricharan@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2014-07-25 16:26:11 -04:00
Hao Zhang
a906847966 board: k2e-evm: add board support
This patch adds Keystone2 k2e_evm evaluation board support.

Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:11 -04:00
Khoronzhuk, Ivan
1284246eb9 ARM: keystone2: spl: add K2E SoC support
Keystone2 K2E SoC has slightly different spl pll settings then
K2HK, so correct this.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:11 -04:00
Khoronzhuk, Ivan
7c38764606 keystone2: use CONFIG_SOC_KEYSTONE in common places
Use CONFIG_SOC_KEYSTONE in common places instead of defining
a lot of "if def .. || if def " for different Keystone2 SoC types.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:11 -04:00
Hao Zhang
20187fd11c ARM: keystone2: add MSMC cache coherency support for K2E SOC
This patch adds Keystone2 K2E SOC specific code to support
MSMC cache coherency. Also create header file for msmc to hold
its API.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:11 -04:00
Hao Zhang
4dca7f0acc ARM: keystone2: clock: add K2E clock support
This patch adds clock definitions and commands to support Keystone2
K2E SOC.

Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:11 -04:00
Hao Zhang
5c76f78858 ARM: keystone2: add K2E SoC hardware definitions
This patch adds hardware definitions specific to Keystone II
K2E device. It has a lot common definitions with k2hk SoC, so
move them to common hardware.h. This is preparation patch for
adding K2E SoC support.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:11 -04:00
Hao Zhang
b1babef856 keystone: ddr3: move K2HK DDR3 configuration to a common file
It's convenient to hold configurations for DDR3 PHY and EMIF in
separate common place. This patch moves K2HK DDR3 PHY and EMIF
configuration data with different rates and memory size to a common
ddr3_cfg.c file.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:11 -04:00
Hao Zhang
2221cd12cd configs: k2hk_evm: config: add common EVM configuration header
This patch adds a common config header file for all the Keystone II
EVM platforms. It combines a lot of general definitions in one file.
The common header included in the EVM should be specific configuration
header.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:10 -04:00
Khoronzhuk, Ivan
8dfc15f56c ARM: keystone: clock: move K2HK SoC dependent code in separate file
This patch in general spit SoC type clock dependent code and general
clock code. Before adding keystone II Edison k2e SoC which has
slightly different dpll set, move k2hk dependent clock code to
separate clock-k2hk.c file.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:10 -04:00
Hao Zhang
e595107ebb ARM: keystone2: move K2HK board files to common KS2 board directory
This patch moves K2HK board directory to a common Keystone II board
directory. The Board related common functions are moved to a common
keystone board file.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:10 -04:00
Murali Karicheri
0bedbb8135 keystone2: add env option to do unitrd dt fixup
With latest v3.13 kernel, unitrd dt fixup is not needed. However for
older kernel versions such as v3.8/v3.10, it is needed. So to work
with both, add a u-boot env variable that can be set to do dt fixup
for older kernels.

Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:10 -04:00
Khoronzhuk, Ivan
3d31538625 k2hk: use common KS2_ prefix for all hardware definitions
Use KS2_ prefix in all definitions, for that replace K2HK_ prefix and
add KS2_ prefix where it's needed. It requires to change names also
in places where they're used. Align lines and remove redundant
definitions in kardware-k2hk.h at the same time.

Using common KS2_ prefix helps resolve redundant redefinitions and
adds opportunity to use KS2_ definition across a project not thinking about
what SoC should be used. It's more convenient and we don't need to worry
about the SoC type in common files, hardware.h will think about that.
The hardware.h decides definitions of what SoC to use.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:10 -04:00
Hao Zhang
7b26c1f608 keystone2: add possibility to turn off all dsps
By default all DSPs are turned off, for another case option
to turn off them is added in this commit.
Also add command to turn off itself.

Acked-by: Murali Karicheri <m-maricheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:10 -04:00
Hao Zhang
4984bce41f keystone2: move cpu_to_bus() to keystone.c
The SoC related common functions in board.c should be placed to
a common keystone.c arch file.

Acked-by: Murali Karicheri <m-maricheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:10 -04:00
Khoronzhuk, Ivan
35c547c2bc ARM: keystone2: keystone_nav: make it dependent on keystone driver
This driver is needed in case if keystone driver is used.
Currently only keystone_net driver uses it. So to avoid
redundant code compilation make the keystone_nav dependent
on keystone net driver. It also leads to compilation errors
for boards that does't use it.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:09 -04:00
Hao Zhang
101eec50f0 keystone2: ddr: add DDR3 PHY configs updated for PG 2.0
Add DDR3 PHY configs updated for PG 2.0
Also add DDR3A PHY reset before init for PG2.0 SoCs.

Acked-by: Murali Karicheri <m-maricheri2@ti.com>
Signed-off-by: Hao Zhang <hzhang@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:09 -04:00
Khoronzhuk, Ivan
0b86858956 keystone: ddr3: add ddr3.h to hold ddr3 API
It's convinient to hold ddr3 function definitions in separate file
such as ddr3.h. So move this from hardware.h to ddr3.h.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:09 -04:00
Khoronzhuk, Ivan
04b7ce0773 ARM: keystone2: psc: use common PSC base
Use common keystone2 Power Sleep controller base address instead of
directly deciding which keystone2 SoC is used in psc module.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 16:26:09 -04:00
Stefan Roese
188948e884 ARM: omap: tao3530: Convert to generic board
Use generic board setup functions by defining
CONFIG_SYS_GENERIC_BOARD.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@ti.com>
2014-07-25 16:26:09 -04:00
Stefan Roese
6d3bbdb0e7 ARM: omap: Remove unused arch/arm/cpu/armv7/omap3/mem.c
These functions have been merged into the common GPMC init code
with this commit a0a37183 (ARM: omap: merge GPMC initialization code
for all platform). The file is not compiled any more. So remove it
as well.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pekon Gupta <pekon@ti.com>
Cc: Tom Rini <trini@ti.com>
Acked-by: Pekon Gupta <pekon@ti.com>
2014-07-25 16:26:09 -04:00
Stefan Roese
fb2fcb798a ARM: omap: Fix GPMC init for OMAP3 platforms
Commit a0a37183 (ARM: omap: merge GPMC initialization code for all
platform) broke NAND on OMAP3 based platforms. I noticed this while
testing the latest 2014.07-rc version on the TAO3530 board. NAND
detection did not work with this error message:

NAND:  nand: error: Unable to find NAND settings in GPMC Configuration - quitting

As OMAP3 configs don't set CONFIG_NAND but CONFIG_NAND_CMD. the GPMC
was not initialized for NAND at all. This patch now fixes this issue.

Tested on TAO3530 board.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Pekon Gupta <pekon@ti.com>
Cc: Tom Rini <trini@ti.com>
Acked-by: Pekon Gupta <pekon@ti.com>
2014-07-25 16:26:09 -04:00
Andreas Bießmann
e6f9d419c8 tricorder: convert to generic board
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Thomas Weber <thomas.weber@corscience.de>
2014-07-25 16:26:08 -04:00
Tom Rini
c4f80f5003 am335x_evm / gumstix pepper: Correct DDR settings
As noted by clang, we have been shifting certain values out of 32bit
range when setting some DDR registers.  Upon further inspection these
had been touching reserved fields (and having no impact).  These came in
from historical bring-up code and can be discarded.  Similarly, we had
been declaring some fields as 0 when they will be initialized that way.
Tested on Beaglebone White.

Reported-by: Jeroen Hofstee <jeroen@myspectrum.nl>
Cc: Ash Charles <ash@gumstix.com>
Signed-off-by: Tom Rini <trini@ti.com>
Tested-By: Ash Charles <ashcharles@gmail.com>
2014-07-25 16:26:08 -04:00
Khoronzhuk, Ivan
c6ac7e3bdc k2hk_evm: add script to automate NAND flash process
Add script to automate NAND flash process. As for now the board has
two burn scripts - burn to boot from SPI NOR flash and burn to boot
from AEMIF NAND flash, rename burn_uboot script to burn_uboot_spi.
Also update README to contain NAND burn U-boot process description.

Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
Acked-by: Murali Karicheri <m-karicheri2@ti.com>
2014-07-25 15:21:06 -04:00
Khoronzhuk, Ivan
0e7f2dbac6 keystone: add support for NAND gpheader image
Add support for NAND gpheader image. TI Keystone2 ROM bootloader
expects 8 bytes of trailing zeroes in the nand u-boot image.
So add zeros at the end of the nand gph image.

Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 15:21:06 -04:00
Khoronzhuk, Ivan
67ac6ffaee mtd: nand: davinci: add opportunity to write keystone U-boot image
The Keystone SoCs use the same NAND driver as Davinci.
This patch adds opportunity to write Keystone U-boot image to NAND
device using appropriate RBL ECC layout. This is needed only if RBL
boots U-boot from NAND device and that's supposed that raw u-boot
partition is used only for writing image.

The main problem is that default Davinci ECC layout is different from
Keystone RBL layout. To read U-boot image the RBL needs that image was
written using RBL ECC layout.

The BBT table is written using default Davinci layout and has to
be updated using one. The BBT can be updated only while erasing
chip or by forced bad block assigning, so erase function has to
use native ecc layout in order to be able to write BBT correctly.
So if we're writing to NAND U-boot address we use RBL layout for
others we use default ECC layout.

Also remove definition for CONFIG_CMD_NAND_ECCLAYOUT as there is no
reasons to use ECC layout commands. It was added by mistake.

Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
2014-07-25 15:21:06 -04:00
Tom Rini
7aa5598aac tps65218/am43xx_evm: Add power framework support to TPS65218
Add in an init function for the drivers/power framework so we can dump
and read the registers via i2c.

Cc: Łukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Tom Rini <trini@ti.com>
2014-07-25 15:21:06 -04:00
Tom Rini
5c44dd6bbd power/pmic.h: Add prototype for power_init_board.
As this is a weak function that we may override, provide a prototype for
it.

Cc: Łukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Tom Rini <trini@ti.com>
2014-07-25 15:21:05 -04:00
Mugunthan V N
4c8014b942 ARM: dra7_evm: Add Ethernet support for dra72x platform
Set the active_slave to 1 as slave 1 is pinned out in dra72x base board

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2014-07-25 15:21:05 -04:00
Mugunthan V N
e5ff845bff ARM: DRA7xx: Add cpsw second port pinmux
Add cpsw second slave port pinmux to use it as primary ethernet port

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2014-07-25 15:21:05 -04:00
Mugunthan V N
7a0227534d drivers: net: cpsw: add support for using second port as ethernet
Add support for using the second slave port of cpsw
to be used as primary ethernet.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
2014-07-25 15:21:05 -04:00
Tom Rini
772e173802 Merge branch 'master' of git://git.denx.de/u-boot-sh 2014-07-25 15:05:09 -04:00
Dirk Eibach
d9f923ffcb board: Add CONFIG_SYS_GENERIC_BOARD to all gdsys boards
Add the generic board infrastructure to all gdsys boards.

Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Stefan Roese <sr@denx.de>
2014-07-25 10:55:49 +02:00
Dirk Eibach
d29437aa77 ppc: Make ppc4xx ready for CONFIG_SYS_GENERIC_BOARD
The generic board  infrastructure assumes that gd is set by
arch code.

Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: Stefan Roese <sr@denx.de>
2014-07-25 10:55:49 +02:00
Nobuhiro Iwamatsu
cff2f5f09e arm: rmobile: Add support Alt board
The alt board has R8A7794, 1GB DDR3-SDRAM, USB, Ethernet, QSPI,
MMC, SDHI and more.

This commit supports the following functions:
 - DDR3-SDRAM
 - SCIF
 - I2C
 - Ethernet
 - QSPI

Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-07-24 14:03:46 +09:00
Nobuhiro Iwamatsu
fafcfc5a98 arm: rmobile: Add support R8A7794
Renesas R8A7794 is CPU with Cortex-A15. This supports the basic register
definition and GPIO and framework of PFC.

Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
2014-07-24 14:03:46 +09:00