mirror of
https://github.com/AsahiLinux/u-boot
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arm: rmobile: Add support Alt board
The alt board has R8A7794, 1GB DDR3-SDRAM, USB, Ethernet, QSPI, MMC, SDHI and more. This commit supports the following functions: - DDR3-SDRAM - SCIF - I2C - Ethernet - QSPI Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
This commit is contained in:
Nobuhiro Iwamatsu
parent
fafcfc5a98
commit
cff2f5f09e
6 changed files with 1305 additions and 0 deletions
9
board/renesas/alt/Makefile
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9
board/renesas/alt/Makefile
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#
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# board/renesas/alt/Makefile
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#
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# Copyright (C) 2014 Renesas Electronics Corporation
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#
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# SPDX-License-Identifier: GPL-2.0
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#
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obj-y := alt.o qos.o
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173
board/renesas/alt/alt.c
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173
board/renesas/alt/alt.c
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/*
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* board/renesas/alt/alt.c
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*
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* Copyright (C) 2014 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <malloc.h>
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#include <asm/processor.h>
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#include <asm/mach-types.h>
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#include <asm/io.h>
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#include <asm/errno.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/arch/rmobile.h>
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#include <netdev.h>
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#include <miiphy.h>
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#include <i2c.h>
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#include <div64.h>
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#include "qos.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define CLK2MHZ(clk) (clk / 1000 / 1000)
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void s_init(void)
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{
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struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
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struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
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/* Watchdog init */
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writel(0xA5A5A500, &rwdt->rwtcsra);
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writel(0xA5A5A500, &swdt->swtcsra);
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/* QoS */
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qos_init();
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}
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#define MSTPSR1 0xE6150038
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#define SMSTPCR1 0xE6150134
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#define TMU0_MSTP125 (1 << 25)
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#define MSTPSR7 0xE61501C4
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#define SMSTPCR7 0xE615014C
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#define SCIF0_MSTP719 (1 << 19)
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#define MSTPSR8 0xE61509A0
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#define SMSTPCR8 0xE6150990
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#define ETHER_MSTP813 (1 << 13)
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#define mstp_setbits(type, addr, saddr, set) \
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out_##type((saddr), in_##type(addr) | (set))
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#define mstp_clrbits(type, addr, saddr, clear) \
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out_##type((saddr), in_##type(addr) & ~(clear))
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#define mstp_setbits_le32(addr, saddr, set) \
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mstp_setbits(le32, addr, saddr, set)
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#define mstp_clrbits_le32(addr, saddr, clear) \
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mstp_clrbits(le32, addr, saddr, clear)
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int board_early_init_f(void)
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{
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/* TMU */
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mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
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/* SCIF0 */
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mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP719);
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/* ETHER */
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mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
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return 0;
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}
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void arch_preboot_os(void)
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{
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/* Disable TMU0 */
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mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
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}
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int board_init(void)
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{
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/* adress of boot parameters */
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gd->bd->bi_boot_params = ALT_SDRAM_BASE + 0x100;
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/* Init PFC controller */
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r8a7794_pinmux_init();
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/* Ether Enable */
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gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
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gpio_request(GPIO_FN_ETH_RX_ER, NULL);
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gpio_request(GPIO_FN_ETH_RXD0, NULL);
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gpio_request(GPIO_FN_ETH_RXD1, NULL);
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gpio_request(GPIO_FN_ETH_LINK, NULL);
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gpio_request(GPIO_FN_ETH_REFCLK, NULL);
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gpio_request(GPIO_FN_ETH_MDIO, NULL);
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gpio_request(GPIO_FN_ETH_TXD1, NULL);
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gpio_request(GPIO_FN_ETH_TX_EN, NULL);
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gpio_request(GPIO_FN_ETH_MAGIC, NULL);
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gpio_request(GPIO_FN_ETH_TXD0, NULL);
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gpio_request(GPIO_FN_ETH_MDC, NULL);
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gpio_request(GPIO_FN_IRQ8, NULL);
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/* PHY reset */
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gpio_request(GPIO_GP_1_24, NULL);
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gpio_direction_output(GPIO_GP_1_24, 0);
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mdelay(20);
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gpio_set_value(GPIO_GP_1_24, 1);
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udelay(1);
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return 0;
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}
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#define CXR24 0xEE7003C0 /* MAC address high register */
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#define CXR25 0xEE7003C8 /* MAC address low register */
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int board_eth_init(bd_t *bis)
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{
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#ifdef CONFIG_SH_ETHER
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int ret = -ENODEV;
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u32 val;
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unsigned char enetaddr[6];
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ret = sh_eth_initialize(bis);
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if (!eth_getenv_enetaddr("ethaddr", enetaddr))
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return ret;
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/* Set Mac address */
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val = enetaddr[0] << 24 | enetaddr[1] << 16 |
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enetaddr[2] << 8 | enetaddr[3];
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writel(val, CXR24);
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val = enetaddr[4] << 8 | enetaddr[5];
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writel(val, CXR25);
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return ret;
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#else
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return 0;
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#endif
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}
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int dram_init(void)
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{
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gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
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gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
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return 0;
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}
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const struct rmobile_sysinfo sysinfo = {
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CONFIG_RMOBILE_BOARD_STRING
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};
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void dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = ALT_SDRAM_BASE;
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gd->bd->bi_dram[0].size = ALT_SDRAM_SIZE;
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}
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int board_late_init(void)
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{
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return 0;
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}
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void reset_cpu(ulong addr)
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{
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u8 val;
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i2c_set_bus_num(1); /* PowerIC connected to ch3 */
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i2c_init(400000, 0);
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i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
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val |= 0x02;
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i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
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}
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944
board/renesas/alt/qos.c
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944
board/renesas/alt/qos.c
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/*
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* board/renesas/alt/qos.c
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*
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* Copyright (C) 2014 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: GPL-2.0
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*
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/mach-types.h>
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#include <asm/io.h>
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#include <asm/arch/rmobile.h>
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/* QoS version 0.10 */
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enum {
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DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
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DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
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DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14,
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DBSC3_15,
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DBSC3_NR,
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};
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static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = {
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[DBSC3_00] = DBSC3_0_QOS_R0_BASE,
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[DBSC3_01] = DBSC3_0_QOS_R1_BASE,
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[DBSC3_02] = DBSC3_0_QOS_R2_BASE,
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[DBSC3_03] = DBSC3_0_QOS_R3_BASE,
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[DBSC3_04] = DBSC3_0_QOS_R4_BASE,
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[DBSC3_05] = DBSC3_0_QOS_R5_BASE,
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[DBSC3_06] = DBSC3_0_QOS_R6_BASE,
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[DBSC3_07] = DBSC3_0_QOS_R7_BASE,
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[DBSC3_08] = DBSC3_0_QOS_R8_BASE,
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[DBSC3_09] = DBSC3_0_QOS_R9_BASE,
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[DBSC3_10] = DBSC3_0_QOS_R10_BASE,
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[DBSC3_11] = DBSC3_0_QOS_R11_BASE,
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[DBSC3_12] = DBSC3_0_QOS_R12_BASE,
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[DBSC3_13] = DBSC3_0_QOS_R13_BASE,
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[DBSC3_14] = DBSC3_0_QOS_R14_BASE,
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[DBSC3_15] = DBSC3_0_QOS_R15_BASE,
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};
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static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = {
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[DBSC3_00] = DBSC3_0_QOS_W0_BASE,
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[DBSC3_01] = DBSC3_0_QOS_W1_BASE,
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[DBSC3_02] = DBSC3_0_QOS_W2_BASE,
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[DBSC3_03] = DBSC3_0_QOS_W3_BASE,
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[DBSC3_04] = DBSC3_0_QOS_W4_BASE,
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[DBSC3_05] = DBSC3_0_QOS_W5_BASE,
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[DBSC3_06] = DBSC3_0_QOS_W6_BASE,
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[DBSC3_07] = DBSC3_0_QOS_W7_BASE,
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[DBSC3_08] = DBSC3_0_QOS_W8_BASE,
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[DBSC3_09] = DBSC3_0_QOS_W9_BASE,
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[DBSC3_10] = DBSC3_0_QOS_W10_BASE,
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[DBSC3_11] = DBSC3_0_QOS_W11_BASE,
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[DBSC3_12] = DBSC3_0_QOS_W12_BASE,
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[DBSC3_13] = DBSC3_0_QOS_W13_BASE,
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[DBSC3_14] = DBSC3_0_QOS_W14_BASE,
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[DBSC3_15] = DBSC3_0_QOS_W15_BASE,
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};
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void qos_init(void)
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{
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int i;
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struct rcar_s3c *s3c;
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struct rcar_s3c_qos *s3c_qos;
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struct rcar_dbsc3_qos *qos_addr;
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struct rcar_mxi *mxi;
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struct rcar_mxi_qos *mxi_qos;
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struct rcar_axi_qos *axi_qos;
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/* DBSC DBADJ2 */
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writel(0x20042004, DBSC3_0_DBADJ2);
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/* S3C -QoS */
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s3c = (struct rcar_s3c *)S3C_BASE;
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writel(0x1F0D0B0A, &s3c->s3crorr);
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writel(0x1F0D0B09, &s3c->s3cworr);
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/* QoS Control Registers */
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s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE;
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writel(0x00890089, &s3c_qos->s3cqos0);
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writel(0x20960010, &s3c_qos->s3cqos1);
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writel(0x20302030, &s3c_qos->s3cqos2);
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writel(0x20AA2200, &s3c_qos->s3cqos3);
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writel(0x00002032, &s3c_qos->s3cqos4);
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writel(0x20960010, &s3c_qos->s3cqos5);
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writel(0x20302030, &s3c_qos->s3cqos6);
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writel(0x20AA2200, &s3c_qos->s3cqos7);
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writel(0x00002032, &s3c_qos->s3cqos8);
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s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE;
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writel(0x00890089, &s3c_qos->s3cqos0);
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writel(0x20960010, &s3c_qos->s3cqos1);
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writel(0x20302030, &s3c_qos->s3cqos2);
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writel(0x20AA2200, &s3c_qos->s3cqos3);
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writel(0x00002032, &s3c_qos->s3cqos4);
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writel(0x20960010, &s3c_qos->s3cqos5);
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writel(0x20302030, &s3c_qos->s3cqos6);
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writel(0x20AA2200, &s3c_qos->s3cqos7);
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writel(0x00002032, &s3c_qos->s3cqos8);
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s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE;
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writel(0x80928092, &s3c_qos->s3cqos0);
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writel(0x20960020, &s3c_qos->s3cqos1);
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writel(0x20302030, &s3c_qos->s3cqos2);
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writel(0x20AA20DC, &s3c_qos->s3cqos3);
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writel(0x00002032, &s3c_qos->s3cqos4);
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writel(0x20960020, &s3c_qos->s3cqos5);
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writel(0x20302030, &s3c_qos->s3cqos6);
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writel(0x20AA20DC, &s3c_qos->s3cqos7);
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writel(0x00002032, &s3c_qos->s3cqos8);
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s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE;
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writel(0x00820082, &s3c_qos->s3cqos0);
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writel(0x20960020, &s3c_qos->s3cqos1);
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writel(0x20302030, &s3c_qos->s3cqos2);
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writel(0x20AA20FA, &s3c_qos->s3cqos3);
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writel(0x00002032, &s3c_qos->s3cqos4);
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writel(0x20960020, &s3c_qos->s3cqos5);
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writel(0x20302030, &s3c_qos->s3cqos6);
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writel(0x20AA20FA, &s3c_qos->s3cqos7);
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writel(0x00002032, &s3c_qos->s3cqos8);
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/* DBSC -QoS */
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/* DBSC0 - Read */
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for (i = DBSC3_00; i < DBSC3_NR; i++) {
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qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i];
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writel(0x00000002, &qos_addr->dblgcnt);
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writel(0x0000207D, &qos_addr->dbtmval0);
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writel(0x00002053, &qos_addr->dbtmval1);
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writel(0x0000202A, &qos_addr->dbtmval2);
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writel(0x00001FBD, &qos_addr->dbtmval3);
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writel(0x00000001, &qos_addr->dbrqctr);
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writel(0x00002064, &qos_addr->dbthres0);
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writel(0x0000203E, &qos_addr->dbthres1);
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writel(0x00002019, &qos_addr->dbthres2);
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writel(0x00000001, &qos_addr->dblgqon);
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}
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/* DBSC0 - Write */
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for (i = DBSC3_00; i < DBSC3_NR; i++) {
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qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i];
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writel(0x00000002, &qos_addr->dblgcnt);
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writel(0x0000207D, &qos_addr->dbtmval0);
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writel(0x00002053, &qos_addr->dbtmval1);
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writel(0x00002043, &qos_addr->dbtmval2);
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writel(0x00002030, &qos_addr->dbtmval3);
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writel(0x00000001, &qos_addr->dbrqctr);
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writel(0x00002064, &qos_addr->dbthres0);
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writel(0x0000203E, &qos_addr->dbthres1);
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writel(0x00002031, &qos_addr->dbthres2);
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writel(0x00000001, &qos_addr->dblgqon);
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}
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/* CCI-400 -QoS */
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writel(0x20001000, CCI_400_MAXOT_1);
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writel(0x20001000, CCI_400_MAXOT_2);
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writel(0x0000000C, CCI_400_QOSCNTL_1);
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writel(0x0000000C, CCI_400_QOSCNTL_2);
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/* MXI -QoS */
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/* Transaction Control (MXI) */
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mxi = (struct rcar_mxi *)MXI_BASE;
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writel(0x00000013, &mxi->mxrtcr);
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writel(0x00000013, &mxi->mxwtcr);
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writel(0x00780080, &mxi->mxsaar0);
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writel(0x02000800, &mxi->mxsaar1);
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/* QoS Control (MXI) */
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mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE;
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writel(0x0000000C, &mxi_qos->vspdu0);
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writel(0x0000000E, &mxi_qos->du0);
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/* AXI -QoS */
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/* Transaction Control (MXI) */
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axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE;
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writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x00002245, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x000020A6, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x00002245, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x00002245, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x00002245, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x0000214C, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002004, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002004, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002004, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002004, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x00002245, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x000020A6, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x000020A6, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x00002053, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x00002053, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_AX2M_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x00002245, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x00002029, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x00002245, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x00002053, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_DDM_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x000020A6, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_ETH_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x00002053, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_MPXM_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x00002245, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x0000214C, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x0000214C, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x000020A6, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM0_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x00002053, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM1_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x00002053, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
/* QoS Register (RT-AXI) */
|
||||
axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x00002053, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x00002053, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x00002245, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)RT_AXI_SY2RT_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x00002245, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
/* QoS Register (MP-AXI) */
|
||||
axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x00002037, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002014, &axi_qos->qosctset0);
|
||||
writel(0x00000040, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002014, &axi_qos->qosctset0);
|
||||
writel(0x00000040, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00001FF0, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00002001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002004, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x00002053, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE;
|
||||
writel(0x00000000, &axi_qos->qosconf);
|
||||
writel(0x0000206E, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
/* QoS Register (SYS-AXI256) */
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x000020EB, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x000020EB, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x000020EB, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x000020EB, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
/* QoS Register (CCI-AXI) */
|
||||
axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002004, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x00002245, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002004, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002004, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002004, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x00002245, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002004, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002004, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000000, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
/* QoS Register (Media-AXI) */
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x000020DC, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x000020AA, &axi_qos->qosthres0);
|
||||
writel(0x00002032, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE;
|
||||
writel(0x00000002, &axi_qos->qosconf);
|
||||
writel(0x000020DC, &axi_qos->qosctset0);
|
||||
writel(0x00002096, &axi_qos->qosctset1);
|
||||
writel(0x00002030, &axi_qos->qosctset2);
|
||||
writel(0x00002030, &axi_qos->qosctset3);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x000020AA, &axi_qos->qosthres0);
|
||||
writel(0x00002032, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002190, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002190, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00000001, &axi_qos->qosthres0);
|
||||
writel(0x00000001, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002190, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002190, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00000001, &axi_qos->qosthres0);
|
||||
writel(0x00000001, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002190, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002190, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00000001, &axi_qos->qosthres0);
|
||||
writel(0x00000001, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00001FF0, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00002001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x000020C8, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x000020C8, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00000001, &axi_qos->qosthres0);
|
||||
writel(0x00000001, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x000020C8, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x000020C8, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x000020C8, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x000020C8, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00000001, &axi_qos->qosthres0);
|
||||
writel(0x00000001, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x000020C8, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x000020C8, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE;
|
||||
writel(0x00000003, &axi_qos->qosconf);
|
||||
writel(0x000020C8, &axi_qos->qosctset0);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE;
|
||||
writel(0x00000003, &axi_qos->qosconf);
|
||||
writel(0x000020C8, &axi_qos->qosctset0);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE;
|
||||
writel(0x00000003, &axi_qos->qosconf);
|
||||
writel(0x00002063, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE;
|
||||
writel(0x00000003, &axi_qos->qosconf);
|
||||
writel(0x00002063, &axi_qos->qosctset0);
|
||||
writel(0x00000001, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002073, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002073, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00000001, &axi_qos->qosthres0);
|
||||
writel(0x00000001, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002073, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002073, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00000001, &axi_qos->qosthres0);
|
||||
writel(0x00000001, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
|
||||
axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE;
|
||||
writel(0x00000001, &axi_qos->qosconf);
|
||||
writel(0x00002073, &axi_qos->qosctset0);
|
||||
writel(0x00000020, &axi_qos->qosreqctr);
|
||||
writel(0x00002064, &axi_qos->qosthres0);
|
||||
writel(0x00002004, &axi_qos->qosthres1);
|
||||
writel(0x00000001, &axi_qos->qosthres2);
|
||||
writel(0x00000001, &axi_qos->qosqon);
|
||||
}
|
||||
12
board/renesas/alt/qos.h
Normal file
12
board/renesas/alt/qos.h
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
/*
|
||||
* Copyright (C) 2013 Renesas Electronics Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#ifndef __QOS_H__
|
||||
#define __QOS_H__
|
||||
|
||||
void qos_init(void);
|
||||
|
||||
#endif
|
||||
|
|
@ -372,6 +372,7 @@ Active arm armv7 omap5 ti dra7xx
|
|||
Active arm armv7 omap5 ti omap5_uevm omap5_uevm - -
|
||||
Active arm armv7 rmobile atmark-techno armadillo-800eva armadillo-800eva - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
|
||||
Active arm armv7 rmobile kmc kzm9g kzm9g - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>:Tetsuyuki Kobayashi <koba@kmckk.co.jp>
|
||||
Active arm armv7 rmobile renesas alt alt - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
|
||||
Active arm armv7 rmobile renesas koelsch koelsch - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
|
||||
Active arm armv7 rmobile renesas lager lager - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
|
||||
Active arm armv7 s5pc1xx samsung goni s5p_goni - Robert Baldyga <r.baldyga@samsung.com>
|
||||
|
|
|
|||
166
include/configs/alt.h
Normal file
166
include/configs/alt.h
Normal file
|
|
@ -0,0 +1,166 @@
|
|||
/*
|
||||
* include/configs/alt.h
|
||||
* This file is alt board configuration.
|
||||
*
|
||||
* Copyright (C) 2014 Renesas Electronics Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0
|
||||
*/
|
||||
|
||||
#ifndef __ALT_H
|
||||
#define __ALT_H
|
||||
|
||||
#undef DEBUG
|
||||
#define CONFIG_ARMV7
|
||||
#define CONFIG_R8A7794
|
||||
#define CONFIG_RMOBILE
|
||||
#define CONFIG_RMOBILE_BOARD_STRING "Alt"
|
||||
#define CONFIG_SH_GPIO_PFC
|
||||
|
||||
#include <asm/arch/rmobile.h>
|
||||
|
||||
#define CONFIG_CMD_EDITENV
|
||||
#define CONFIG_CMD_SAVEENV
|
||||
#define CONFIG_CMD_MEMORY
|
||||
#define CONFIG_CMD_DFL
|
||||
#define CONFIG_CMD_SDRAM
|
||||
#define CONFIG_CMD_RUN
|
||||
#define CONFIG_CMD_LOADS
|
||||
#define CONFIG_CMD_NET
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_NFS
|
||||
#define CONFIG_CMD_BOOTZ
|
||||
#define CONFIG_CMD_SF
|
||||
#define CONFIG_CMD_SPI
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xE6304000
|
||||
#define CONFIG_SYS_THUMB_BUILD
|
||||
#define CONFIG_SYS_GENERIC_BOARD
|
||||
|
||||
#define CONFIG_CMDLINE_TAG
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_INITRD_TAG
|
||||
#define CONFIG_CMDLINE_EDITING
|
||||
|
||||
#define CONFIG_OF_LIBFDT
|
||||
#define BOARD_LATE_INIT
|
||||
|
||||
#define CONFIG_BAUDRATE 38400
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
#define CONFIG_BOOTARGS ""
|
||||
|
||||
#define CONFIG_VERSION_VARIABLE
|
||||
#undef CONFIG_SHOW_BOOT_PROGRESS
|
||||
|
||||
#define CONFIG_ARCH_CPU_INIT
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
#define CONFIG_DISPLAY_BOARDINFO
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
#define CONFIG_TMU_TIMER
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC
|
||||
#define STACK_AREA_SIZE 0xC000
|
||||
#define LOW_LEVEL_MERAM_STACK \
|
||||
(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
|
||||
|
||||
/* MEMORY */
|
||||
#define ALT_SDRAM_BASE 0x40000000
|
||||
#define ALT_SDRAM_SIZE (1024u * 1024 * 1024)
|
||||
#define ALT_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
|
||||
|
||||
#define CONFIG_SYS_LONGHELP
|
||||
#define CONFIG_SYS_CBSIZE 256
|
||||
#define CONFIG_SYS_PBSIZE 256
|
||||
#define CONFIG_SYS_MAXARGS 16
|
||||
#define CONFIG_SYS_BARGSIZE 512
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 38400, 115200 }
|
||||
|
||||
/* SCIF */
|
||||
#define CONFIG_SCIF_CONSOLE
|
||||
#define CONFIG_CONS_SCIF2
|
||||
#undef CONFIG_SYS_CONSOLE_INFO_QUIET
|
||||
#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
|
||||
#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START (ALT_SDRAM_BASE)
|
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
|
||||
504 * 1024 * 1024)
|
||||
#undef CONFIG_SYS_ALT_MEMTEST
|
||||
#undef CONFIG_SYS_MEMTEST_SCRATCH
|
||||
#undef CONFIG_SYS_LOADS_BAUD_CHANGE
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE (ALT_SDRAM_BASE)
|
||||
#define CONFIG_SYS_SDRAM_SIZE (ALT_UBOOT_SDRAM_SIZE)
|
||||
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fc0)
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE 0x00000000
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
|
||||
#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
|
||||
|
||||
/* FLASH */
|
||||
#define CONFIG_SPI
|
||||
#define CONFIG_SPI_FLASH_BAR
|
||||
#define CONFIG_SH_QSPI
|
||||
#define CONFIG_SPI_FLASH
|
||||
#define CONFIG_SPI_FLASH_SPANSION
|
||||
#define CONFIG_SPI_FLASH_QUAD
|
||||
#define CONFIG_SYS_NO_FLASH
|
||||
|
||||
/* ENV setting */
|
||||
#define CONFIG_ENV_IS_IN_SPI_FLASH
|
||||
#define CONFIG_ENV_SECT_SIZE (256 * 1024)
|
||||
#define CONFIG_ENV_ADDR 0xC0000
|
||||
#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
|
||||
#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"bootm_low=0x40e00000\0" \
|
||||
"bootm_size=0x100000\0" \
|
||||
|
||||
/* SH Ether */
|
||||
#define CONFIG_NET_MULTI
|
||||
#define CONFIG_SH_ETHER
|
||||
#define CONFIG_SH_ETHER_USE_PORT 0
|
||||
#define CONFIG_SH_ETHER_PHY_ADDR 0x1
|
||||
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
|
||||
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
|
||||
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
|
||||
#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
|
||||
#define CONFIG_PHYLIB
|
||||
#define CONFIG_PHY_MICREL
|
||||
#define CONFIG_BITBANGMII
|
||||
#define CONFIG_BITBANGMII_MULTI
|
||||
|
||||
/* Board Clock */
|
||||
#define RMOBILE_XTAL_CLK 20000000u
|
||||
#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
|
||||
#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
|
||||
#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2)
|
||||
#define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24)
|
||||
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_P_CLK_FREQ
|
||||
|
||||
#define CONFIG_SYS_TMU_CLK_DIV 4
|
||||
|
||||
/* i2c */
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_SH
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3
|
||||
#define CONFIG_SYS_I2C_SH_BASE0 0xE6500000
|
||||
#define CONFIG_SYS_I2C_SH_SPEED0 400000
|
||||
#define CONFIG_SYS_I2C_SH_BASE1 0xE6510000
|
||||
#define CONFIG_SYS_I2C_SH_SPEED1 400000
|
||||
#define CONFIG_SYS_I2C_SH_BASE2 0xE60B0000
|
||||
#define CONFIG_SYS_I2C_SH_SPEED2 400000
|
||||
#define CONFIG_SH_I2C_DATA_HIGH 4
|
||||
#define CONFIG_SH_I2C_DATA_LOW 5
|
||||
#define CONFIG_SH_I2C_CLOCK 10000000
|
||||
|
||||
#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
|
||||
|
||||
#endif /* __ALT_H */
|
||||
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Reference in a new issue