Commit graph

5921 commits

Author SHA1 Message Date
Bin Meng
15c7c6b31a x86: ich-spi: Fix a bug of reading from a non-64 bytes aligned address
The ich spi controller driver spi_xfer() tries to align reading
address to 64 bytes when doing spi data in, which causes a bug of
either infinite loop or a huge size memcpy().

Actually the ich spi controller does not have such requirement of
64 bytes alignment when reading data from spi slave devices.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2014-12-13 15:08:04 -07:00
Tom Rini
a5a5882611 Merge git://git.denx.de/u-boot-dm 2014-12-11 20:47:34 -05:00
Tom Rini
fc9b0b8043 Merge branch 'master' of git://git.denx.de/u-boot-usb
Conflicts:
	board/freescale/mx6sxsabresd/mx6sxsabresd.c

Signed-off-by: Tom Rini <trini@ti.com>
2014-12-11 18:40:49 -05:00
Tom Rini
2c49323d5d Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq 2014-12-11 18:28:09 -05:00
Simon Glass
b0e6ef4640 dm: i2c: tegra: Convert to driver model
This converts all Tegra boards over to use driver model for I2C. The driver
is adjusted to use driver model and the following obsolete CONFIGs are
removed:

   - CONFIG_SYS_I2C_INIT_BOARD
   - CONFIG_I2C_MULTI_BUS
   - CONFIG_SYS_MAX_I2C_BUS
   - CONFIG_SYS_I2C_SPEED
   - CONFIG_SYS_I2C

This has been tested on:
- trimslice (no I2C)
- beaver
- Jetson-TK1

It has not been tested on Tegra 114 as I don't have that board.

Acked-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-12-11 13:18:44 -07:00
Simon Glass
964d153c0e dm: device: Add newline to debug() messages
Some of these are missing a newline. Add it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2014-12-11 13:18:43 -07:00
Simon Glass
20142019a9 dm: Add a simple EEPROM driver
There seem to be a few EEPROM drivers around - perhaps we should have a
single standard one? This simple driver is used for sandbox testing, but
could be pressed into more active service.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-11 13:18:43 -07:00
Simon Glass
6ec1b75358 dm: i2c: Add an I2C EEPROM simulator
To enable testing of I2C, add a simple I2C EEPROM simulator for sandbox.
It supports reading and writing from a small data store.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-11 13:18:42 -07:00
Simon Glass
d19de0d314 dm: i2c: Add a sandbox I2C driver
This driver includes some test features such as only supporting certain
bus speeds. It passes its I2C traffic through to an emulator.

Acked-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-11 13:18:42 -07:00
Simon Glass
c70c71d833 dm: i2c: Add I2C emulation driver for sandbox
In order to test I2C we need some sort of emulation interface. Add hooks
to allow a driver to emulate an I2C device for sandbox.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-11 13:18:42 -07:00
Simon Glass
c6202d857e dm: i2c: Add a uclass for I2C
The uclass implements the same operations as the current I2C framework but
makes some changes to make it fit driver model better:

- Remove the chip address from API calls
- Remove the address length from API calls
- Remove concept of 'current' I2C bus
- Drop all existing init functions

Acked-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2014-12-11 13:18:42 -07:00
Simon Glass
59c73d7555 dm: serial_pl01x: Add missing private data size
The private data size is missing from the driver, so we store it at 0,
which causes problems when something overwrites memory at 0.

Fix this.

Change-Id: I6f551ee905b0064ae8343e41e46450c37c8c8c1a
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
2014-12-11 13:18:41 -07:00
Masahiro Yamada
80d9ef8d40 lib: string: move strlcpy() to a common place
Move strlcpy() definition from drivers/usb/gadget/ether.c to
lib/string.c because it is a very useful function.
Let's add the prototype to include/linux/string.h too.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-11 13:18:41 -07:00
Jaiprakash Singh
1d421cc677 driver/mtd: Fix IFC compilation warnings
'eccstat' array elements might be used uninitialized

Signed-off-by: Jaiprakash Singh <b44839@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:42:32 -08:00
Tang Yuantian
a7787b7850 fsl/sleep: updated the deep sleep framework for QorIQ platforms
With the introducing of generic board and ARM-based cores, current
deep sleep framework doesn't work anymore.
This patch will convert the current framework to adapt this change.
Basically it does:
1. Converts all the Freescale's DDR driver to support deep sleep.
2. Added basic framework support for ARM-based and PPC-based
cores separately.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:41:18 -08:00
Nikhil Badola
da5ce448c7 drivers: usb: fsl: Check USB Erratum A007792 applicability
Check USB Erratum A007792 applicability. If applicable, add
corresponding  property in the device tree via device tree fixup

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:41:11 -08:00
Nikhil Badola
ecfc19f31f drivers: usb: fsl: Add USB device-tree errata framework
Add a new framework for fsl usb erratum handling to standardize
erratum checking only inside Uboot. Information to kernel is passed
via a boolean property corresponding to erratum, hence eliminating
need for code duplication inside kernel

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:41:03 -08:00
Nikhil Badola
a1c04e2785 drivers: usb: Make usb device-tree fixup code architecture independent
move usb device tree fixup code from "arch/powerpc/" to "drivers/usb/"
so that it works independent of architecture it is running on

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:40:50 -08:00
Alison Wang
8ab967b6c6 arm: ls102xa: Add NAND boot support for LS1021AQDS board
This patch adds NAND boot support for LS1021AQDS board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from NAND flash to DDR, finally SPL transfer control to u-boot.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:40:24 -08:00
Minghuan Lian
da419027af arm: ls102xa: Update PCIe dts node status
The patch changes PCIe dts node status to 'disabled' if the
corresponding controller is disabled according to serdes protocol.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-11 09:35:56 -08:00
Tom Rini
9b416a9f4c Merge branch 'master' of git://www.denx.de/git/u-boot-imx 2014-12-10 09:07:25 -05:00
Tom Rini
272a1acf1e Merge git://git.denx.de/u-boot-mpc85xx 2014-12-08 16:35:07 -05:00
Tom Rini
98d2d5e8c4 Merge branch 'master' of git://git.denx.de/u-boot-ti 2014-12-08 16:35:06 -05:00
Tom Rini
8bd60ccf53 Merge git://git.denx.de/u-boot-i2c 2014-12-08 16:35:05 -05:00
Tom Rini
1a9c8f12f2 Merge branch 'master' of git://git.denx.de/u-boot-sh 2014-12-08 09:36:26 -05:00
Masahiro Yamada
8b923a56dc blackfin: include <linux/compiler.h> rather than define __iomem
The macro __iomem is defined in include/linux/compiler.h.
Let's include it rather than double __iomem defines.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Sonic Zhang <sonic.adi@gmail.com>
2014-12-08 09:35:46 -05:00
Masahiro Yamada
afc366f01b Replace <compiler.h> with <linux/compiler.h>
Including <linux/compiler.h> is enough for general use.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
2014-12-08 09:35:46 -05:00
Vikas Manocha
eb8a4fe0dc serial: pl01x: avoid pl01x type check two times
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-08 09:35:45 -05:00
Vikas Manocha
f7e517b4eb serial: pl01x: disable as per type of pl01x
pl010 & pl011 have different control register offsets, setting it as per
the pl01x type.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-08 09:35:44 -05:00
Vikas Manocha
d2ca9fd2cd serial: pl01x: move all line control at same place
Receive line control uses same setting as transmit line control, also one lcrh
write is effective for both baud rate & receive line control internal update.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-08 09:35:44 -05:00
Vikas Manocha
2df810717e serial: pl01x: fix pl011 baud rate configuration
UART_IBRD, UART_FBRD, and UART_LCR_H form a single 30-bit wide register which
is updated on a single write strobe generated by a UART_LCR_H write. So, to
internally update the content of UART_IBRD or UART_FBRD, a write to UART_LCR_H
must always be performed at the end.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-08 09:35:44 -05:00
Vikas Manocha
a7deea691c serial: pl01x: pass pl01x_type to set baudrate
Although we were checking the pl01x type, seems like PL010 type was being
passed by mistake.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Acked-by: Simon Glass <sjg@chromium.org>
2014-12-08 09:35:44 -05:00
Mark Tomlinson
f4ed36964a i2c: Correct spelling error
"diconnect" and "disconnet" should both be "disconnect".

Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
2014-12-08 07:27:22 +01:00
Mark Tomlinson
2fe50ef403 i2c: Fix deselection of muxes
Due to an uninitialised variable, when muxes were deselected, any value
could be written to the mux control register. On the PCA9548, this could
result in multiple channels being selected, thus enabling multiple
pull-up resistors, and much bus capacitance.

The fix is simply to initialise the written value to zero.

Signed-off-by: Mark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
2014-12-08 07:27:06 +01:00
Shengzhou Liu
c18fc2c960 net/phy: enable serdes auto-negotiation for vsc8514 phy
VSC8514 QSGMII PHY requires enabling auto-negotiation,
otherwise it wouldn't work.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:15 -08:00
Shengzhou Liu
cc19c25e27 net/fman: update 10GEC to fit new SoC
fm_standard_init() initializes each 10G port by FM_TGEC_INFO_INITIALIZER.
but it needs different implementation of FM_TGEC_INFO_INITIALIZER on different SoCs.
on SoCs earlier(e.g. T4240, T2080), the notation between 10GEC and MAC as below:
	10GEC1->MAC9, 10GEC2->MAC10, 10GEC3->MAC1, 10GEC4->MAC2
on SoCs later(e.g. T1024, etc), the notation between 10GEC and MAC as below:
	10GEC1->MAC1, 10GEC2->MAC2

so we introduce CONFIG_FSL_FM_10GEC_REGULAR_NOTATION to fit the new SoCs on
which 10GEC enumeration is consistent with MAC enumeration.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:15 -08:00
Shengzhou Liu
f605079041 powerpc/mpc85xx: Add T1024/T1023 SoC support
Add support for Freescale T1024/T1023 SoC.

The T1024 SoC includes the following function and features:
- Two 64-bit Power architecture e5500 cores, up to 1.4GHz
- private 256KB L2 cache each core and shared 256KB CoreNet platform cache (CPC)
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
- Four MAC for 1G/2.5G/10G network interfaces (RGMII, SGMII, QSGMII, XFI)
- High-speed peripheral interfaces
  - Three PCI Express 2.0 controllers
- Additional peripheral interfaces
  - One SATA 2.0 controller
  - Two USB 2.0 controllers with integrated PHY
  - Enhanced secure digital host controller (SD/eSDHC/eMMC)
  - Enhanced serial peripheral interface (eSPI)
  - Four I2C controllers
  - Four 2-pin UARTs or two 4-pin UARTs
  - Integrated Flash Controller supporting NAND and NOR flash
- Two 8-channel DMA engines
- Multicore programmable interrupt controller (PIC)
- LCD interface (DIU) with 12 bit dual data rate
- QUICC Engine block supporting TDM, HDLC, and UART
- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
- Support for hardware virtualization and partitioning enforcement
- QorIQ Platform's Trust Architecture 2.0

Differences between T1024 and T1023:
  Feature         T1024  T1023
  QUICC Engine:   yes    no
  DIU:            yes    no
  Deep Sleep:     yes    no
  I2C controller: 4      3
  DDR:            64-bit 32-bit
  IFC:            32-bit 28-bit

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:14 -08:00
York Sun
789b3447c0 driver/ddr/fsl: Add workaround for faulty SPD
Some UDIMMs have faulty SPD with wrong mapping for DQ[36-39].
Using raw card spec in case this error is detected.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:14 -08:00
Suresh Gupta
e2544e7a54 B4860QDS: Enable enet port as per fsl_b4860_serdes2 string in hwconfig
In B4860QDS board SerDes2 lanes EFGH either go to SFP or AMC riser card
slot2 so either DTSEC3/DTSEC4 or TGEC1/TGEC2 should be accessible. This
Patch enables DTSEC3/DTSEC4 or TGEC1/TGEC2 on bases of user specified
string fsl_b4860_serdes2:sfp_amc=amc or fsl_b4860_serdes2:sfp_amc=sfp
respectively in hwconfig.

Signed-off-by: Suresh Gupta <suresh.gupta@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:14 -08:00
Shaohui Xie
89b94d851d powerpc/b4860qds: add xfi support
We need following changes to make xfi work on B4:
1. set cross-point switch VSC3308 to use sfp config when running xfi;
2. add 10G interface check for xfi;
3. set phy address for xfi so the 10G ports can be registered by mdio;

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:13 -08:00
Shengzhou Liu
9b18e5199e net/phy: Add support for CS4315/CS4340 PHY
Add support for Cortina CS4315/CS4340 10G PHY.
- This driver loads CS43xx firmware from NOR/NAND/SPI/SD device
  to initialize Cortina PHY.
- Cortina PHY has non-standard offset of PHY ID registers, thus
  we define own get_phy_id() to override default get_phy_id().
- To define macro CONFIG_PHY_CORTINA will enable this driver.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:11 -08:00
York Sun
84baed2a2b driver/ddr/fsl: Adjust timing_cfg_0 to better support two DDR slots
Increase write-to-write and read-to-read turnaround time for two-slot DDR
configurations. Previously only quad-rank and two dual-rank configurations
have this additional turnaround time. A recent test on two single-rank
DIMMs shows the shorter additional turnaround time is also needed.

Signed-off-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:11 -08:00
Joakim Tjernlund
bcb60cb9c4 Freescale t104x: Do not exclude SGMII
fman_port_enet_if() tests if FM1_DTSEC2 or FM1_DTSEC4 uses
RGMII or MII and if not returns PHY_INTERFACE_MODE_NONE.
This excludes testing for SGMII further down.

Remove the unconditional "else return PHY_INTERFACE_MODE_NONE"
so SGMII can be tested too.

Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Reviewed-by: York Sun <yorksun@freescale.com>
2014-12-05 08:06:07 -08:00
Gregoire Gentil
956a8bae53 ns16550.c: Fix for ns16550 driver hanging on OMAP4
The same problem that is seen on some OMAP3 is also seen on some OMAP4
so include them in the test in order to prevent some hangs during SPL.

[trini: Re-word commit message, make apply cleanly]
Signed-off-by: Tom Rini <trini@ti.com>
2014-12-04 21:28:32 -05:00
Stefan Roese
fb384c4720 mtd: nand: omap_gpmc: Always use ready/busy pin
The functions to detect the state of the ready / busy signal is already
available but only used in the SPL case. Lets use it always, also for the
main U-Boot. As all boards should have this HW connection.

Testing on Siemens Draco (am335x) showed a small perfomance gain by using
this ready pin to detect the NAND chip state. Here the values tested on
Draco with Hynix 4GBit NAND:

Without NAND ready pin:

U-Boot# time nand read 80400000 0 400000

NAND read: device 0 offset 0x0, size 0x400000
4194304 bytes read: OK

time: 2.947 seconds, 2947 ticks

With NAND ready pin:

U-Boot# time nand read 80400000 0 400000

NAND read: device 0 offset 0x0, size 0x400000
4194304 bytes read: OK

time: 2.795 seconds, 2795 ticks

So an increase of approx. 5%.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Roger Meier <r.meier@siemens.com>
Cc: Samuel Egli <samuel.egli@siemens.com>
2014-12-04 21:28:31 -05:00
Paul Kocialkowski
aac5450ea9 omap_hsmmc: Board-specific TWL4030 MMC power initializations
Boards using the TWL4030 regulator may not all use the LDOs the same way
(e.g. MMC2 power can be controlled by another LDO than VMMC2).
This delegates TWL4030 MMC power initializations to board-specific functions,
that may still call twl4030_power_mmc_init for the default behavior.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@ti.com>
[trini: Fix omap3_evm warning, add twl4030.h]
Signed-off-by: Tom Rini <trini@ti.com>
2014-12-04 21:28:15 -05:00
Nobuhiro Iwamatsu
9675f61077 mmc: sh_mmcif: Add support rmobile
Renesas R-Mobile/R-Car ARM SoC of MMC has the same IP that are supported by
sh_mmcif. This adds support R-Mobile/R-Car ARM SoC with the setting of the
clock support.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-12-05 11:16:22 +09:00
Nobuhiro Iwamatsu
7a7eb983a4 mmc: sh_mmcif: Change maximum and minimum value of MMC clock
Maximum value and the minimum value of clock for sh_mmcif instead by
base of MMC clock. This removes fixed clock, make the changes to be calculated
according to environment.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-12-05 11:15:52 +09:00
Nobuhiro Iwamatsu
21ea350385 mmc: sh_mmcif: Use DIV_ROUND_UP and fls instead of calculation loop
Use DIV_ROUND_UP and fls to simplify the code.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2014-12-05 11:15:11 +09:00
Paul Kocialkowski
f3e85e4825 twl4030: device-index-specific MMC power initializations, common ramp-up delay
Not every device has multiple MMC slots available, so it makes sense to enable
only the required LDOs for the available slots. Generic code in omap_hsmmc will
enable both VMMC1 and VMMC2, in doubt.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@ti.com>
2014-12-04 11:04:40 -05:00