Our R-Car3 Android userspace relies on the output of 'fastboot
getvar platform' and U-Boot currently is not able to handle it:
host $> fastboot getvar platform
getvar:platform FAILED (remote: Variable not implemented)
finished. total time: 0.001s
We either have the option of adding 'fastboot.platform' variable
to the default/saved environment as a workaround or add proper
'fastboot getvar platform' support in U-Boot via this patch.
In the latter case, other platforms can benefit from it too.
Note that R-Car3 already exports 'platform' environment variable via
v2019.01 commit 00e4b57e9e ("ARM: rmobile: Set environment variable
containing CPU type").
Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
Where we have to compute partition names, rather than using a hardcoded
32 for the partition name length, replace with PART_NAME_LEN.
Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
Reviewed-by: Eugeniu Rosca <rosca.eugeniu@gmail.com>
The DK1 and DK2 boards use the USB Type-C controller STUSB1600.
This patch updates:
- the device tree to add the I2C node in the DT
- the board stm32mp1 to probe this I2C device and use this controller
to check cable detection.
- the DWC2 driver to support a new dt property
"u-boot,force-b-session-valid" which forces B session and
device mode; it is a workaround because the VBUS sensing and
ID detection isn't available with stusb1600.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Add compatible "st,stm32mp1-hsotg" and associated driver data to manage
the usb33d-supply and the ST specific register for VBus sensing.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
# Conflicts:
# drivers/usb/gadget/dwc2_udc_otg.c
Reviewed-by: Lukasz Majewski <lukma@denx.de>
All TX fifo size can be different, add tx_fifo_sz_array[]
into dwc2_plat_otg_data to be able to set them.
tx_fifo_sz_array[] is 17 Bytes long and can contains max 16
tx fifo size (synopsys IP supports max 16 IN endpoints).
First entry of tx_fifo_sz_array[] is the number of valid
fifo size the array contains.
In case of tx_fifo_sz_array[] doesn't contains the same
number of element than max hardware endpoint, display
a warning message.
Compatibility with board which doesn't use tx_fifo_sz_array[]
(Rockchip rk322x/rk3128/rv1108/rk3288/rk3036) is kept.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Some DWC2 ip variant doesn't use 16 hardware endpoint as hardcoded
in the driver. Bits INEps [29:26] of HWCFG4 register allows to get
this information.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Add a new function to check the session B validity, to be use to check
cable connection.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Reset the hardware to be sure of the device state.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Minimal conversion to driver model by using the uclass
UCLASS_USB_GADGET_GENERIC based on:
- reset uclass
- clock uclass
- generic uclass.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Since its inception in upstream fastboot android-n-preview-1 [1],
"has-slot" option has never taken the form of "has_slot". Amongst the
users of "getvar has-slot:" is the upstream bootloadertest.py [2].
Current U-Boot "has_slot" version must be a typo. Fix it.
[1] https://android.googlesource.com/platform/system/core/+/a797479bd51c
("Fix fastboot variable name")
[2] https://android.googlesource.com/platform/system/extras/+/72de393e118e3
("Bootloader verification for AndroidThings.")
Fixes: f73a7df984 ("net: fastboot: Merge AOSP UDP fastboot")
Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
Acked-by: Alex Kiernan <alex.kiernan@gmail.com>
USB_MUSB_TI requires USB_MUSB_DSPS, failing at link time if it's not
selected:
drivers/usb/musb-new/built-in.o: In function `ti_musb_host_ofdata_to_platdata':
drivers/usb/musb-new/ti-musb.c:193: undefined reference to `musb_dsps_ops'
or if OF_CONTROL is not selected:
arch/arm/mach-omap2/built-in.o:(.data.usb0+0x24): undefined reference to `musb_dsps_ops'
Reviewed-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Tested-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
Add the DM_MMC-compatible DesignWare MMC driver support for Synopsys
ARC devboards. It is created to switch ARC devboards to use DM_MMC.
It required information such as clocks (Bus Interface Unit clock,
Card Interface Unit clock) and SDIO bus width.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
The generic timer count is an incrementing 64bit value and a timer driver
must return an incrementing 64bit value. The DW APB timer only provides a
32bit timer counting down, thus the result must be inverted and converted
to a 64bit value. The current implementation is however missing the 64bit
up-conversion and this results in random timer roll-overs, which in turn
triggers random timeouts throughout the codebase.
This patch adds the missing 64bit up-conversion to fix the issue.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Scrub memory content if ECC is enabled and it is not
from warm reset boot.
Enable icache and dcache before scrub memory
and use "DC ZVA" instruction to clear memory
to zeros. This instruction writes a cache line
at a time and it can prevent false ECC error
trigger if write cache line partially.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Stratix 10 maps dram from 0 to 128GB. There is a 2GB hole
in the memory for peripherals and other IO from 2GB to 4GB.
However the dram controller ignores upper address bits for
smaller dram configurations. Example: a 4GB dram
maps to multiple locations, every 4GB on the address.
Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Move SDRAM size check to SDRAM driver. sdram_calculate_size()
is called in SDRAM initialization already, avoid calling
twice in size check function.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
This adds reset handling to the cadence qspi driver.
For backwards compatibility, only a warning is printed when failing to
get reset handles.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
This adds reset handling to the devicetree-enabled Denali NAND driver.
For backwards compatibility, only a warning is printed when failing to
get reset handles.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
To clean up reset handling for socfpga gen5, port the DDR driver to DM
using UCLASS_RAM and implement proper reset handling.
This gets us rid of one ad-hoc call to socfpga_per_reset().
The gen5 driver is implemented in 2 distinct files. One of it (containing
the calibration training) is not touched much and is kept at using
hard coded addresses since the code grows even more otherwise.
SPL is changed from calling hard into the DDR driver code to just
probing UCLASS_RESET and UCLASS_RAM. It is happy after finding a RAM
driver after that.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
This adds code to take peripherals out of reset based on an environment
variable. This is in preparation for removing the code that does this from
SPL.
However, some drivers even in current Linux cannot handle peripheral reset,
so until this works, we need a compatibility workaround.
This workaround is implemented in the 'assert' and 'remove' callbacks of
this reset driver: the 'assert' callback does not disable peripherals that
were already taken out of reset, while the 'remove' callback, which is
called on OS_PREPARE, deasserts all peripheral resets if the environment
variable "socfpga_legacy_reset_compat" is set to 1, which is what the gen5
SPL did up to now.
This is in preparation to clean up the SPL and implementing proper reset
handling for U-Boot.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
The only member of this driver's priv struct is a pointer, which is
called 'membase'. However, since this driver handles multiple sub-
architectures, this is not the base address from dts but the base
address of some common registers of those sub-arches.
Reflect this better in sourcecode by renaming 'membase' to 'modrst_base'.
Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
fpga:
- Add support for external data in FIT
- Extend testing for external data case
- Inform user about a need to run post config on Zynq
arm:
- Tune zynq command functions
- Fix internal variable setting
arm64:
- Add support for zc39dr decoding
- Disable WDT for zcu100
- Small changes in reset_reason()
- Some DT changes (spi)
- Tune qspi-mini configuration
- Remove useless eeprom setting
- Fix two sdhci boot case
spi:
- Fix tap delay programming
clk:
- Enable i2c in SPL
net:
- Fix gem phydev handling
- Remove phy detection code from gem driver
general:
- Correct EXT_DTB usage for MULTI_DTB_FIT configuration
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Merge tag 'xilinx-for-v2019.07' of git://git.denx.de/u-boot-microblaze
Xilinx/FPGA changes for v2019.07
fpga:
- Add support for external data in FIT
- Extend testing for external data case
- Inform user about a need to run post config on Zynq
arm:
- Tune zynq command functions
- Fix internal variable setting
arm64:
- Add support for zc39dr decoding
- Disable WDT for zcu100
- Small changes in reset_reason()
- Some DT changes (spi)
- Tune qspi-mini configuration
- Remove useless eeprom setting
- Fix two sdhci boot case
spi:
- Fix tap delay programming
clk:
- Enable i2c in SPL
net:
- Fix gem phydev handling
- Remove phy detection code from gem driver
general:
- Correct EXT_DTB usage for MULTI_DTB_FIT configuration
Convert driver to use spi-mem ops in order to support accelerated MMIO
flash interface in generic way and for better performance.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Now that all boards using TI QSPI have moved to DM and DT, drop non DM
code completely.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
[jagan: update MIGRATION.txt, rebase config_whitelist.txt]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
It seems like the Allwinner SATA driver is already quite capable of
using the driver model, so we can force this on all boards and can
remove support for a non-DM_SCSI build.
This removes the warning about boards with SATA ports not being
DM_SCSI compliant.
It also takes the opportunity to move the driver out of the board/sunxi
directory to join its siblings in drivers/ata, and to make it a proper
Kconfig citizen.
The board defconfigs stay untouched.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
[jagan: select DM_SCSI separately]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Add CLK and RESET support for sun8i_emac driver to
enable TX clock and reset pins via CLK and RESET
framework.
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Lothar Felten <lothar.felten@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Unlike other Allwinner SoC's R40 GMAC clock control register
is locate in CCU, but rest located via syscon itself. Since
the phandle property for current code look for 'syscon' and
it will grab the respective ccu or syscon base address based
on DT property defined in respective SoC dtsi.
So, use the existing 'syscon' code even for R40 for retrieving
GMAC clock via CCU and update the register directly in
sun8i_emac_set_syscon instead of writing it separately using
ccm base.
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Lothar Felten <lothar.felten@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Add CLk support for sunxi_emac to enable AHB_EMAC clock
via CLK framework.
Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
GMAC reset reg offset added by below commit seems to assume
it as EMAC but R40 indeed using GMAC.
"clk: sunxi: Implement EMAC, GMAC clocks, resets"
(sha1: 68620c9698)
So, fix by updating the reg offset for RST_BUS_GMAC.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
The phydev supported features were reset in phy_set_supported() so,
move the setting of driver supported features after this so that it
wont lost in phy_set_supported().
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Post configuration cant be run at u-boot as u-boot
didn't has any info about the design.So,this patch
adds an info message that post config was not run
and needs to be run manually if needed.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The commit 'f48ef0d81aa837a33020f8d61abb3929ba613774' did break I2C
support because requesting the clock for the I2C ip-block isn't
supported during SPL.
To fixup this we add support requesting clocks for:
- i2c0
- i2c1
Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch fixes the tap delay values to be set at 100MHz and 150MHz
as per TRM by fixing the if condition to use <= instead of <.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Ensure the string for filename is always constant, otherwise it can be
corrupted by the writing.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
-----------
- DM support in sata
- Toradex Board to DM
- wandboard to DM
- tbs2910 to DM
- GE boards to DM
- VHybrid boards to DM
- DM_VIDEO for i.MX
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Merge tag 'u-boot-imx-20190415' of git://git.denx.de/u-boot-imx
Move to DM
-----------
- DM support in sata
- Toradex Board to DM
- wandboard to DM
- tbs2910 to DM
- GE boards to DM
- VHybrid boards to DM
- DM_VIDEO for i.MX
- bug fix for ASCII characters > 127
- ANSI sequence handling extensions (implement clear line,
reverse video and relative cursor movement commands)
- preparation for doing character set translations
- left/right and up/down arrow keys translation to ANSI
control sequences for cursor movement to fix selection
with an USB keyboard in bootmenu
- CONFIG_SYS_WHITE_ON_BLACK font scheme configuration for
sunxi boards
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Merge tag 'video-for-2019.07-rc1' of git://git.denx.de/u-boot-video
- optional backlight PWM polarity config via polarity cell
- bug fix for ASCII characters > 127
- ANSI sequence handling extensions (implement clear line,
reverse video and relative cursor movement commands)
- preparation for doing character set translations
- left/right and up/down arrow keys translation to ANSI
control sequences for cursor movement to fix selection
with an USB keyboard in bootmenu
- CONFIG_SYS_WHITE_ON_BLACK font scheme configuration for
sunxi boards
In the sunxi-common.h config header we unconditionally define
CONFIG_SYS_WHITE_ON_BLACK, although it's actually a Kconfig option which
could be individually selected by a user.
Remove this #define from the header and let it default to "y" on sunxi
boards (like we do for other platforms).
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
In preparation for doing character set translations, factor out the
actual glyph display functionality into a separate function.
This will be used in a subsequent patch.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
There is a standard ANSI terminal escape sequence to clear a whole line
of text. So far the DM_VIDEO console was missing this code.
Detect the sequence and use vidconsole_set_row with the background
colour to fix this omission.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The ANSI terminal escapce sequence standard defines relative cursor
movement commands (ESC [ A-F). So far the DM_VIDEO console code was
ignoring them.
Interpret those sequences and move the cursor by the requested amount of
rows or columns in the right direction. This brings the code on par with
the legacy video console driver (cfb_console).
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The video console for DM_VIDEO compliant drivers only understands a very
small number of ANSI sequences. First and foremost it misses the "reverse
video" command, which is used by our own bootmenu command to highlight
the selected entry.
To avoid forcing people to use their imagination when using the
bootmenu, let's just implement the rather simple reverse effect. We need
to store the background colour index for that, so that we can
recalculate both the foreground and background colour pixel values.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[agust: merged BG color escape seq change to fix "ut dm video_ansi" test]
Signed-off-by: Anatolij Gustschin <agust@denx.de>
When the character to be printed on a DM_VIDEO console is from the
"extended ASCII" range (0x80 - 0xff), it will be treated as a negative
number, as it's declared as a signed char. This leads to negative array
indicies into the glyph bitmap array, and random garbled characters.
Cast the character to an unsigned type to make the index always positive
and avoid an out-of-bounds access.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch enables the reading of the polarity cell from a PWM
phandle and calls pwm_set_invert().
Not all platforms have polarity cell, so skip if it's not pressent.
Signed-off-by: Stefan Mavrodiev <stefan@olimex.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
While commit 3e020f03e9 ("driver: misc: add MXC_OCOTP Kconfig entry")
introduced a Kconfig entry it did not actually migrate all
configurations to using it.
As CONFIG_MXC_OCOTP was in mx{6/7}_common.h enable it by default on
those architectures. Additionally, also enable it on ARCH_IMX8M and
ARCH_VF610 where all current members enabled it through their legacy
configuration header files.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Move CONFIG_USB_EHCI_VF to drivers/usb/host/Kconfig and update the one
and only user thereof being colibri_vf.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Spotted two missing spaces in comments.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Extend the driver to build with DM_VIDEO enabled. DTS files
must additionally include 'u-boot,dm-pre-reloc' property in
soc and ipu nodes to enable driver binding to ipu device.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Do not report negative sector numbers for disks > 1TB, do not limit
sector numbers to 32 bit if CONFIG_SYS_64BIT_LBA is enabled.
Signed-off-by: Soeren Moch <smoch@web.de>
The NXP's FEC driver can be reused on vf610 device (with DM).
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Stefan Agner <stefan.agner@toradex.com>
pinctrl race-condition fix
various other fixes in sandbox, sound, mkimage, etc.
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Merge tag 'pull-12apr19' of git://git.denx.de/u-boot-dm
fdtdec tests and improvements for carve-outs
pinctrl race-condition fix
various other fixes in sandbox, sound, mkimage, etc.
- ath79: small fixes, add support for QCA9563 SoC and AP152 reference board
- mscc: small fixes, add network support for JR2 and ServalT SoCs
- bmips: small fixes, enable more drivers for ARM specific BCM6858 and BCM63158 SoCs
- MIPS: fix redundant relocation of initrd images
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Merge tag 'mips-pull-2019-04-12' of git://git.denx.de/u-boot-mips
- mt76xx: add USB support, small fixes
- ath79: small fixes, add support for QCA9563 SoC and AP152 reference board
- mscc: small fixes, add network support for JR2 and ServalT SoCs
- bmips: small fixes, enable more drivers for ARM specific BCM6858 and BCM63158 SoCs
- MIPS: fix redundant relocation of initrd images
- Misc dts files sync'ed with Linux version (Chris)
- Orion watchdog fix (Chris)
- kwbimage changed to also support Marvell bin_hdr binary (Chris)
- Add DM support to enable CONFIG_BLK for sata_mv (Stefan)
- Enable BLK on multiple platforms (Stefan)
- Misc minor fixes to AXP theadorable board (Stefan)
- Correct logic for DM_SCSI + unconverted drivers check (stefan)
- Misc changes to kirkwood to enable DM_USB here (Chris)
- Change ahci_mvebu to enable usage on A38x (Baruch)
- Update the kirkwood entry in git-mailrc (Baruch)
- Misc minor improvements (turris, documentation) (Baruch)
- Enhance sata_mv to support Kirkwood as well (Michael)
- Add wdt command (Michael)
- Add Marvell integrated CPUs (MSYS) support with DB-XC3-24G4XG
board support (Chris)
This driver is derived from this Linux driver:
linux/drivers/phy/ralink/phy-ralink-usb.c
The driver sets up power and host mode, but also needs to configure PHY
registers for the MT7628 and MT7688.
I removed the reset controller handling for the USB host and device, as
it does not seem to be necessary right now. The soft reset bits for both
devices are enabled by default and testing has shown (with hackish
reset handling added), that USB related commands work identical with
or without the reset handling.
Please note that the resulting USB support is tested only very minimal.
I was able to detect one of my 3 currently available USB sticks.
Perhaps some further work is needed to fully support the EHCI controller
integrated in the MT76x8 SoC.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Add network driver for Microsemi Ethernet switch.
It is present on ServalT SoCs.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Add network driver for Microsemi Ethernet switch.
It is present on Jaguar2 SoCs.
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
This driver is used on several big endian mips board.
So we could use raw I/O function instead of forcing
big endian access.
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
S17 ethernet support is for QCA8337N, which used on
AP152 (QCA9563) board. It is a 7 ports GbE switch.
Signed-off-by: Rosy Song <rosysong@rosinson.com>
Changes for v2-v3:
- add more commit message for s17
Changes for v4-v5:
- coding style cleanup
The function mscc_miim_reset resets all the phys, but it is called for
each phy separetely. One consequence of this is that the boot time
is increased by 2 seconds.
The fix consists for calling the mscc_miim_reset function only once for
all phys.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
The driver adds the support for the STMicroelectronics FMC2 NAND
Controller found on STM32MP SOCs.
This patch adds the polling mode, a basic mode that do not need
any DMA channels.
Only NAND_ECC_HW mode is actually supported.
The driver supports a maximum 8k page size.
The following ECC strength and step size are currently supported:
- nand-ecc-strength = <8>, nand-ecc-step-size = <512> (BCH8)
- nand-ecc-strength = <4>, nand-ecc-step-size = <512> (BCH4)
- nand-ecc-strength = <1>, nand-ecc-step-size = <512> (Extended ECC
based on Hamming)
This patch has been tested on Micron MT29F8G08ABACAH4.
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
We are facing issues in the driver since SPI NOR framework has moved
on SPI MEM framework, and SPI NAND framework is not running properly
with the current driver.
To be able to solve issues met on SPI NOR Flashes and to be able to
support SPI NAND Flashes, the driver has been reworked. We are now using
exec_op ops instead of using xfer ops.
Thanks to this rework, the driver has been successfully tested with:
- mx66l51235l SPI NOR Flash on stm32f746 SOC
- n25q128a SPI NOR Flash on stm32f769 SOC
- mx66l51235l SPI NOR Flash on stm32mp1 SOC
- mt29f2g01abagd SPI NAND Flash on stm32mp1 SOC
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
Tested-by: Patrick DELAUNAY <patrick.delaunay@st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com>
This patch adds pinctrl/GPIO driver for STMicroelectronics
Multi-Function eXpander (STMFX) GPIO expander.
STMFX is an I2C slave controller, offering up to 24 GPIOs.
The driver relies on UCLASS_PINCTRL and UCLASS_GPIO.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Add functions to read/update the non volatile memory of STPMIC1
(8 bytes-register at 0xF8 address) and allow access
with fuse command (bank=1, word > 0xF8).
For example:
STM32MP> fuse read 1 0xf8 8
Reading bank 1:
Word 0x000000f8: 000000ee 00000092 000000c0 00000002
Word 0x000000fc: 000000f2 00000080 00000002 00000033
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Alignment with STPMIC1 datasheet
s/MAIN_CONTROL_REG/MAIN_CR/g
s/MASK_RESET_BUCK/BUCKS_MRST_CR/g
s/MASK_RESET_LDOS/LDOS_MRST_CR/g
s/BUCKX_CTRL_REG/BUCKX_MAIN_CR/g
s/VREF_CTRL_REG/REFDDR_MAIN_CR/g
s/LDOX_CTRL_REG/LDOX_MAIN_CR/g
s/USB_CTRL_REG/BST_SW_CR/g
s/STPMIC1_NVM_USER_STATUS_REG/STPMIC1_NVM_SR/g
s/STPMIC1_NVM_USER_CONTROL_REG/STPMIC1_NVM_CR/g
and update all the associated defines.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Alignment with kernel driver name & binding
introduced by https://patchwork.kernel.org/cover/10761943/
to use the final marketing name = STPMIC1.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Prepare file modification for kernel alignment and
rename driver to stpmic1.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
SW impact for Rev 1.2 of STPMIC1 in U-Boot:
Buck converters output voltage change for Buck1
=> Vdd min 0,725 to max 1,5V instead of 0.6V to 1.35V
(see STPMIC1 datasheet / chapter 5.3 Buck converters)
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Add support of trusted boot, using TF-A as first stage bootloader,
The boot sequence is
BootRom >=> TF-A.stm32 (clock & DDR) >=> U-Boot.stm32
The TF-A monitor provides secure monitor with support of SMC
- proprietary to manage secure devices (BSEC for example)
- PSCI for power
The same device tree is used for STMicroelectronics boards with
basic boot and with trusted boot.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
This adds support for the Gigadevice gd25lq128 ID needed on the
upcoming libretech-ac board.
SPI_NOR_QUAD_READ is not set since it has not been tested in Quad
mode.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Pbias voltage should match the IO voltage set for the SD card. With the
latest pbias change to 3.3V, update the capabilities and IO voltages
settings to 3.3V.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
As per recent TRM[1], PBIAS cell on dra7 devices supports
3.3v and not 3.0v as documented earlier.
Update PBIAS regulator max voltage and the voltage written
in the driver to reflect this.
[1] http://www.ti.com/lit/pdf/sprui30
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
The SPL image overflows when cpsw dt nodes are added and SPL_OF_CONTROL
is enabled. Use static platdata instead to save space.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
The ofdata_to_platdata function should not be called if OF_CONTROL is
not enabled because fdtdec_* calls will fail. Block the function with
OF_CONTROL
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
ti_cm_get_macid() is used to get a syscon node from the dt, read the
efuse address and then assign the macid read from the address. Divide
these two steps into separate functions one of which can be called from
ofdata_to_platdata() while the other can be called from _probe(). This
ensures that platdata can be assigned statically in a board file when
OF_CONTROL is not enabled. Also add a macid_sel_compat in private data
to get information about the macid byte placement.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Convert cpsw_platform_data to a pointer in cpsw_priv. Allocate it
dynamically and assign it as a part of eth_pdata. This helps in
isolating platform data handling and implementing platdata for SPL
in a board file.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
