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stpmic1: update register names
Alignment with STPMIC1 datasheet s/MAIN_CONTROL_REG/MAIN_CR/g s/MASK_RESET_BUCK/BUCKS_MRST_CR/g s/MASK_RESET_LDOS/LDOS_MRST_CR/g s/BUCKX_CTRL_REG/BUCKX_MAIN_CR/g s/VREF_CTRL_REG/REFDDR_MAIN_CR/g s/LDOX_CTRL_REG/LDOX_MAIN_CR/g s/USB_CTRL_REG/BST_SW_CR/g s/STPMIC1_NVM_USER_STATUS_REG/STPMIC1_NVM_SR/g s/STPMIC1_NVM_USER_CONTROL_REG/STPMIC1_NVM_CR/g and update all the associated defines. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
This commit is contained in:
Patrick Delaunay
parent
42f01aacfd
commit
db4ff0df65
4 changed files with 125 additions and 107 deletions
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@ -50,39 +50,39 @@ int board_ddr_power_init(void)
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return 0;
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/* VTT = Set LDO3 to sync mode */
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ret = pmic_reg_read(dev, STPMIC1_LDOX_CTRL_REG(STPMIC1_LDO3));
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ret = pmic_reg_read(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3));
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if (ret < 0)
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return ret;
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ret &= ~STPMIC1_LDO3_MODE;
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ret &= ~STPMIC1_LDO12356_OUTPUT_MASK;
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ret |= STPMIC1_LDO3_DDR_SEL << STPMIC1_LDO12356_OUTPUT_SHIFT;
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ret &= ~STPMIC1_LDO12356_VOUT_MASK;
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ret |= STPMIC1_LDO_VOUT(STPMIC1_LDO3_DDR_SEL);
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ret = pmic_reg_write(dev, STPMIC1_LDOX_CTRL_REG(STPMIC1_LDO3),
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ret = pmic_reg_write(dev, STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
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ret);
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if (ret < 0)
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return ret;
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/* VDD_DDR = Set BUCK2 to 1.35V */
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ret = pmic_clrsetbits(dev,
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STPMIC1_BUCKX_CTRL_REG(STPMIC1_BUCK2),
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STPMIC1_BUCK_OUTPUT_MASK,
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STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
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STPMIC1_BUCK_VOUT_MASK,
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STPMIC1_BUCK2_1350000V);
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if (ret < 0)
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return ret;
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/* Enable VDD_DDR = BUCK2 */
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ret = pmic_clrsetbits(dev,
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STPMIC1_BUCKX_CTRL_REG(STPMIC1_BUCK2),
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STPMIC1_BUCK_EN, STPMIC1_BUCK_EN);
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STPMIC1_BUCKX_MAIN_CR(STPMIC1_BUCK2),
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STPMIC1_BUCK_ENA, STPMIC1_BUCK_ENA);
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if (ret < 0)
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return ret;
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mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
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/* Enable VREF */
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ret = pmic_clrsetbits(dev, STPMIC1_VREF_CTRL_REG,
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STPMIC1_VREF_EN, STPMIC1_VREF_EN);
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ret = pmic_clrsetbits(dev, STPMIC1_REFDDR_MAIN_CR,
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STPMIC1_VREF_ENA, STPMIC1_VREF_ENA);
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if (ret < 0)
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return ret;
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@ -90,8 +90,8 @@ int board_ddr_power_init(void)
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/* Enable LDO3 */
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ret = pmic_clrsetbits(dev,
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STPMIC1_LDOX_CTRL_REG(STPMIC1_LDO3),
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STPMIC1_LDO_EN, STPMIC1_LDO_EN);
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STPMIC1_LDOX_MAIN_CR(STPMIC1_LDO3),
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STPMIC1_LDO_ENA, STPMIC1_LDO_ENA);
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if (ret < 0)
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return ret;
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@ -25,8 +25,8 @@ void spl_board_init(void)
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DM_GET_DRIVER(pmic_stpmic1), &dev);
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if (!ret)
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pmic_clrsetbits(dev,
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STPMIC1_MASK_RESET_BUCK,
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STPMIC1_MASK_RESET_BUCK3,
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STPMIC1_MASK_RESET_BUCK3);
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STPMIC1_BUCKS_MRST_CR,
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STPMIC1_MRST_BUCK(STPMIC1_BUCK3),
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STPMIC1_MRST_BUCK(STPMIC1_BUCK3));
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#endif
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}
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@ -132,20 +132,20 @@ static const struct stpmic1_output buck_voltage_range[] = {
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/* BUCK modes */
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static const struct dm_regulator_mode buck_modes[] = {
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STPMIC1_MODE(STPMIC1_BUCK_MODE_HP, STPMIC1_BUCK_MODE_HP, "HP"),
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STPMIC1_MODE(STPMIC1_BUCK_MODE_LP, STPMIC1_BUCK_MODE_LP, "LP"),
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STPMIC1_MODE(STPMIC1_PREG_MODE_HP, STPMIC1_PREG_MODE_HP, "HP"),
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STPMIC1_MODE(STPMIC1_PREG_MODE_LP, STPMIC1_PREG_MODE_LP, "LP"),
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};
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static int stpmic1_buck_get_uv(struct udevice *dev, int buck)
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{
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int sel;
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sel = pmic_reg_read(dev, STPMIC1_BUCKX_CTRL_REG(buck));
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sel = pmic_reg_read(dev, STPMIC1_BUCKX_MAIN_CR(buck));
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if (sel < 0)
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return sel;
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sel &= STPMIC1_BUCK_OUTPUT_MASK;
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sel >>= STPMIC1_BUCK_OUTPUT_SHIFT;
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sel &= STPMIC1_BUCK_VOUT_MASK;
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sel >>= STPMIC1_BUCK_VOUT_SHIFT;
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return stpmic1_output_find_uv(sel, &buck_voltage_range[buck]);
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}
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@ -164,9 +164,9 @@ static int stpmic1_buck_set_value(struct udevice *dev, int uv)
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return sel;
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return pmic_clrsetbits(dev->parent,
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STPMIC1_BUCKX_CTRL_REG(buck),
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STPMIC1_BUCK_OUTPUT_MASK,
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sel << STPMIC1_BUCK_OUTPUT_SHIFT);
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STPMIC1_BUCKX_MAIN_CR(buck),
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STPMIC1_BUCK_VOUT_MASK,
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sel << STPMIC1_BUCK_VOUT_SHIFT);
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}
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static int stpmic1_buck_get_enable(struct udevice *dev)
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@ -174,11 +174,11 @@ static int stpmic1_buck_get_enable(struct udevice *dev)
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int ret;
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ret = pmic_reg_read(dev->parent,
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STPMIC1_BUCKX_CTRL_REG(dev->driver_data - 1));
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STPMIC1_BUCKX_MAIN_CR(dev->driver_data - 1));
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if (ret < 0)
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return false;
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return ret & STPMIC1_BUCK_EN ? true : false;
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return ret & STPMIC1_BUCK_ENA ? true : false;
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}
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static int stpmic1_buck_set_enable(struct udevice *dev, bool enable)
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@ -200,8 +200,8 @@ static int stpmic1_buck_set_enable(struct udevice *dev, bool enable)
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}
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ret = pmic_clrsetbits(dev->parent,
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STPMIC1_BUCKX_CTRL_REG(dev->driver_data - 1),
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STPMIC1_BUCK_EN, enable ? STPMIC1_BUCK_EN : 0);
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STPMIC1_BUCKX_MAIN_CR(dev->driver_data - 1),
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STPMIC1_BUCK_ENA, enable ? STPMIC1_BUCK_ENA : 0);
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mdelay(delay);
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return ret;
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@ -212,20 +212,20 @@ static int stpmic1_buck_get_mode(struct udevice *dev)
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int ret;
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ret = pmic_reg_read(dev->parent,
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STPMIC1_BUCKX_CTRL_REG(dev->driver_data - 1));
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STPMIC1_BUCKX_MAIN_CR(dev->driver_data - 1));
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if (ret < 0)
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return ret;
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return ret & STPMIC1_BUCK_MODE ? STPMIC1_BUCK_MODE_LP :
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STPMIC1_BUCK_MODE_HP;
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return ret & STPMIC1_BUCK_PREG_MODE ? STPMIC1_PREG_MODE_LP :
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STPMIC1_PREG_MODE_HP;
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}
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static int stpmic1_buck_set_mode(struct udevice *dev, int mode)
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{
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return pmic_clrsetbits(dev->parent,
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STPMIC1_BUCKX_CTRL_REG(dev->driver_data - 1),
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STPMIC1_BUCK_MODE,
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mode ? STPMIC1_BUCK_MODE : 0);
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STPMIC1_BUCKX_MAIN_CR(dev->driver_data - 1),
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STPMIC1_BUCK_PREG_MODE,
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mode ? STPMIC1_BUCK_PREG_MODE : 0);
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}
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static int stpmic1_buck_probe(struct udevice *dev)
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@ -312,7 +312,7 @@ static int stpmic1_ldo_get_value(struct udevice *dev)
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{
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int sel, ldo = dev->driver_data - 1;
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sel = pmic_reg_read(dev->parent, STPMIC1_LDOX_CTRL_REG(ldo));
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sel = pmic_reg_read(dev->parent, STPMIC1_LDOX_MAIN_CR(ldo));
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if (sel < 0)
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return sel;
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@ -320,8 +320,8 @@ static int stpmic1_ldo_get_value(struct udevice *dev)
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if (ldo == STPMIC1_LDO4)
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return STPMIC1_LDO4_UV;
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sel &= STPMIC1_LDO12356_OUTPUT_MASK;
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sel >>= STPMIC1_LDO12356_OUTPUT_SHIFT;
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sel &= STPMIC1_LDO12356_VOUT_MASK;
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sel >>= STPMIC1_LDO12356_VOUT_SHIFT;
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/* ldo3, sel = 31 => BUCK2/2 */
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if (ldo == STPMIC1_LDO3 && sel == STPMIC1_LDO3_DDR_SEL)
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@ -343,9 +343,9 @@ static int stpmic1_ldo_set_value(struct udevice *dev, int uv)
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return sel;
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return pmic_clrsetbits(dev->parent,
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STPMIC1_LDOX_CTRL_REG(ldo),
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STPMIC1_LDO12356_OUTPUT_MASK,
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sel << STPMIC1_LDO12356_OUTPUT_SHIFT);
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STPMIC1_LDOX_MAIN_CR(ldo),
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STPMIC1_LDO12356_VOUT_MASK,
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sel << STPMIC1_LDO12356_VOUT_SHIFT);
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}
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static int stpmic1_ldo_get_enable(struct udevice *dev)
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@ -353,11 +353,11 @@ static int stpmic1_ldo_get_enable(struct udevice *dev)
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int ret;
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ret = pmic_reg_read(dev->parent,
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STPMIC1_LDOX_CTRL_REG(dev->driver_data - 1));
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STPMIC1_LDOX_MAIN_CR(dev->driver_data - 1));
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if (ret < 0)
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return false;
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return ret & STPMIC1_LDO_EN ? true : false;
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return ret & STPMIC1_LDO_ENA ? true : false;
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}
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static int stpmic1_ldo_set_enable(struct udevice *dev, bool enable)
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@ -379,8 +379,8 @@ static int stpmic1_ldo_set_enable(struct udevice *dev, bool enable)
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}
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ret = pmic_clrsetbits(dev->parent,
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STPMIC1_LDOX_CTRL_REG(dev->driver_data - 1),
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STPMIC1_LDO_EN, enable ? STPMIC1_LDO_EN : 0);
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STPMIC1_LDOX_MAIN_CR(dev->driver_data - 1),
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STPMIC1_LDO_ENA, enable ? STPMIC1_LDO_ENA : 0);
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mdelay(delay);
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return ret;
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@ -393,15 +393,15 @@ static int stpmic1_ldo_get_mode(struct udevice *dev)
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if (ldo != STPMIC1_LDO3)
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return -EINVAL;
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ret = pmic_reg_read(dev->parent, STPMIC1_LDOX_CTRL_REG(ldo));
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ret = pmic_reg_read(dev->parent, STPMIC1_LDOX_MAIN_CR(ldo));
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if (ret < 0)
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return ret;
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if (ret & STPMIC1_LDO3_MODE)
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return STPMIC1_LDO_MODE_BYPASS;
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ret &= STPMIC1_LDO12356_OUTPUT_MASK;
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ret >>= STPMIC1_LDO12356_OUTPUT_SHIFT;
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ret &= STPMIC1_LDO12356_VOUT_MASK;
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ret >>= STPMIC1_LDO12356_VOUT_SHIFT;
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return ret == STPMIC1_LDO3_DDR_SEL ? STPMIC1_LDO_MODE_SINK_SOURCE :
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STPMIC1_LDO_MODE_NORMAL;
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@ -414,14 +414,14 @@ static int stpmic1_ldo_set_mode(struct udevice *dev, int mode)
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if (ldo != STPMIC1_LDO3)
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return -EINVAL;
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ret = pmic_reg_read(dev->parent, STPMIC1_LDOX_CTRL_REG(ldo));
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ret = pmic_reg_read(dev->parent, STPMIC1_LDOX_MAIN_CR(ldo));
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if (ret < 0)
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return ret;
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switch (mode) {
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case STPMIC1_LDO_MODE_SINK_SOURCE:
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ret &= ~STPMIC1_LDO12356_OUTPUT_MASK;
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ret |= STPMIC1_LDO3_DDR_SEL << STPMIC1_LDO12356_OUTPUT_SHIFT;
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ret &= ~STPMIC1_LDO12356_VOUT_MASK;
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ret |= STPMIC1_LDO3_DDR_SEL << STPMIC1_LDO12356_VOUT_SHIFT;
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case STPMIC1_LDO_MODE_NORMAL:
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ret &= ~STPMIC1_LDO3_MODE;
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break;
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@ -430,7 +430,7 @@ static int stpmic1_ldo_set_mode(struct udevice *dev, int mode)
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break;
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}
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return pmic_reg_write(dev->parent, STPMIC1_LDOX_CTRL_REG(ldo), ret);
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return pmic_reg_write(dev->parent, STPMIC1_LDOX_MAIN_CR(ldo), ret);
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}
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static int stpmic1_ldo_probe(struct udevice *dev)
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@ -483,11 +483,11 @@ static int stpmic1_vref_ddr_get_enable(struct udevice *dev)
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{
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int ret;
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ret = pmic_reg_read(dev->parent, STPMIC1_VREF_CTRL_REG);
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ret = pmic_reg_read(dev->parent, STPMIC1_REFDDR_MAIN_CR);
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if (ret < 0)
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return false;
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return ret & STPMIC1_VREF_EN ? true : false;
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return ret & STPMIC1_VREF_ENA ? true : false;
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}
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static int stpmic1_vref_ddr_set_enable(struct udevice *dev, bool enable)
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@ -500,8 +500,8 @@ static int stpmic1_vref_ddr_set_enable(struct udevice *dev, bool enable)
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if (stpmic1_vref_ddr_get_enable(dev) == enable)
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return 0;
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ret = pmic_clrsetbits(dev->parent, STPMIC1_VREF_CTRL_REG,
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STPMIC1_VREF_EN, enable ? STPMIC1_VREF_EN : 0);
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ret = pmic_clrsetbits(dev->parent, STPMIC1_REFDDR_MAIN_CR,
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STPMIC1_VREF_ENA, enable ? STPMIC1_VREF_ENA : 0);
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mdelay(delay);
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return ret;
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@ -540,31 +540,31 @@ static int stpmic1_boost_get_enable(struct udevice *dev)
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{
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int ret;
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ret = pmic_reg_read(dev->parent, STPMIC1_USB_CTRL_REG);
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ret = pmic_reg_read(dev->parent, STPMIC1_BST_SW_CR);
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if (ret < 0)
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return false;
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return ret & STPMIC1_USB_BOOST_EN ? true : false;
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return ret & STPMIC1_BST_ON ? true : false;
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}
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static int stpmic1_boost_set_enable(struct udevice *dev, bool enable)
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{
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int ret;
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ret = pmic_reg_read(dev->parent, STPMIC1_USB_CTRL_REG);
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ret = pmic_reg_read(dev->parent, STPMIC1_BST_SW_CR);
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if (ret < 0)
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return ret;
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if (!enable && ret & STPMIC1_USB_PWR_SW_EN)
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if (!enable && ret & STPMIC1_PWR_SW_ON)
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return -EINVAL;
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/* if regulator is already in the wanted state, nothing to do */
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if (!!(ret & STPMIC1_USB_BOOST_EN) == enable)
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if (!!(ret & STPMIC1_BST_ON) == enable)
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return 0;
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ret = pmic_clrsetbits(dev->parent, STPMIC1_USB_CTRL_REG,
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STPMIC1_USB_BOOST_EN,
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enable ? STPMIC1_USB_BOOST_EN : 0);
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ret = pmic_clrsetbits(dev->parent, STPMIC1_BST_SW_CR,
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STPMIC1_BST_ON,
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enable ? STPMIC1_BST_ON : 0);
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if (enable)
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mdelay(STPMIC1_USB_BOOST_START_UP_DELAY_MS);
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@ -604,7 +604,7 @@ static int stpmic1_pwr_sw_get_enable(struct udevice *dev)
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uint mask = 1 << dev->driver_data;
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int ret;
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ret = pmic_reg_read(dev->parent, STPMIC1_USB_CTRL_REG);
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ret = pmic_reg_read(dev->parent, STPMIC1_BST_SW_CR);
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if (ret < 0)
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return false;
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@ -618,7 +618,7 @@ static int stpmic1_pwr_sw_set_enable(struct udevice *dev, bool enable)
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STPMIC1_DEFAULT_STOP_DELAY_MS;
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int ret;
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ret = pmic_reg_read(dev->parent, STPMIC1_USB_CTRL_REG);
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ret = pmic_reg_read(dev->parent, STPMIC1_BST_SW_CR);
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if (ret < 0)
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return ret;
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@ -627,17 +627,17 @@ static int stpmic1_pwr_sw_set_enable(struct udevice *dev, bool enable)
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return 0;
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/* Boost management */
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if (enable && !(ret & STPMIC1_USB_BOOST_EN)) {
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pmic_clrsetbits(dev->parent, STPMIC1_USB_CTRL_REG,
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STPMIC1_USB_BOOST_EN, STPMIC1_USB_BOOST_EN);
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if (enable && !(ret & STPMIC1_BST_ON)) {
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pmic_clrsetbits(dev->parent, STPMIC1_BST_SW_CR,
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STPMIC1_BST_ON, STPMIC1_BST_ON);
|
||||
mdelay(STPMIC1_USB_BOOST_START_UP_DELAY_MS);
|
||||
} else if (!enable && ret & STPMIC1_USB_BOOST_EN &&
|
||||
(ret & STPMIC1_USB_PWR_SW_EN) != STPMIC1_USB_PWR_SW_EN) {
|
||||
pmic_clrsetbits(dev->parent, STPMIC1_USB_CTRL_REG,
|
||||
STPMIC1_USB_BOOST_EN, 0);
|
||||
} else if (!enable && ret & STPMIC1_BST_ON &&
|
||||
(ret & STPMIC1_PWR_SW_ON) != STPMIC1_PWR_SW_ON) {
|
||||
pmic_clrsetbits(dev->parent, STPMIC1_BST_SW_CR,
|
||||
STPMIC1_BST_ON, 0);
|
||||
}
|
||||
|
||||
ret = pmic_clrsetbits(dev->parent, STPMIC1_USB_CTRL_REG,
|
||||
ret = pmic_clrsetbits(dev->parent, STPMIC1_BST_SW_CR,
|
||||
mask, enable ? mask : 0);
|
||||
mdelay(delay);
|
||||
|
||||
|
|
|
|||
|
|
@ -6,51 +6,69 @@
|
|||
#ifndef __PMIC_STPMIC1_H_
|
||||
#define __PMIC_STPMIC1_H_
|
||||
|
||||
#define STPMIC1_MAIN_CONTROL_REG 0x10
|
||||
#define STPMIC1_MASK_RESET_BUCK 0x18
|
||||
#define STPMIC1_MASK_RESET_LDOS 0x1a
|
||||
#define STPMIC1_BUCKX_CTRL_REG(buck) (0x20 + (buck))
|
||||
#define STPMIC1_VREF_CTRL_REG 0x24
|
||||
#define STPMIC1_LDOX_CTRL_REG(ldo) (0x25 + (ldo))
|
||||
#define STPMIC1_USB_CTRL_REG 0x40
|
||||
#define STPMIC1_NVM_USER_STATUS_REG 0xb8
|
||||
#define STPMIC1_NVM_USER_CONTROL_REG 0xb9
|
||||
#define STPMIC1_MAIN_CR 0x10
|
||||
#define STPMIC1_BUCKS_MRST_CR 0x18
|
||||
#define STPMIC1_LDOS_MRST_CR 0x1a
|
||||
#define STPMIC1_BUCKX_MAIN_CR(buck) (0x20 + (buck))
|
||||
#define STPMIC1_REFDDR_MAIN_CR 0x24
|
||||
#define STPMIC1_LDOX_MAIN_CR(ldo) (0x25 + (ldo))
|
||||
#define STPMIC1_BST_SW_CR 0x40
|
||||
#define STPMIC1_NVM_SR 0xb8
|
||||
#define STPMIC1_NVM_CR 0xb9
|
||||
|
||||
/* Main PMIC Control Register (MAIN_CONTROL_REG) */
|
||||
#define STPMIC1_CTRL_SWITCH_OFF BIT(0)
|
||||
#define STPMIC1_CTRL_RESTART BIT(1)
|
||||
/* Main PMIC Control Register (MAIN_CR) */
|
||||
#define STPMIC1_SWOFF BIT(0)
|
||||
#define STPMIC1_RREQ_EN BIT(1)
|
||||
|
||||
#define STPMIC1_MASK_RESET_BUCK3 BIT(2)
|
||||
#define STPMIC1_MASK_RESET_BUCK_DBG GENMASK(3, 0)
|
||||
#define STPMIC1_MASK_RESET_LDOS_DBG 0x6F
|
||||
/* BUCKS_MRST_CR */
|
||||
#define STPMIC1_MRST_BUCK(buck) BIT(buck)
|
||||
#define STPMIC1_MRST_BUCK_ALL GENMASK(3, 0)
|
||||
|
||||
#define STPMIC1_BUCK_EN BIT(0)
|
||||
#define STPMIC1_BUCK_MODE BIT(1)
|
||||
#define STPMIC1_BUCK_OUTPUT_MASK GENMASK(7, 2)
|
||||
#define STPMIC1_BUCK_OUTPUT_SHIFT 2
|
||||
#define STPMIC1_BUCK2_1200000V (24 << STPMIC1_BUCK_OUTPUT_SHIFT)
|
||||
#define STPMIC1_BUCK2_1350000V (30 << STPMIC1_BUCK_OUTPUT_SHIFT)
|
||||
#define STPMIC1_BUCK3_1800000V (39 << STPMIC1_BUCK_OUTPUT_SHIFT)
|
||||
/* LDOS_MRST_CR */
|
||||
#define STPMIC1_MRST_LDO(ldo) BIT(ldo)
|
||||
#define STPMIC1_MRST_LDO_ALL GENMASK(6, 0)
|
||||
|
||||
#define STPMIC1_VREF_EN BIT(0)
|
||||
/* BUCKx_MAIN_CR (x=1...4) */
|
||||
#define STPMIC1_BUCK_ENA BIT(0)
|
||||
#define STPMIC1_BUCK_PREG_MODE BIT(1)
|
||||
#define STPMIC1_BUCK_VOUT_MASK GENMASK(7, 2)
|
||||
#define STPMIC1_BUCK_VOUT_SHIFT 2
|
||||
#define STPMIC1_BUCK_VOUT(sel) (sel << STPMIC1_BUCK_VOUT_SHIFT)
|
||||
|
||||
#define STPMIC1_BUCK2_1200000V STPMIC1_BUCK_VOUT(24)
|
||||
#define STPMIC1_BUCK2_1350000V STPMIC1_BUCK_VOUT(30)
|
||||
|
||||
#define STPMIC1_BUCK3_1800000V STPMIC1_BUCK_VOUT(39)
|
||||
|
||||
/* REFDDR_MAIN_CR */
|
||||
#define STPMIC1_VREF_ENA BIT(0)
|
||||
|
||||
/* LDOX_MAIN_CR */
|
||||
#define STPMIC1_LDO_ENA BIT(0)
|
||||
#define STPMIC1_LDO12356_VOUT_MASK GENMASK(6, 2)
|
||||
#define STPMIC1_LDO12356_VOUT_SHIFT 2
|
||||
#define STPMIC1_LDO_VOUT(sel) (sel << STPMIC1_LDO12356_VOUT_SHIFT)
|
||||
|
||||
#define STPMIC1_LDO_EN BIT(0)
|
||||
#define STPMIC1_LDO12356_OUTPUT_MASK GENMASK(6, 2)
|
||||
#define STPMIC1_LDO12356_OUTPUT_SHIFT 2
|
||||
#define STPMIC1_LDO3_MODE BIT(7)
|
||||
#define STPMIC1_LDO3_DDR_SEL 31
|
||||
#define STPMIC1_LDO3_1800000 (9 << STPMIC1_LDO12356_OUTPUT_SHIFT)
|
||||
#define STPMIC1_LDO3_1800000 STPMIC1_LDO_VOUT(9)
|
||||
|
||||
#define STPMIC1_LDO4_UV 3300000
|
||||
|
||||
#define STPMIC1_USB_BOOST_EN BIT(0)
|
||||
#define STPMIC1_USB_PWR_SW_EN GENMASK(2, 1)
|
||||
/* BST_SW_CR */
|
||||
#define STPMIC1_BST_ON BIT(0)
|
||||
#define STPMIC1_VBUSOTG_ON BIT(1)
|
||||
#define STPMIC1_SWOUT_ON BIT(2)
|
||||
#define STPMIC1_PWR_SW_ON (STPMIC1_VBUSOTG_ON | STPMIC1_SWOUT_ON)
|
||||
|
||||
#define STPMIC1_NVM_USER_CONTROL_PROGRAM BIT(0)
|
||||
#define STPMIC1_NVM_USER_CONTROL_READ BIT(1)
|
||||
/* NVM_SR */
|
||||
#define STPMIC1_NVM_BUSY BIT(0)
|
||||
|
||||
#define STPMIC1_NVM_USER_STATUS_BUSY BIT(0)
|
||||
#define STPMIC1_NVM_USER_STATUS_ERROR BIT(1)
|
||||
/* NVM_CR */
|
||||
#define STPMIC1_NVM_CMD_PROGRAM 1
|
||||
#define STPMIC1_NVM_CMD_READ 2
|
||||
|
||||
/* Timeout */
|
||||
#define STPMIC1_DEFAULT_START_UP_DELAY_MS 1
|
||||
#define STPMIC1_DEFAULT_STOP_DELAY_MS 5
|
||||
#define STPMIC1_USB_BOOST_START_UP_DELAY_MS 10
|
||||
|
|
@ -64,8 +82,8 @@ enum {
|
|||
};
|
||||
|
||||
enum {
|
||||
STPMIC1_BUCK_MODE_HP,
|
||||
STPMIC1_BUCK_MODE_LP,
|
||||
STPMIC1_PREG_MODE_HP,
|
||||
STPMIC1_PREG_MODE_LP,
|
||||
};
|
||||
|
||||
enum {
|
||||
|
|
|
|||
Loading…
Reference in a new issue